[WebAssembly] SIMD integer abs instructions

[tlively]

Summary

These were merged to the SIMD proposal in
https://github.com/WebAssembly/simd/pull/128.

Depends on D76397 to avoid merge conflicts.

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

130

Out of curiosity, before this patch, how was ISD::ABS lowered, given that there's no mention of lowering ABS in this file? If it was expanded, wasn't something like setOperationAction(ISD::ABS, T, Expand) supposed to be in this file?

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

130

ABS is one of the nodes that are expanded by default in TargetLoweringBase: https://github.com/llvm/llvm-project/blob/master/llvm/lib/CodeGen/TargetLoweringBase.cpp#L638-L666

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

WebAssemblyTargetLowering::WebAssemblyTargetLowering(
 
   // SIMD-specific configuration
   if (Subtarget->hasSIMD128()) {
     // Support saturating add for i8x16 and i16x8
     for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
       for (auto T : {MVT::v16i8, MVT::v8i16})
         setOperationAction(Op, T, Legal);
 
+    // Support integer abs
+    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+      setOperationAction(ISD::ABS, T, Legal);
+
     // Custom lower BUILD_VECTORs to minimize number of replace_lanes
     for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
                    MVT::v2f64})
       setOperationAction(ISD::BUILD_VECTOR, T, Custom);
 
     // We have custom shuffle lowering to expose the shuffle mask
     for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
                    MVT::v2f64})

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
   defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 17)>;
   defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 34)>;
   defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 51)>;
 }
 
 // Integer vector negation
 def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
 
+// Integer absolute value: abs
+defm ABS : SIMDUnary<v16i8, "i8x16", abs, "abs", 225>;
+defm ABS : SIMDUnary<v8i16, "i16x8", abs, "abs", 226>;
+defm ABS : SIMDUnary<v4i32, "i32x4", abs, "abs", 227>;
+
 // Integer negation: neg
 defm NEG : SIMDUnaryInt<ivneg, "neg", 81>;
 
 // Any lane true: any_true
 defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 82>;
 
 // All lanes true: all_true
 defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 83>;

llvm/test/CodeGen/WebAssembly/simd-arith.ll

define <16 x i8> @avgr_u_v16i8_wrap(<16 x i8> %x, <16 x i8> %y) {
   %a = add <16 x i8> %x, %y
   %b = add <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
                           i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %c = udiv <16 x i8> %b, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2,
                            i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
   ret <16 x i8> %c
 }
 
+; CHECK-LABEL: abs_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128-NEXT: .functype abs_v16i8 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i8x16.abs $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @abs_v16i8(<16 x i8> %x) {
+  %a = sub <16 x i8> zeroinitializer, %x
+  %b = icmp slt <16 x i8> %x, zeroinitializer
+  %c = select <16 x i1> %b, <16 x i8> %a, <16 x i8> %x
+  ret <16 x i8> %c
+}
+
 ; CHECK-LABEL: neg_v16i8:
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype neg_v16i8 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @neg_v16i8(<16 x i8> %x) {
   %a = sub <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0,
                       i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>,

 ; SIMD128-NOT: i16x8.avgr_u
 define <8 x i16> @avgr_u_v8i16_wrap(<8 x i16> %x, <8 x i16> %y) {
   %a = add <8 x i16> %x, %y
   %b = add <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %c = udiv <8 x i16> %b, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
   ret <8 x i16> %c
 }
 
+; CHECK-LABEL: abs_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128-NEXT: .functype abs_v8i16 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.abs $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @abs_v8i16(<8 x i16> %x) {
+  %a = sub <8 x i16> zeroinitializer, %x
+  %b = icmp slt <8 x i16> %x, zeroinitializer
+  %c = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %x
+  ret <8 x i16> %c
+}
+
 ; CHECK-LABEL: neg_v8i16:
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128-NEXT: .functype neg_v8i16 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i16x8.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @neg_v8i16(<8 x i16> %x) {
   %a = sub <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>,
                      %x

 ; SIMD128-NEXT: i32x4.max_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @max_u_v4i32(<4 x i32> %x, <4 x i32> %y) {
   %c = icmp ugt <4 x i32> %x, %y
   %a = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %y
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: abs_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .functype abs_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.abs $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @abs_v4i32(<4 x i32> %x) {
+  %a = sub <4 x i32> zeroinitializer, %x
+  %b = icmp slt <4 x i32> %x, zeroinitializer
+  %c = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %x
+  ret <4 x i32> %c
+}
+
 ; CHECK-LABEL: neg_v4i32:
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128-NEXT: .functype neg_v4i32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @neg_v4i32(<4 x i32> %x) {
   %a = sub <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %x
   ret <4 x i32> %a

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     i8x16.avgr_u
 
     # CHECK: i16x8.avgr_u # encoding: [0xfd,0xda,0x01]
     i16x8.avgr_u
 
     # CHECK: i32x4.dot_i16x8_s # encoding: [0xfd,0xdb,0x01]
     i32x4.dot_i16x8_s
 
+    # CHECK: i8x16.abs # encoding: [0xfd,0xe1,0x01]
+    i8x16.abs
+
+    # CHECK: i16x8.abs # encoding: [0xfd,0xe2,0x01]
+    i16x8.abs
+
+    # CHECK: i32x4.abs # encoding: [0xfd,0xe3,0x01]
+    i32x4.abs
+
     # CHECK: i8x16.bitmask # encoding: [0xfd,0xe4,0x01]
     i8x16.bitmask
 
     # CHECK: i16x8.bitmask # encoding: [0xfd,0xe5,0x01]
     i16x8.bitmask
 
     # CHECK: i32x4.bitmask # encoding: [0xfd,0xe6,0x01]
     i32x4.bitmask
 
     end_function