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[AMDGPU] Reuse register during frame index elimination
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Authored by kerbowa on Wed, Mar 18, 2:37 PM.

Details

Summary

If there were no free VGPRs we would need two emergency spill slots for register
scavenging during PEI/frame index elimination. Reuse 'ResultReg' for scale
calculation so that only one spill is needed.

Diff Detail

Event Timeline

kerbowa created this revision.Wed, Mar 18, 2:37 PM
arsenm added inline comments.Wed, Mar 18, 2:47 PM
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
1144–1145

Typo Resue

llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
3

Add other subtarget run lines to catch the different add handling?

24

I assume these live ins are just to force all registers to be live? I think this will break when things are finally inverted to scavenge from the end of the block. I think there should also be an implicit use on the S_ENDPGM (I think you can use the all VGPR reg mask to shorten it)

38

We ended up with an add of 0 which doesn't seem ideal

craig.topper added inline comments.
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
1144–1145

Same typo exists in the review title too

kerbowa updated this revision to Diff 251248.Wed, Mar 18, 7:57 PM

Address review comments.

kerbowa retitled this revision from [AMDGPU] Resue register during frame index elimination to [AMDGPU] Reuse register during frame index elimination.Wed, Mar 18, 7:58 PM
kerbowa marked 7 inline comments as done.Wed, Mar 18, 8:04 PM
kerbowa added inline comments.
llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
24

Is csr_amdgpu_allvgprs the mask you are referring to?

38

I don't think I see an add of 0.

kerbowa updated this revision to Diff 251294.Thu, Mar 19, 12:03 AM
kerbowa marked 2 inline comments as done.

Rebase tests.

arsenm accepted this revision.Thu, Mar 19, 2:45 PM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
24

Yes, though the CSR part is misleading

38

Oh right, I got confused by the clamp immediate

This revision is now accepted and ready to land.Thu, Mar 19, 2:45 PM
This revision was automatically updated to reflect the committed changes.