[x86] Enable bypassing 64-bit division on generic x86-64

[atdt]

Summary

This is currently enabled for Intel big cores from Sandy Bridge onward, as well as Atom, Silvermont, and KNL, due to 64-bit division being so slow on these cores. AMD cores can do this in hardware (use 32-bit division based on input operand width), so it's not a win there. But since the majority of x86 CPUs benefit from this optimization, and since the potential upside is significantly greater than the downside, we should enable this for the generic x86-64 target.

[RKSimon]

Test cases?

@craig.topper Any objections?

[atdt]

In D75567#1959215, @RKSimon wrote:

Test cases?

I'm not sure what kind of test case to add. The codegen tests for bypassing slow division use -mattr=[+-]idivq-to-divl to explicitly control this feature, rather than assume it is enabled or disabled for a particular target.

[craig.topper]

I don't have any objections

[RKSimon]

In D75567#1959903, @atdt wrote:

In D75567#1959215, @RKSimon wrote:

Test cases?

I'm not sure what kind of test case to add. The codegen tests for bypassing slow division use -mattr=[+-]idivq-to-divl to explicitly control this feature, rather than assume it is enabled or disabled for a particular target.

In which case we probably just need to add an additional -mcpu=x86-64 test to bypass-slow-division-tune.ll ?

[atdt]

Update unit test for bypassing 64-bit division on generic x86-64

[craig.topper]

LGTM

[RKSimon]

LGTM - cheers

[atdt]

Thanks! I can't commit this myself.

llvm/lib/Target/X86/X86.td

def : ProcessorModel<"x86-64", SandyBridgeModel, [
   FeatureCMPXCHG8B,
   FeatureCMOV,
   FeatureMMX,
   FeatureSSE2,
   FeatureFXSR,
   FeatureNOPL,
   Feature64Bit,
   FeatureSlow3OpsLEA,
+  FeatureSlowDivide64,
   FeatureSlowIncDec,
   FeatureMacroFusion,
   FeatureInsertVZEROUPPER
 ]>;
 
 //===----------------------------------------------------------------------===//
 // Calling Conventions
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/X86/bypass-slow-division-tune.ll

 ; ATOM-NEXT:    xorl %edx, %edx
 ; ATOM-NEXT:    divl %esi
 ; ATOM-NEXT:    # kill: def $eax killed $eax def $rax
 ; ATOM-NEXT:    retq
 ;
 ; X64-LABEL: div64:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    movq %rdi, %rcx
+; X64-NEXT:    orq %rsi, %rcx
+; X64-NEXT:    shrq $32, %rcx
+; X64-NEXT:    je .LBB1_1
+; X64-NEXT:  # %bb.2:
 ; X64-NEXT:    cqto
 ; X64-NEXT:    idivq %rsi
 ; X64-NEXT:    retq
+; X64-NEXT:  .LBB1_1:
+; X64-NEXT:    # kill: def $eax killed $eax killed $rax
+; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    divl %esi
+; X64-NEXT:    # kill: def $eax killed $eax def $rax
+; X64-NEXT:    retq
 ;
 ; SLM-LABEL: div64:
 ; SLM:       # %bb.0: # %entry
 ; SLM-NEXT:    movq %rdi, %rcx
 ; SLM-NEXT:    movq %rdi, %rax
 ; SLM-NEXT:    orq %rsi, %rcx
 ; SLM-NEXT:    shrq $32, %rcx
 ; SLM-NEXT:    je .LBB1_1

 ; ATOM-NEXT:    xorl %edx, %edx
 ; ATOM-NEXT:    divl %esi
 ; ATOM-NEXT:    # kill: def $eax killed $eax def $rax
 ; ATOM-NEXT:    retq
 ;
 ; X64-LABEL: div64_hugews:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    movq %rdi, %rcx
+; X64-NEXT:    orq %rsi, %rcx
+; X64-NEXT:    shrq $32, %rcx
+; X64-NEXT:    je .LBB4_1
+; X64-NEXT:  # %bb.2:
 ; X64-NEXT:    cqto
 ; X64-NEXT:    idivq %rsi
 ; X64-NEXT:    retq
+; X64-NEXT:  .LBB4_1:
+; X64-NEXT:    # kill: def $eax killed $eax killed $rax
+; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    divl %esi
+; X64-NEXT:    # kill: def $eax killed $eax def $rax
+; X64-NEXT:    retq
 ;
 ; SLM-LABEL: div64_hugews:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    movq %rdi, %rcx
 ; SLM-NEXT:    movq %rdi, %rax
 ; SLM-NEXT:    orq %rsi, %rcx
 ; SLM-NEXT:    shrq $32, %rcx
 ; SLM-NEXT:    je .LBB4_1