[MC][ELF][ARM] Add relocations for some ARM pc-relative fixups.

[psmith]

Summary

Add ELF relocations for the following fixups:

• fixup_arm_ldst_pcrel_12 -> R_ARM_LDR_PC_G0
• fixup_arm_adr_pcrel_12 -> R_ARM_ALU_PC_G0

These relocations map to the pseudo instructions:

• ldr rd, label
• adr rd, label

They are short ranged and normally resolved by the fixup, however MC will no longer resolve the fixups to global symbols due to interpositioning concerns. We can handle these at link time by implementing the relocations.

This is the ARM equivalent of D75039, LLD patch implementing the relocations will be submitted later today.

[MaskRay]

llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp

140

From the fixup name it is hard to predicate the name of the relocation type. Does anyone know why?

[psmith]

llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp

140

Apologies for the delay in responding. I missed the notification in the inbox. I don't have a particularly good answer, my guess is that there is a mix of ELF and MachO terminology from the assembler, with more of a slant towards MachO than ELF. The 12 will refer to the number of bits in the immediate.

The G0 is short for Group 0. The relocations while too short ranged to be useful on their own can be used in groups to load much more useful constants. The intention is to write something like the Arm PLT entry. In LLD we hard code the masks but in principle they can be calculated by relocations.

ADD ip, pc, #-8:PC_OFFSET_27_20: X ; R_ARM_ALU_PC_G0_NC(X)
ADD ip, ip, #-4:PC_OFFSET_19_12: X ; R_ARM_ALU_PC_G1_NC(X)
LDR pc, [ip, #0:PC_OFFSET_11_0: X]! ; R_ARM_LDR_PC_G2(X)

The G0 and G1 each take 8 bytes of the offset to X then LDR uses the bottom 12 for the offset. For example:

ip = pc + (X & 0x0ff00000)
ip = ip + (X & 0x000ff000)
pc = [ip + 0x00000fff]

[MaskRay]

This shows up again in homepage after a recent Phabricator upgrade. Is our agreement that we should not generate such short-range relocations (diverging from GNU as)?

[psmith]

Yes. I think the consensus was to match the GCC behaviour, I'll abandon the revision.

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
   unsigned IsPCRelConstant =
       MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant;
   const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
       // ARMFixupKinds.h.
       //
       // Name                      Offset (bits) Size (bits)     Flags
-      {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
+      {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_ldst_pcrel_12", 0, 32,
        MCFixupKindInfo::FKF_IsPCRel |
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
       {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
       {"fixup_t2_pcrel_10", 0, 32,
        MCFixupKindInfo::FKF_IsPCRel |
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_pcrel_9", 0, 32,
        IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_thumb_adr_pcrel_10", 0, 8,
        MCFixupKindInfo::FKF_IsPCRel |
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-      {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
+      {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_adr_pcrel_12", 0, 32,
        MCFixupKindInfo::FKF_IsPCRel |
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},

llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp

if (IsPCRel) {
     case ARM::fixup_arm_thumb_bl:
     case ARM::fixup_arm_thumb_blx:
       switch (Modifier) {
       case MCSymbolRefExpr::VK_TLSCALL:
         return ELF::R_ARM_THM_TLS_CALL;
       default:
         return ELF::R_ARM_THM_CALL;
       }
+    case ARM::fixup_arm_adr_pcrel_12:
+      return ELF::R_ARM_ALU_PC_G0;
+    case ARM::fixup_arm_ldst_pcrel_12:
+      return ELF::R_ARM_LDR_PC_G0;
     case ARM::fixup_thumb_adr_pcrel_10:
     case ARM::fixup_arm_thumb_cp:
       return ELF::R_ARM_THM_PC8;
     case ARM::fixup_t2_adr_pcrel_12:
       return ELF::R_ARM_THM_ALU_PREL_11_0;
     case ARM::fixup_t2_ldst_pcrel_12:
       return ELF::R_ARM_THM_PC12;
     case ARM::fixup_bf_target:

llvm/test/MC/ARM/arm-relax-adr.s

+@ RUN: not llvm-mc -triple armv5a-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: llvm-mc -triple armv5a-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF %s
+
+        .global func1
+_func1:
+        adr r0, _func2
+@ CHECK-ERROR: unsupported relocation on symbol
+@ CHECK-ELF: 0x0 R_ARM_ALU_PC_G0 _func2 0x0

llvm/test/MC/ARM/arm-relax-ldrlit.s

+@ RUN: not llvm-mc -triple armv5a-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
+@ RUN: llvm-mc -triple armv5a-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF %s
+
+        .global func1
+_func1:
+        ldr r0, _func2
+@ CHECK-ERROR: unsupported relocation on symbol
+@ CHECK-ELF: 0x0 R_ARM_LDR_PC_G0 _func2 0x0

llvm/test/MC/ARM/pcrel-global-rel.s

 @ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t
-@ RUN: llvm-readobj -r %t
+@ RUN: llvm-readobj -r %t | FileCheck %s
 
 @ Check that for ELF targets we generate a relocation for a within section
 @ pc-relative reference to a global symbol as it may be interposed and we won't
 @ know till link time whether this is possible.
+
+.globl foo
+foo:
+adr r2, foo      @ arm_adr_pcrel_12
+ldr r0, foo      @ arm_ldst_pcrel_12
+
 .thumb
 .thumb_func
 
 .globl bar
 bar:
 adr r0, bar      @ thumb_adr_pcrel_10
 adr.w r0, bar    @ t2_adr_pcrel_12
 ldr.w pc, bar    @ t2_ldst_pcrel_12
 
-@ CHECK:      0x0 R_ARM_THM_ALU_PREL_11_0 bar 0x0
-@ CHECK-NEXT: 0x4 R_ARM_THM_ALU_PREL_11_0 bar 0x0
-@ CHECK-NEXT: 0x8 R_ARM_THM_PC12 bar 0x0
+@ CHECK:          0x0 R_ARM_ALU_PC_G0 foo 0x0
+@ CHECK-NEXT:     0x4 R_ARM_LDR_PC_G0 foo 0x0
+@ CHECK-NEXT:     0x8 R_ARM_THM_ALU_PREL_11_0 bar 0x0
+@ CHECK-NEXT:     0xC R_ARM_THM_ALU_PREL_11_0 bar 0x0
+@ CHECK-NEXT:     0x10 R_ARM_THM_PC12 bar 0x0

llvm/test/MC/ARM/pcrel-global.s

 @ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t
 @ RUN: llvm-readelf -r %t | FileCheck %s
 
 @ CHECK: There are no relocations in this file.
 .syntax unified
 
 .globl foo
 foo:
 ldrd r0, r1, foo @ arm_pcrel_10_unscaled
 vldr d0, foo     @ arm_pcrel_10
-adr r2, foo      @ arm_adr_pcrel_12
-ldr r0, foo      @ arm_ldst_pcrel_12