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Differential D75088

AMDGPU/GlobalISel: Fix some illegal scalar argument types
ClosedPublic

Authored by arsenm on Feb 24 2020, 3:46 PM.

Details

Reviewers
nhaehnle
kerbowa
foad
Summary

Fixes integrs that don't evenly divide to i32 pieces. We should
probably extract some of the code in the legalizer to start handling
argument breakdowns. I'm dissatisfied with the argument lowering's
handling of vectors for example, and we should not be producing the
weird G_EXTRACTs we do now.

Diff Detail

Event Timeline

arsenm created this revision.Feb 24 2020, 3:46 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 24 2020, 3:46 PM
Herald added subscribers: hiraditya, t-tye, tpr and 6 others. · View Herald Transcript
arsenm added a comment.Mar 4 2020, 3:55 PM

ping

arsenm added a comment.Mar 9 2020, 1:13 PM

ping

foad added inline comments.Mar 10 2020, 2:38 AM
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
258

Isn't the whole point of the zeroext attribute that you don't need an explicit G_ZEXT here? You can just use [[MV]] directly.

arsenm marked an inline comment as done.Mar 10 2020, 8:51 AM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
258

We need an equivalent of ISD::AssertZext, but don't have it. This is serving as a placeholder

kerbowa accepted this revision.Mar 15 2020, 10:11 PM

LGTM

This revision is now accepted and ready to land.Mar 15 2020, 10:11 PM
arsenm closed this revision.Mar 16 2020, 9:51 AM

c460dc6eebc3d7a0b4ec755994a9e2984223f327

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
16 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
142 lines

Diff 246329

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Show First 20 Lines • Show All 517 Lines • ▼ Show 20 Lines
} }
// TODO: Move this to generic code // TODO: Move this to generic code
static void packSplitRegsToOrigType(MachineIRBuilder &B, static void packSplitRegsToOrigType(MachineIRBuilder &B,
ArrayRef<Register> OrigRegs, ArrayRef<Register> OrigRegs,
ArrayRef<Register> Regs, ArrayRef<Register> Regs,
LLT LLTy, LLT LLTy,
LLT PartLLT) { LLT PartLLT) {
MachineRegisterInfo &MRI = *B.getMRI();
if (!LLTy.isVector() && !PartLLT.isVector()) { if (!LLTy.isVector() && !PartLLT.isVector()) {
assert(OrigRegs.size() == 1);
LLT OrigTy = MRI.getType(OrigRegs[0]);
unsigned SrcSize = PartLLT.getSizeInBits() * Regs.size();
if (SrcSize == OrigTy.getSizeInBits())
B.buildMerge(OrigRegs[0], Regs); B.buildMerge(OrigRegs[0], Regs);
else {
auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);
B.buildTrunc(OrigRegs[0], Widened);
}
return; return;
} }
if (LLTy.isVector() && PartLLT.isVector()) { if (LLTy.isVector() && PartLLT.isVector()) {
assert(LLTy.getElementType() == PartLLT.getElementType()); assert(LLTy.getElementType() == PartLLT.getElementType());
int DstElts = LLTy.getNumElements(); int DstElts = LLTy.getNumElements();
int PartElts = PartLLT.getNumElements(); int PartElts = PartLLT.getNumElements();
if (DstElts % PartElts == 0) if (DstElts % PartElts == 0)
B.buildConcatVectors(OrigRegs[0], Regs); B.buildConcatVectors(OrigRegs[0], Regs);
else { else {
// Deal with v3s16 split into v2s16 // Deal with v3s16 split into v2s16
assert(PartElts == 2 && DstElts % 2 != 0); assert(PartElts == 2 && DstElts % 2 != 0);
int RoundedElts = PartElts * ((DstElts + PartElts - 1) / PartElts); int RoundedElts = PartElts * ((DstElts + PartElts - 1) / PartElts);
LLT RoundedDestTy = LLT::vector(RoundedElts, PartLLT.getElementType()); LLT RoundedDestTy = LLT::vector(RoundedElts, PartLLT.getElementType());
auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs); auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs);
B.buildExtract(OrigRegs[0], RoundedConcat, 0); B.buildExtract(OrigRegs[0], RoundedConcat, 0);
} }
return; return;
} }
MachineRegisterInfo &MRI = *B.getMRI();
assert(LLTy.isVector() && !PartLLT.isVector()); assert(LLTy.isVector() && !PartLLT.isVector());
LLT DstEltTy = LLTy.getElementType(); LLT DstEltTy = LLTy.getElementType();
// Pointer information was discarded. We'll need to coerce some register types // Pointer information was discarded. We'll need to coerce some register types
// to avoid violating type constraints. // to avoid violating type constraints.
LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType(); LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType();
▲ Show 20 Lines • Show All 206 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

Show First 20 Lines • Show All 221 Lines • ▼ Show 20 Linesdefine void @void_func_p3i8(i8 addrspace(3)* %arg0) #0 {
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[COPY]](p3), [[DEF]](p1) :: (store 4 into `i8 addrspace(3)* addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[COPY]](p3), [[DEF]](p1) :: (store 4 into `i8 addrspace(3)* addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
; CHECK: S_SETPC_B64_return [[COPY2]] ; CHECK: S_SETPC_B64_return [[COPY2]]
store i8 addrspace(3)* %arg0, i8 addrspace(3)* addrspace(1)* undef store i8 addrspace(3)* %arg0, i8 addrspace(3)* addrspace(1)* undef
ret void ret void
} }
define void @void_func_i48(i48 %arg0) #0 {
; CHECK-LABEL: name: void_func_i48
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[TRUNC]](s48), [[DEF]](p1) :: (store 6 into `i48 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
; CHECK: S_SETPC_B64_return [[COPY3]]
store i48 %arg0, i48 addrspace(1)* undef
ret void
}
define void @void_func_i48_zeroext(i48 zeroext %arg0) #0 {
; CHECK-LABEL: name: void_func_i48_zeroext
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s48)
foadUnsubmitted
Not Done
ReplyInline Actions

Isn't the whole point of the zeroext attribute that you don't need an explicit G_ZEXT here? You can just use [[MV]] directly.

foad: Isn't the whole point of the `zeroext` attribute that you //don't// need an explicit `G_ZEXT`…
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

We need an equivalent of ISD::AssertZext, but don't have it. This is serving as a placeholder

arsenm: We need an equivalent of ISD::AssertZext, but don't have it. This is serving as a placeholder
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ZEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
; CHECK: S_SETPC_B64_return [[COPY3]]
%ext = zext i48 %arg0 to i64
%add = add i64 %ext, 12
store i64 %add, i64 addrspace(1)* undef
ret void
}
define void @void_func_i48_signext(i48 signext %arg0) #0 {
; CHECK-LABEL: name: void_func_i48_signext
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s48)
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
; CHECK: S_SETPC_B64_return [[COPY3]]
%ext = sext i48 %arg0 to i64
%add = add i64 %ext, 12
store i64 %add, i64 addrspace(1)* undef
ret void
}
define void @void_func_i64(i64 %arg0) #0 { define void @void_func_i64(i64 %arg0) #0 {
; CHECK-LABEL: name: void_func_i64 ; CHECK-LABEL: name: void_func_i64
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[MV]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[MV]](s64), [[DEF]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
; CHECK: S_SETPC_B64_return [[COPY3]] ; CHECK: S_SETPC_B64_return [[COPY3]]
store i64 %arg0, i64 addrspace(1)* undef store i64 %arg0, i64 addrspace(1)* undef
ret void ret void
} }
define void @void_func_i95(i95 %arg0) #0 {
; CHECK-LABEL: name: void_func_i95
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[TRUNC]](s95), [[DEF]](p1) :: (store 12 into `i95 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
; CHECK: S_SETPC_B64_return [[COPY4]]
store i95 %arg0, i95 addrspace(1)* undef
ret void
}
define void @void_func_i95_zeroext(i95 zeroext %arg0) #0 {
; CHECK-LABEL: name: void_func_i95_zeroext
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
; CHECK: [[C:%[0-9]+]]:_(s96) = G_CONSTANT i96 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[ZEXT:%[0-9]+]]:_(s96) = G_ZEXT [[TRUNC]](s95)
; CHECK: [[ADD:%[0-9]+]]:_(s96) = G_ADD [[ZEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
; CHECK: S_SETPC_B64_return [[COPY4]]
%ext = zext i95 %arg0 to i96
%add = add i96 %ext, 12
store i96 %add, i96 addrspace(1)* undef
ret void
}
define void @void_func_i95_signext(i95 signext %arg0) #0 {
; CHECK-LABEL: name: void_func_i95_signext
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s95) = G_TRUNC [[MV]](s96)
; CHECK: [[C:%[0-9]+]]:_(s96) = G_CONSTANT i96 12
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[SEXT:%[0-9]+]]:_(s96) = G_SEXT [[TRUNC]](s95)
; CHECK: [[ADD:%[0-9]+]]:_(s96) = G_ADD [[SEXT]], [[C]]
; CHECK: G_STORE [[ADD]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
; CHECK: S_SETPC_B64_return [[COPY4]]
%ext = sext i95 %arg0 to i96
%add = add i96 %ext, 12
store i96 %add, i96 addrspace(1)* undef
ret void
}
define void @void_func_i96(i96 %arg0) #0 {
; CHECK-LABEL: name: void_func_i96
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[MV]](s96), [[DEF]](p1) :: (store 12 into `i96 addrspace(1)* undef`, align 8, addrspace 1)
; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
; CHECK: S_SETPC_B64_return [[COPY4]]
store i96 %arg0, i96 addrspace(1)* undef
ret void
}
define void @void_func_p0i8(i8* %arg0) #0 { define void @void_func_p0i8(i8* %arg0) #0 {
; CHECK-LABEL: name: void_func_p0i8 ; CHECK-LABEL: name: void_func_p0i8
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) ; CHECK: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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