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Differential D74950

GlobalISel: Fix narrowing of (G_ASHR i64:x, 32)
ClosedPublic

Authored by foad on Feb 21 2020, 12:34 AM.

Details

Reviewers
arsenm
Commits
rGcab39e4b8c82: GlobalISel: Fix narrowing of (G_ASHR i64:x, 32)

Diff Detail

Event Timeline

foad created this revision.Feb 21 2020, 12:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 21 2020, 12:34 AM
Herald added subscribers: llvm-commits, kerbowa, volkan and 5 others. · View Herald Transcript
Harbormaster failed remote builds in B46978: Diff 245797!Feb 21 2020, 12:59 AM
arsenm accepted this revision.Feb 21 2020, 8:42 AM
This revision is now accepted and ready to land.Feb 21 2020, 8:42 AM
Closed by commit rGcab39e4b8c82: GlobalISel: Fix narrowing of (G_ASHR i64:x, 32) (authored by foad). · Explain WhyFeb 21 2020, 8:51 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
4 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
4 lines

Diff 245797

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 1,443 Lines • ▼ Show 20 Linesbool CombinerHelper::applyCombineShiftToUnmerge(MachineInstr &MI,
} else { } else {
assert(MI.getOpcode() == TargetOpcode::G_ASHR); assert(MI.getOpcode() == TargetOpcode::G_ASHR);
auto Hi = Builder.buildAShr( auto Hi = Builder.buildAShr(
HalfTy, Unmerge.getReg(1), HalfTy, Unmerge.getReg(1),
Builder.buildConstant(HalfTy, HalfSize - 1)); Builder.buildConstant(HalfTy, HalfSize - 1));
if (ShiftVal == HalfSize) { if (ShiftVal == HalfSize) {
// (G_ASHR i64:x, 32) -> // (G_ASHR i64:x, 32) ->
// G_MERGE_VALUES lo_32(x), (G_ASHR hi_32(x), 31) // G_MERGE_VALUES hi_32(x), (G_ASHR hi_32(x), 31)
Builder.buildMerge(DstReg, { Unmerge.getReg(0), Hi }); Builder.buildMerge(DstReg, { Unmerge.getReg(1), Hi });
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      Builder.buildMerge(DstReg, { Unmerge.getReg(1), Hi });
+      Builder.buildMerge(DstReg, {Unmerge.getReg(1), Hi});
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Builder.buildMerge(DstReg, { Unmerge.getReg…
} else if (ShiftVal == Size - 1) { } else if (ShiftVal == Size - 1) {
// Don't need a second shift. // Don't need a second shift.
// (G_ASHR i64:x, 63) -> // (G_ASHR i64:x, 63) ->
// %narrowed = (G_ASHR hi_32(x), 31) // %narrowed = (G_ASHR hi_32(x), 31)
// G_MERGE_VALUES %narrowed, %narrowed // G_MERGE_VALUES %narrowed, %narrowed
Builder.buildMerge(DstReg, { Hi, Hi }); Builder.buildMerge(DstReg, { Hi, Hi });
} else { } else {
auto Lo = Builder.buildAShr( auto Lo = Builder.buildAShr(
Show All 33 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
--- ---
name: narrow_ashr_s64_32_s64amt name: narrow_ashr_s64_32_s64amt
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: narrow_ashr_s64_32_s64amt ; CHECK-LABEL: name: narrow_ashr_s64_32_s64amt
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[ASHR]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_CONSTANT i64 32 %1:_(s64) = G_CONSTANT i64 32
%2:_(s64) = G_ASHR %0, %1 %2:_(s64) = G_ASHR %0, %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: narrow_ashr_s64_32 name: narrow_ashr_s64_32
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: narrow_ashr_s64_32 ; CHECK-LABEL: name: narrow_ashr_s64_32
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[ASHR]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 32 %1:_(s32) = G_CONSTANT i32 32
%2:_(s64) = G_ASHR %0, %1 %2:_(s64) = G_ASHR %0, %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
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