[AArch64][ASMParser] Refuse equal source/destination for LDRAA/LDRAB

[ostannard]

The exact line in the architecture manual is if wback && n == t && n != 31 then. I _think_ we already get the n != 31 case correct, because we will parse one operand to XZR and the other to SP, but could you please add a test for this?

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4123

s/source/destination/ ?

[Pierre-vh]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4123

What do you mean? Should I change the error message? What do you suggest?

[Pierre-vh]

I changed the error message like you suggested and I also added more tests (suggested by @DavidSpickett )

[Pierre-vh]

Forgot the ldraa variant for the sp/sp xzr/xzr test

[ostannard]

LGTM

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

4123

The change you've made is what I meant: the last word of the message is referring to Xt, which is a destination register, not as source.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

case AArch64::STLXPX: {
     unsigned Rt2 = Inst.getOperand(2).getReg();
     unsigned Rn = Inst.getOperand(3).getReg();
     if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
         (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
       return Error(Loc[0],
                    "unpredictable STXP instruction, status is also a source");
     break;
   }
+  case AArch64::LDRABwriteback:
+  case AArch64::LDRAAwriteback: {
+    unsigned Xt = Inst.getOperand(0).getReg();
+    unsigned Xn = Inst.getOperand(1).getReg();
+    if (Xt == Xn)
+      return Error(Loc[0],
+          "unpredictable LDRA instruction, writeback base"
+          " is also a destination");
+    break;
+  }
   }
 
 
   // Now check immediate ranges. Separate from the above as there is overlap
   // in the instructions being checked and this keeps the nested conditionals
   // to a minimum.
   switch (Inst.getOpcode()) {
   case AArch64::ADDSWri:

llvm/test/MC/AArch64/armv8.3a-diagnostics.s

// CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
   ldraa x0, [x1, 4086]
 // CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
   ldrab x0, [x1, 4089]
 // CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
   ldrab x0, [x1, -4097]
 // CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
   ldrab x0, [x1, 4086]
 // CHECK: error: index must be a multiple of 8 in range [-4096, 4088].
+  ldraa x0, [x0, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable LDRA instruction, writeback base is also a destination
+  ldrab x0, [x0, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable LDRA instruction, writeback base is also a destination
+  ldraa xzr, [xzr, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldraa sp, [sp, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldrab xzr, [xzr, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+  ldrab sp, [sp, -4096]!
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

llvm/test/MC/AArch64/armv8.3a-signed-pointer.s

// CHECK-REQ-NEXT:  ldrab x0, [x1]
   ldraa x0, [x1]!
 // CHECK-NEXT: ldraa x0, [x1, #0]!  // encoding: [0x20,0x0c,0x20,0xf8]
 // CHECK-REQ: error: instruction requires: pa
 // CHECK-REQ-NEXT:  ldraa x0, [x1]!
   ldrab x0, [x1]!
 // CHECK-NEXT: ldrab x0, [x1, #0]!  // encoding: [0x20,0x0c,0xa0,0xf8]
 // CHECK-REQ: error: instruction requires: pa
 // CHECK-REQ-NEXT:  ldrab x0, [x1]!
+  ldraa xzr, [sp, -4096]!
+// CHECK-NEXT: ldraa xzr, [sp, #-4096]!  // encoding: [0xff,0x0f,0x60,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldraa xzr, [sp, -4096]!
+  ldrab xzr, [sp, -4096]!
+// CHECK-NEXT: ldrab xzr, [sp, #-4096]!  // encoding: [0xff,0x0f,0xe0,0xf8]
+// CHECK-REQ: error: instruction requires: pa
+// CHECK-REQ-NEXT:  ldrab xzr, [sp, -4096]!