[FPEnv][ARM] Don't call mutateStrictFPToFP when lowering

[john.brawn]

Summary

mutateStrictFPToFP can delete the node and replace it with another with the same value which can later cause problems, and returning the result of mutateStrictFPToFP doesn't work because SelectionDAGLegalize expects that the returned value has the same number of results as the original. Instead handle things by doing the mutation manually.

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (isUnsupportedFloatingType(SrcVal.getValueType())) {
     SDValue Result;
     std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
                                           CallOptions, Loc, Chain);
     return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
   }
 
   // FIXME: Remove this when we have strict fp instruction selection patterns
   if (IsStrict) {
-    DAG.mutateStrictFPToFP(Op.getNode());
+    SDLoc Loc(Op);
+    SDValue Result =
+        DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
+                                                             : ISD::FP_TO_UINT,
+                    Loc, Op.getValueType(), SrcVal);
+    return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
   }
 
   return Op;
 }
 
 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
   EVT VT = Op.getValueType();
   SDLoc dl(Op);
SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
 
   assert(!(DstSz == 32 && Subtarget->hasFP16()) &&
          "With FP16, 16 to 32 conversion is legal!");
 
   // Converting from 32 -> 64 is valid if we have FP64.
   if (SrcSz == 32 && DstSz == 64 && Subtarget->hasFP64()) {
     // FIXME: Remove this when we have strict fp instruction selection patterns
     if (IsStrict) {
-      DAG.mutateStrictFPToFP(Op.getNode());
+      SDLoc Loc(Op);
+      SDValue Result = DAG.getNode(ISD::FP_EXTEND,
+                                   Loc, Op.getValueType(), SrcVal);
+      return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
     }
     return Op;
   }
 
   // Either we are converting from 16 -> 64, without FP16 and/or
   // FP.double-precision or without Armv8-fp. So we must do it in two
   // steps.
   // Or we are converting from 32 -> 64 without fp.double-precision or 16 -> 32

llvm/test/CodeGen/ARM/fp-intrinsics.ll

 ; CHECK-LABEL: fptosi_f32:
 ; CHECK-NOSP: bl __aeabi_f2iz
 ; CHECK-SP: vcvt.s32.f32
 define i32 @fptosi_f32(float %x) #0 {
   %val = call i32 @llvm.experimental.constrained.fptosi.f32(float %x, metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
+; CHECK-LABEL: fptosi_f32_twice:
+; CHECK-NOSP: bl __aeabi_f2iz
+; CHECK-NOSP: bl __aeabi_f2iz
+; CHECK-SP: vcvt.s32.f32
+; FIXME-CHECK-SP: vcvt.s32.f32
+define void @fptosi_f32_twice(float %arg, i32* %ptr) #0 {
+entry:
+  %conv = call i32 @llvm.experimental.constrained.fptosi.f32(float %arg, metadata !"fpexcept.strict") #0
+  store i32 %conv, i32* %ptr, align 4
+  %conv1 = call i32 @llvm.experimental.constrained.fptosi.f32(float %arg, metadata !"fpexcept.strict") #0
+  %idx = getelementptr inbounds i32, i32* %ptr, i32 1
+  store i32 %conv1, i32* %idx, align 4
+  ret void
+}
+
 ; CHECK-LABEL: fptoui_f32:
 ; CHECK-NOSP: bl __aeabi_f2uiz
 ; FIXME-CHECK-SP: vcvt.u32.f32
 define i32 @fptoui_f32(float %x) #0 {
   %val = call i32 @llvm.experimental.constrained.fptoui.f32(float %x, metadata !"fpexcept.strict") #0
   ret i32 %val
 }
 
+; CHECK-LABEL: fptoui_f32_twice:
+; CHECK-NOSP: bl __aeabi_f2uiz
+; CHECK-NOSP: bl __aeabi_f2uiz
+; FIXME-CHECK-SP: vcvt.u32.f32
+; FIXME-CHECK-SP: vcvt.u32.f32
+define void @fptoui_f32_twice(float %arg, i32* %ptr) #0 {
+entry:
+  %conv = call i32 @llvm.experimental.constrained.fptoui.f32(float %arg, metadata !"fpexcept.strict") #0
+  store i32 %conv, i32* %ptr, align 4
+  %conv1 = call i32 @llvm.experimental.constrained.fptoui.f32(float %arg, metadata !"fpexcept.strict") #0
+  %idx = getelementptr inbounds i32, i32* %ptr, i32 1
+  store i32 %conv1, i32* %idx, align 4
+  ret void
+}
+
 ; CHECK-LABEL: sqrt_f32:
 ; CHECK-NOSP: bl sqrtf
 ; CHECK-SP: vsqrt.f32
 define float @sqrt_f32(float %x) #0 {
   %val = call float @llvm.experimental.constrained.sqrt.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret float %val
 }
 

 ; CHECK-LABEL: fpext_f32:
 ; CHECK-NODP: bl __aeabi_f2d
 ; CHECK-DP: vcvt.f64.f32
 define double @fpext_f32(float %x) #0 {
   %val = call double @llvm.experimental.constrained.fpext.f64.f32(float %x, metadata !"fpexcept.strict") #0
   ret double %val
 }
 
+; CHECK-LABEL: fpext_f32_twice:
+; CHECK-NODP: bl __aeabi_f2d
+; CHECK-NODP: bl __aeabi_f2d
+; CHECK-DP: vcvt.f64.f32
+; FIXME-CHECK-DP: vcvt.f64.f32
+define void @fpext_f32_twice(float %arg, double* %ptr) #0 {
+entry:
+  %conv1 = call double @llvm.experimental.constrained.fpext.f64.f32(float %arg, metadata !"fpexcept.strict") #0
+  store double %conv1, double* %ptr, align 8
+  %conv2 = call double @llvm.experimental.constrained.fpext.f64.f32(float %arg, metadata !"fpexcept.strict") #0
+  %idx = getelementptr inbounds double, double* %ptr, i32 1
+  store double %conv2, double* %idx, align 8
+  ret void
+}
+
 ; CHECK-LABEL: sitofp_f32_i32:
 ; CHECK-NOSP: bl __aeabi_i2f
 ; FIXME-CHECK-SP: vcvt.f32.s32
 define float @sitofp_f32_i32(i32 %x) #0 {
   %val = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
   ret float %val
 }