[TBLGEN] Emit register pressure set enum

[arsenm]

Can we just stop emitting all of the pressure sets we don't use instead?

[rampitec]

In D74649#1877422, @arsenm wrote:

Can we just stop emitting all of the pressure sets we don't use instead?

I am not sure how tablegen can tell we are not going to use it. That would be a separate patch anyway, since we need a way to point to a pset even if we have fewer of them. My guess the only reason not to have this enum was some non conventional characters in names for some targets.

[rampitec]

Moved to the enum section.

[nhaehnle]

llvm/utils/TableGen/RegisterInfoEmitter.cpp

101–109

Is there no pre-existing way of doing this in TableGen? If not, why is this needed in the first place?

[rampitec]

llvm/utils/TableGen/RegisterInfoEmitter.cpp

101–109

I was looking for one and didn't find. Looks like in other cases tablegen just avoids such names. Here I saw "+" sign. Probably it will take yet another change to remove both invalid symbols and this function.

[rampitec]

Produce legal pset names from start.

[rampitec]

This is still needed even after D74744. See D74671 why.

[vpykhtin]

LGTM.

llvm/test/TableGen/Common/reg-with-subregs-common.td

list<int> all = [0,   1,  2,  3,  4,  5,  6 , 7,
                    8,   9, 10, 11, 12, 13, 14, 15,
                    16, 17, 18, 19, 20, 21, 22, 23,
                    24, 25, 26, 27, 28, 29, 30, 31];
   list<int> slice =
     !foldl([]<int>, all, acc, cur,
            !listconcat(acc, !if(!lt(cur, N), [cur], [])));
 }
 
+#ifdef USE_NAMESPACE
+  let Namespace = "TestNamespace" in {
+#endif
 foreach Index = 0-31 in {
   def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
 foreach Size = {2,4,8,16} in {
   foreach Index = Indexes<!add(33, !mul(Size, -1))>.slice in {
     def !foldl("", Indexes<Size>.slice, acc, cur,
                !strconcat(acc#!if(!eq(acc,""),"","_"), "sub"#!add(cur, Index))) :
       SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
       let CoveringSubRegIndices =
         !foldl([]<SubRegIndex>, Indexes<Size>.slice, acc, cur,
                !listconcat(acc, [!cast<SubRegIndex>(sub#!add(cur, Index))]));
     }
   }
 }
 
 foreach Index = 0-255 in {
   def R#Index : Register <"r"#Index>;
 }
+#ifdef USE_NAMESPACE
+}
+#endif
 
 def GPR32 : RegisterClass<"TestTarget", [i32], 32,
                           (add (sequence "R%u", 0, 255))>;
 
 def GPR64 : RegisterTuples<[sub0, sub1],
                            [(decimate (shl GPR32, 0), 1),
                             (decimate (shl GPR32, 1), 1)
                            ]>;
def GPR1024 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
                               (decimate (shl GPR32, 26), 1),
                               (decimate (shl GPR32, 27), 1),
                               (decimate (shl GPR32, 28), 1),
                               (decimate (shl GPR32, 29), 1),
                               (decimate (shl GPR32, 30), 1),
                               (decimate (shl GPR32, 31), 1)
                              ]>;
 
+#ifdef USE_NAMESPACE
+  let Namespace = "TestNamespace" in {
+#endif
 def GPR_64 : RegisterClass<"", [v2i32], 64, (add GPR64)>;
 def GPR_1024 : RegisterClass<"", [v32i32], 1024, (add GPR1024)>;
+#ifdef USE_NAMESPACE
+}
+#endif

llvm/test/TableGen/pset-enum.td

+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common -DUSE_NAMESPACE %s | FileCheck --check-prefixes=CHECK,NAMESPACE %s
+
+include "reg-with-subregs-common.td"
+
+// CHECK-LABEL:    // Register pressure sets enum.
+// NAMESPACE-NEXT: namespace TestNamespace {
+// CHECK-NEXT:     enum RegisterPressureSets {
+// CHECK-NEXT:       GPR32 = 0,
+// CHECK-NEXT:     };
+// NAMESPACE-NEXT: } // end namespace TestNamespace

llvm/utils/TableGen/CodeGenRegisters.cpp

for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
                             RegUnitSets[SearchIdx].Units.end(),
                             std::inserter(Intersection, Intersection.begin()));
       if (Intersection.empty())
         continue;
 
       // Speculatively grow the RegUnitSets to hold the new set.
       RegUnitSets.resize(RegUnitSets.size() + 1);
       RegUnitSets.back().Name =
-        RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
+        RegUnitSets[Idx].Name + "_with_" + RegUnitSets[SearchIdx].Name;
 
       std::set_union(RegUnitSets[Idx].Units.begin(),
                      RegUnitSets[Idx].Units.end(),
                      RegUnitSets[SearchIdx].Units.begin(),
                      RegUnitSets[SearchIdx].Units.end(),
                      std::inserter(RegUnitSets.back().Units,
                                    RegUnitSets.back().Units.begin()));
 

llvm/utils/TableGen/RegisterInfoEmitter.cpp

private:
   void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
                                 const std::string &ClassName);
   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
                                       const std::string &ClassName);
 };
 
 } // end anonymous namespace
 
 // runEnums - Print out enum values for all of the registers.
 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
                                    CodeGenTarget &Target, CodeGenRegBank &Bank) {
   const auto &Registers = Bank.getRegisters();
 
   // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
   assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
 
   StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
 
   emitSourceFileHeader("Target Register Enum Values", OS);
 
   OS << "\n#ifdef GET_REGINFO_ENUM\n";
   OS << "#undef GET_REGINFO_ENUM\n\n";
 
   OS << "namespace llvm {\n\n";
 
if (!SubRegIndices.empty()) {
     unsigned i = 0;
     for (const auto &Idx : SubRegIndices)
       OS << "  " << Idx.getName() << ",\t// " << ++i << "\n";
     OS << "  NUM_TARGET_SUBREGS\n};\n";
     if (!Namespace.empty())
       OS << "} // end namespace " << Namespace << "\n\n";
   }
 
+  OS << "// Register pressure sets enum.\n";
+  if (!Namespace.empty())
+    OS << "namespace " << Namespace << " {\n";
+  OS << "enum RegisterPressureSets {\n";
+  unsigned NumSets = Bank.getNumRegPressureSets();
+  for (unsigned i = 0; i < NumSets; ++i ) {
+    const RegUnitSet &RegUnits = Bank.getRegSetAt(i);
+    OS << "  " << RegUnits.Name << " = " << i << ",\n";
+  }
+  OS << "};\n";
+  if (!Namespace.empty())
+    OS << "} // end namespace " << Namespace << '\n';
+  OS << '\n';
+
   OS << "} // end namespace llvm\n\n";
   OS << "#endif // GET_REGINFO_ENUM\n\n";
 }
 
 static void printInt(raw_ostream &OS, int Val) {
   OS << Val;
 }