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Differential D74624

[MIPS GlobalISel] Select 4 byte unaligned load and store
ClosedPublic

Authored by Petar.Avramovic on Feb 14 2020, 8:43 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG5171d1523dd8: [MIPS GlobalISel] Select 4 byte unaligned load and store
Summary

Improve legality checks for load and store, 4 byte scalar load and store
are now legal for all subtargets.
During regbank selection 4 byte unaligned loads and stores for MIPS32r5
and older get mapped to gprb.
Select 4 byte unaligned loads and stores for MIPS32r5.
Fix tests that unintentionally had unaligned load or store.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
Mips/
79 lines
54 lines
18 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
89 lines
90 lines
99 lines
96 lines
legalizer/
239 lines
271 lines
llvm-ir/
182 lines
6 lines
178 lines
regbankselect/
97 lines
18 lines
110 lines

Diff 245363

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Linesprivate:
bool isRegInFprb(Register Reg, MachineRegisterInfo &MRI) const; bool isRegInFprb(Register Reg, MachineRegisterInfo &MRI) const;
bool materialize32BitImm(Register DestReg, APInt Imm, bool materialize32BitImm(Register DestReg, APInt Imm,
MachineIRBuilder &B) const; MachineIRBuilder &B) const;
bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const; bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
const TargetRegisterClass * const TargetRegisterClass *
getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const; getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
unsigned selectLoadStoreOpCode(MachineInstr &I, unsigned selectLoadStoreOpCode(MachineInstr &I,
MachineRegisterInfo &MRI) const; MachineRegisterInfo &MRI) const;
bool buildUnalignedStore(MachineInstr &I, unsigned Opc,
MachineOperand &BaseAddr, unsigned Offset,
MachineMemOperand *MMO) const;
bool buildUnalignedLoad(MachineInstr &I, unsigned Opc, Register Dest,
MachineOperand &BaseAddr, unsigned Offset,
Register TiedDest, MachineMemOperand *MMO) const;
const MipsTargetMachine &TM; const MipsTargetMachine &TM;
const MipsSubtarget &STI; const MipsSubtarget &STI;
const MipsInstrInfo &TII; const MipsInstrInfo &TII;
const MipsRegisterInfo &TRI; const MipsRegisterInfo &TRI;
const MipsRegisterBankInfo &RBI; const MipsRegisterBankInfo &RBI;
#define GET_GLOBALISEL_PREDICATES_DECL #define GET_GLOBALISEL_PREDICATES_DECL
▲ Show 20 Lines • Show All 183 Lines • ▼ Show 20 Lines if (Ty.isVector()) {
return Opc; return Opc;
} }
} }
} }
return Opc; return Opc;
} }
bool MipsInstructionSelector::buildUnalignedStore(
MachineInstr &I, unsigned Opc, MachineOperand &BaseAddr, unsigned Offset,
MachineMemOperand *MMO) const {
MachineInstr *NewInst =
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
.add(I.getOperand(0))
.add(BaseAddr)
.addImm(Offset)
.addMemOperand(MMO);
if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
return false;
return true;
}
bool MipsInstructionSelector::buildUnalignedLoad(
MachineInstr &I, unsigned Opc, Register Dest, MachineOperand &BaseAddr,
unsigned Offset, Register TiedDest, MachineMemOperand *MMO) const {
MachineInstr *NewInst =
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
.addDef(Dest)
.add(BaseAddr)
.addImm(Offset)
.addUse(TiedDest)
.addMemOperand(*I.memoperands_begin());
if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
return false;
return true;
}
bool MipsInstructionSelector::select(MachineInstr &I) { bool MipsInstructionSelector::select(MachineInstr &I) {
MachineBasicBlock &MBB = *I.getParent(); MachineBasicBlock &MBB = *I.getParent();
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
if (!isPreISelGenericOpcode(I.getOpcode())) { if (!isPreISelGenericOpcode(I.getOpcode())) {
if (I.isCopy()) if (I.isCopy())
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines case G_PHI: {
I.setDesc(TII.get(TargetOpcode::PHI)); I.setDesc(TII.get(TargetOpcode::PHI));
return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
} }
case G_STORE: case G_STORE:
case G_LOAD: case G_LOAD:
case G_ZEXTLOAD: case G_ZEXTLOAD:
case G_SEXTLOAD: { case G_SEXTLOAD: {
const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); auto MMO = *I.memoperands_begin();
if (NewOpc == I.getOpcode())
return false;
MachineOperand BaseAddr = I.getOperand(1); MachineOperand BaseAddr = I.getOperand(1);
int64_t SignedOffset = 0; int64_t SignedOffset = 0;
// Try to fold load/store + G_PTR_ADD + G_CONSTANT // Try to fold load/store + G_PTR_ADD + G_CONSTANT
// %SignedOffset:(s32) = G_CONSTANT i32 16_bit_signed_immediate // %SignedOffset:(s32) = G_CONSTANT i32 16_bit_signed_immediate
// %Addr:(p0) = G_PTR_ADD %BaseAddr, %SignedOffset // %Addr:(p0) = G_PTR_ADD %BaseAddr, %SignedOffset
// %LoadResult/%StoreSrc = load/store %Addr(p0) // %LoadResult/%StoreSrc = load/store %Addr(p0)
// into: // into:
// %LoadResult/%StoreSrc = NewOpc %BaseAddr(p0), 16_bit_signed_immediate // %LoadResult/%StoreSrc = NewOpc %BaseAddr(p0), 16_bit_signed_immediate
MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg()); MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg());
if (Addr->getOpcode() == G_PTR_ADD) { if (Addr->getOpcode() == G_PTR_ADD) {
MachineInstr *Offset = MRI.getVRegDef(Addr->getOperand(2).getReg()); MachineInstr *Offset = MRI.getVRegDef(Addr->getOperand(2).getReg());
if (Offset->getOpcode() == G_CONSTANT) { if (Offset->getOpcode() == G_CONSTANT) {
APInt OffsetValue = Offset->getOperand(1).getCImm()->getValue(); APInt OffsetValue = Offset->getOperand(1).getCImm()->getValue();
if (OffsetValue.isSignedIntN(16)) { if (OffsetValue.isSignedIntN(16)) {
BaseAddr = Addr->getOperand(1); BaseAddr = Addr->getOperand(1);
SignedOffset = OffsetValue.getSExtValue(); SignedOffset = OffsetValue.getSExtValue();
} }
} }
} }
// Unaligned memory access
if (MMO->getSize() > MMO->getAlignment() &&
!STI.systemSupportsUnalignedAccess()) {
if (MMO->getSize() != 4 || !isRegInGprb(I.getOperand(0).getReg(), MRI))
return false;
if (I.getOpcode() == G_STORE) {
if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO))
return false;
if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO))
return false;
I.eraseFromParent();
return true;
}
if (I.getOpcode() == G_LOAD) {
Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
.addDef(ImplDef);
Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3,
ImplDef, MMO))
return false;
if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(),
BaseAddr, SignedOffset, Tmp, MMO))
return false;
I.eraseFromParent();
return true;
}
return false;
}
const unsigned NewOpc = selectLoadStoreOpCode(I, MRI);
if (NewOpc == I.getOpcode())
return false;
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
.add(I.getOperand(0)) .add(I.getOperand(0))
.add(BaseAddr) .add(BaseAddr)
.addImm(SignedOffset) .addImm(SignedOffset)
.addMemOperand(*I.memoperands_begin()); .addMemOperand(MMO);
break; break;
} }
case G_UDIV: case G_UDIV:
case G_UREM: case G_UREM:
case G_SDIV: case G_SDIV:
case G_SREM: { case G_SREM: {
Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV; bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV;
▲ Show 20 Lines • Show All 427 Lines • Show Last 20 Lines

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

Show All 15 Lines
#include "llvm/IR/IntrinsicsMips.h" #include "llvm/IR/IntrinsicsMips.h"
using namespace llvm; using namespace llvm;
struct TypesAndMemOps { struct TypesAndMemOps {
LLT ValTy; LLT ValTy;
LLT PtrTy; LLT PtrTy;
unsigned MemSize; unsigned MemSize;
bool MustBeNaturallyAligned; bool SystemSupportsUnalignedAccess;
}; };
// Assumes power of 2 memory size. Subtargets that have only naturally-aligned
// memory access need to perform additional legalization here.
bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) {
assert(isPowerOf2_64(MemSize) && "Expected power of 2 memory size");
assert(isPowerOf2_64(AlignInBits) && "Expected power of 2 align");
if (MemSize > AlignInBits)
return true;
return false;
}
static bool static bool
CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query, CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
std::initializer_list<TypesAndMemOps> SupportedValues) { std::initializer_list<TypesAndMemOps> SupportedValues) {
unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits;
// Non power of two memory access is never legal.
if (!isPowerOf2_64(QueryMemSize))
return false;
for (auto &Val : SupportedValues) { for (auto &Val : SupportedValues) {
if (Val.ValTy != Query.Types[0]) if (Val.ValTy != Query.Types[0])
continue; continue;
if (Val.PtrTy != Query.Types[1]) if (Val.PtrTy != Query.Types[1])
continue; continue;
if (Val.MemSize != Query.MMODescrs[0].SizeInBits) if (Val.MemSize != QueryMemSize)
continue;
if (Val.MustBeNaturallyAligned &&
Query.MMODescrs[0].SizeInBits % Query.MMODescrs[0].AlignInBits != 0)
continue; continue;
if (!Val.SystemSupportsUnalignedAccess &&
isUnalignedMemmoryAccess(QueryMemSize, Query.MMODescrs[0].AlignInBits))
return false;
return true; return true;
} }
return false; return false;
} }
static bool CheckTyN(unsigned N, const LegalityQuery &Query, static bool CheckTyN(unsigned N, const LegalityQuery &Query,
std::initializer_list<LLT> SupportedValues) { std::initializer_list<LLT> SupportedValues) {
for (auto &Val : SupportedValues) for (auto &Val : SupportedValues)
Show All 26 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO}) getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
.lowerFor({{s32, s1}}); .lowerFor({{s32, s1}});
getActionDefinitionsBuilder(G_UMULH) getActionDefinitionsBuilder(G_UMULH)
.legalFor({s32}) .legalFor({s32})
.maxScalar(0, s32); .maxScalar(0, s32);
// MIPS32r6 does not have alignment restrictions for memory access.
// For MIPS32r5 and older memory access must be naturally-aligned i.e. aligned
// to at least a multiple of its own size. There is however a two instruction
// combination that performs 4 byte unaligned access (lwr/lwl and swl/swr)
// therefore 4 byte load and store are legal and will use NoAlignRequirements.
bool NoAlignRequirements = true;
getActionDefinitionsBuilder({G_LOAD, G_STORE}) getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalIf([=, &ST](const LegalityQuery &Query) { .legalIf([=, &ST](const LegalityQuery &Query) {
if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()}, if (CheckTy0Ty1MemSizeAlign(
{s32, p0, 16, ST.hasMips32r6()}, Query, {{s32, p0, 8, NoAlignRequirements},
{s32, p0, 32, ST.hasMips32r6()}, {s32, p0, 16, ST.systemSupportsUnalignedAccess()},
{p0, p0, 32, ST.hasMips32r6()}, {s32, p0, 32, NoAlignRequirements},
{s64, p0, 64, ST.hasMips32r6()}})) {p0, p0, 32, NoAlignRequirements},
return true; {s64, p0, 64, ST.systemSupportsUnalignedAccess()}}))
if (ST.hasMSA() && return true;
CheckTy0Ty1MemSizeAlign(Query, {{v16s8, p0, 128, false}, if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign(
{v8s16, p0, 128, false}, Query, {{v16s8, p0, 128, NoAlignRequirements},
{v4s32, p0, 128, false}, {v8s16, p0, 128, NoAlignRequirements},
{v2s64, p0, 128, false}})) {v4s32, p0, 128, NoAlignRequirements},
{v2s64, p0, 128, NoAlignRequirements}}))
return true; return true;
return false; return false;
}) })
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_IMPLICIT_DEF) getActionDefinitionsBuilder(G_IMPLICIT_DEF)
.legalFor({s32, s64}); .legalFor({s32, s64});
▲ Show 20 Lines • Show All 378 Lines • Show Last 20 Lines

llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Linesstatic bool isFloatingPointOpcodeDef(unsigned Opc) {
case TargetOpcode::G_SITOFP: case TargetOpcode::G_SITOFP:
case TargetOpcode::G_UITOFP: case TargetOpcode::G_UITOFP:
return true; return true;
default: default:
return isFloatingPointOpcode(Opc); return isFloatingPointOpcode(Opc);
} }
} }
static bool isGprbTwoInstrUnalignedLoadOrStore(const MachineInstr *MI) {
if (MI->getOpcode() == TargetOpcode::G_LOAD ||
MI->getOpcode() == TargetOpcode::G_STORE) {
auto MMO = *MI->memoperands_begin();
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MI->getMF()->getSubtarget());
if (MMO->getSize() == 4 && (!STI.systemSupportsUnalignedAccess() &&
MMO->getSize() > MMO->getAlignment()))
return true;
}
return false;
}
static bool isAmbiguous(unsigned Opc) { static bool isAmbiguous(unsigned Opc) {
switch (Opc) { switch (Opc) {
case TargetOpcode::G_LOAD: case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE: case TargetOpcode::G_STORE:
case TargetOpcode::G_PHI: case TargetOpcode::G_PHI:
case TargetOpcode::G_SELECT: case TargetOpcode::G_SELECT:
case TargetOpcode::G_IMPLICIT_DEF: case TargetOpcode::G_IMPLICIT_DEF:
case TargetOpcode::G_UNMERGE_VALUES: case TargetOpcode::G_UNMERGE_VALUES:
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Linesbool MipsRegisterBankInfo::TypeInfoForMF::visit(
InstType &AmbiguousTy) { InstType &AmbiguousTy) {
assert(isAmbiguous(MI->getOpcode()) && "Visiting non-Ambiguous opcode.\n"); assert(isAmbiguous(MI->getOpcode()) && "Visiting non-Ambiguous opcode.\n");
if (wasVisited(MI)) if (wasVisited(MI))
return true; // InstType has already been determined for MI. return true; // InstType has already been determined for MI.
startVisit(MI); startVisit(MI);
AmbiguousRegDefUseContainer DefUseContainer(MI); AmbiguousRegDefUseContainer DefUseContainer(MI);
if (isGprbTwoInstrUnalignedLoadOrStore(MI)) {
setTypes(MI, Integer);
return true;
}
if (AmbiguousTy == InstType::Ambiguous && if (AmbiguousTy == InstType::Ambiguous &&
(MI->getOpcode() == TargetOpcode::G_MERGE_VALUES || (MI->getOpcode() == TargetOpcode::G_MERGE_VALUES ||
MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES)) MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES))
AmbiguousTy = InstType::AmbiguousWithMergeOrUnmerge; AmbiguousTy = InstType::AmbiguousWithMergeOrUnmerge;
// Visit instructions where MI's DEF operands are USED. // Visit instructions where MI's DEF operands are USED.
if (visitAdjacentInstrs(MI, DefUseContainer.getDefUses(), true, AmbiguousTy)) if (visitAdjacentInstrs(MI, DefUseContainer.getDefUses(), true, AmbiguousTy))
return true; return true;
▲ Show 20 Lines • Show All 485 Lines • Show Last 20 Lines

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align4 = common global float 0.000000e+00, align 4
@i32_align8 = common global i32 0, align 8
define float @load_float_align1() {
entry:
%0 = load float, float* @float_align1, align 1
ret float %0
}
define float @load_float_align4() {
entry:
%0 = load float, float* @float_align4, align 4
ret float %0
}
define i32 @load_i32_align8() {
entry:
%0 = load i32, i32* @i32_align8, align 8
ret i32 %0
}
...
---
name: load_float_align1
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_float_align1
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; MIPS32: [[LWL:%[0-9]+]]:gpr32 = LWL [[ADDiu]], 3, [[DEF]] :: (dereferenceable load 4 from @float_align1, align 1)
; MIPS32: [[LWR:%[0-9]+]]:gpr32 = LWR [[ADDiu]], 0, [[LWL]] :: (dereferenceable load 4 from @float_align1, align 1)
; MIPS32: $f0 = COPY [[LWR]]
; MIPS32: RetRA implicit $f0
%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_float_align4
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_float_align4
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
; MIPS32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load 4 from @float_align4)
; MIPS32: $f0 = COPY [[LWC1_]]
; MIPS32: RetRA implicit $f0
%1:gprb(p0) = G_GLOBAL_VALUE @float_align4
%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align4)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_i32_align8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i32_align8
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load 4 from @i32_align8, align 8)
; MIPS32: $v0 = COPY [[LW]]
; MIPS32: RetRA implicit $v0
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align8
%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align8, align 8)
$v0 = COPY %0(s32)
RetRA implicit $v0
...

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align8 = common global float 0.000000e+00, align 8
@i32_align2 = common global i32 0, align 2
define float @load_float_align1() {
entry:
%0 = load float, float* @float_align1, align 1
ret float %0
}
define float @load_float_align8() {
entry:
%0 = load float, float* @float_align8, align 8
ret float %0
}
define i32 @load_i32_align2() {
entry:
%0 = load i32, i32* @i32_align2, align 2
ret i32 %0
}
...
---
name: load_float_align1
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32R6-LABEL: name: load_float_align1
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load 4 from @float_align1, align 1)
; MIPS32R6: $f0 = COPY [[LWC1_]]
; MIPS32R6: RetRA implicit $f0
%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_float_align8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32R6-LABEL: name: load_float_align8
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load 4 from @float_align8, align 8)
; MIPS32R6: $f0 = COPY [[LWC1_]]
; MIPS32R6: RetRA implicit $f0
%1:gprb(p0) = G_GLOBAL_VALUE @float_align8
%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align8, align 8)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_i32_align2
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32R6-LABEL: name: load_i32_align2
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
; MIPS32R6: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load 4 from @i32_align2, align 2)
; MIPS32R6: $v0 = COPY [[LW]]
; MIPS32R6: RetRA implicit $v0
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align2, align 2)
$v0 = COPY %0(s32)
RetRA implicit $v0
...

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align4 = common global float 0.000000e+00, align 4
@i32_align8 = common global i32 0, align 8
define void @store_float_align1(float %a) {
entry:
store float %a, float* @float_align1, align 1
ret void
}
define void @store_float_align4(float %a) {
entry:
store float %a, float* @float_align4, align 4
ret void
}
define void @store_i32_align8(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align8, align 8
ret void
}
...
---
name: store_float_align1
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32-LABEL: name: store_float_align1
; MIPS32: liveins: $f12
; MIPS32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
; MIPS32: SWL [[COPY1]], [[ADDiu]], 3 :: (store 4 into @float_align1, align 1)
; MIPS32: SWR [[COPY1]], [[ADDiu]], 0 :: (store 4 into @float_align1, align 1)
; MIPS32: RetRA
%0:fprb(s32) = COPY $f12
%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
%2:gprb(s32) = COPY %0(s32)
G_STORE %2(s32), %1(p0) :: (store 4 into @float_align1, align 1)
RetRA
...
---
name: store_float_align4
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32-LABEL: name: store_float_align4
; MIPS32: liveins: $f12
; MIPS32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
; MIPS32: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align4)
; MIPS32: RetRA
%0:fprb(s32) = COPY $f12
%1:gprb(p0) = G_GLOBAL_VALUE @float_align4
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align4)
RetRA
...
---
name: store_i32_align8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: store_i32_align8
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
; MIPS32: SW [[COPY]], [[ADDiu]], 0 :: (store 4 into @i32_align8, align 8)
; MIPS32: RetRA
%0:gprb(s32) = COPY $a0
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align8
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align8, align 8)
RetRA
...

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align8 = common global float 0.000000e+00, align 8
@i32_align2 = common global i32 0, align 2
define void @store_float_align1(float %a) #0 {
entry:
store float %a, float* @float_align1, align 1
ret void
}
define void @store_float_align8(float %a) #0 {
entry:
store float %a, float* @float_align8, align 8
ret void
}
define void @store_i32_align2(i32 signext %a) #0 {
entry:
store i32 %a, i32* @i32_align2, align 2
ret void
}
...
---
name: store_float_align1
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32R6-LABEL: name: store_float_align1
; MIPS32R6: liveins: $f12
; MIPS32R6: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align1, align 1)
; MIPS32R6: RetRA
%0:fprb(s32) = COPY $f12
%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align1, align 1)
RetRA
...
---
name: store_float_align8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32R6-LABEL: name: store_float_align8
; MIPS32R6: liveins: $f12
; MIPS32R6: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store 4 into @float_align8, align 8)
; MIPS32R6: RetRA
%0:fprb(s32) = COPY $f12
%1:gprb(p0) = G_GLOBAL_VALUE @float_align8
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align8, align 8)
RetRA
...
---
name: store_i32_align2
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32R6-LABEL: name: store_i32_align2
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
; MIPS32R6: SW [[COPY]], [[ADDiu]], 0 :: (store 4 into @i32_align2, align 2)
; MIPS32R6: RetRA
%0:gprb(s32) = COPY $a0
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align2, align 2)
RetRA
...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align2 = common global float 0.000000e+00, align 2
@float_align4 = common global float 0.000000e+00, align 4
@float_align8 = common global float 0.000000e+00, align 8
@i32_align1 = common global i32 0, align 1
@i32_align2 = common global i32 0, align 2
@i32_align4 = common global i32 0, align 4
@i32_align8 = common global i32 0, align 8
define float @load_float_align1() {
entry:
%0 = load float, float* @float_align1, align 1
ret float %0
}
define float @load_float_align2() {
entry:
%0 = load float, float* @float_align2, align 2
ret float %0
}
define float @load_float_align4() {
entry:
%0 = load float, float* @float_align4, align 4
ret float %0
}
define float @load_float_align8() {
entry:
%0 = load float, float* @float_align8, align 8
ret float %0
}
define i32 @load_i32_align1() {
entry:
%0 = load i32, i32* @i32_align1, align 1
ret i32 %0
}
define i32 @load_i32_align2() {
entry:
%0 = load i32, i32* @i32_align2, align 2
ret i32 %0
}
define i32 @load_i32_align4() {
entry:
%0 = load i32, i32* @i32_align4, align 4
ret i32 %0
}
define i32 @load_i32_align8() {
entry:
%0 = load i32, i32* @i32_align8, align 8
ret i32 %0
}
...
---
name: load_float_align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_float_align1
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align1
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align1, align 1)
; MIPS32: $f0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $f0
; MIPS32R6-LABEL: name: load_float_align1
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align1
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align1, align 1)
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $f0
%1:_(p0) = G_GLOBAL_VALUE @float_align1
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_float_align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_float_align2
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align2
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align2, align 2)
; MIPS32: $f0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $f0
; MIPS32R6-LABEL: name: load_float_align2
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align2
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align2, align 2)
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $f0
%1:_(p0) = G_GLOBAL_VALUE @float_align2
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align2, align 2)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_float_align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_float_align4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align4
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align4)
; MIPS32: $f0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $f0
; MIPS32R6-LABEL: name: load_float_align4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align4
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align4)
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $f0
%1:_(p0) = G_GLOBAL_VALUE @float_align4
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align4)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_float_align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_float_align8
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align8
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align8, align 8)
; MIPS32: $f0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $f0
; MIPS32R6-LABEL: name: load_float_align8
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align8
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align8, align 8)
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $f0
%1:_(p0) = G_GLOBAL_VALUE @float_align8
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align8, align 8)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_i32_align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i32_align1
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align1, align 1)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load_i32_align1
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align1, align 1)
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $v0
%1:_(p0) = G_GLOBAL_VALUE @i32_align1
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align1, align 1)
$v0 = COPY %0(s32)
RetRA implicit $v0
...
---
name: load_i32_align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i32_align2
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align2, align 2)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load_i32_align2
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align2, align 2)
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $v0
%1:_(p0) = G_GLOBAL_VALUE @i32_align2
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align2, align 2)
$v0 = COPY %0(s32)
RetRA implicit $v0
...
---
name: load_i32_align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i32_align4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align4)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load_i32_align4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align4)
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $v0
%1:_(p0) = G_GLOBAL_VALUE @i32_align4
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align4)
$v0 = COPY %0(s32)
RetRA implicit $v0
...
---
name: load_i32_align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i32_align8
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align8, align 8)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load_i32_align8
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align8, align 8)
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $v0
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align8, align 8)
$v0 = COPY %0(s32)
RetRA implicit $v0
...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align2 = common global float 0.000000e+00, align 2
@float_align4 = common global float 0.000000e+00, align 4
@float_align8 = common global float 0.000000e+00, align 8
@i32_align1 = common global i32 0, align 1
@i32_align2 = common global i32 0, align 2
@i32_align4 = common global i32 0, align 4
@i32_align8 = common global i32 0, align 8
define void @store_float_align1(float %a) {
entry:
store float %a, float* @float_align1, align 1
ret void
}
define void @store_float_align2(float %a) {
entry:
store float %a, float* @float_align2, align 2
ret void
}
define void @store_float_align4(float %a) {
entry:
store float %a, float* @float_align4, align 4
ret void
}
define void @store_float_align8(float %a) {
entry:
store float %a, float* @float_align8, align 8
ret void
}
define void @store_i32_align1(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align1, align 1
ret void
}
define void @store_i32_align2(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align2, align 2
ret void
}
define void @store_i32_align4(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align4, align 4
ret void
}
define void @store_i32_align8(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align8, align 8
ret void
}
...
---
name: store_float_align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32-LABEL: name: store_float_align1
; MIPS32: liveins: $f12
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align1
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align1, align 1)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_float_align1
; MIPS32R6: liveins: $f12
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align1
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align1, align 1)
; MIPS32R6: RetRA
%0:_(s32) = COPY $f12
%1:_(p0) = G_GLOBAL_VALUE @float_align1
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align1, align 1)
RetRA
...
---
name: store_float_align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32-LABEL: name: store_float_align2
; MIPS32: liveins: $f12
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align2
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align2, align 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_float_align2
; MIPS32R6: liveins: $f12
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align2
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align2, align 2)
; MIPS32R6: RetRA
%0:_(s32) = COPY $f12
%1:_(p0) = G_GLOBAL_VALUE @float_align2
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align2, align 2)
RetRA
...
---
name: store_float_align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32-LABEL: name: store_float_align4
; MIPS32: liveins: $f12
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align4
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_float_align4
; MIPS32R6: liveins: $f12
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align4
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align4)
; MIPS32R6: RetRA
%0:_(s32) = COPY $f12
%1:_(p0) = G_GLOBAL_VALUE @float_align4
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align4)
RetRA
...
---
name: store_float_align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32-LABEL: name: store_float_align8
; MIPS32: liveins: $f12
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align8
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align8, align 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_float_align8
; MIPS32R6: liveins: $f12
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @float_align8
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align8, align 8)
; MIPS32R6: RetRA
%0:_(s32) = COPY $f12
%1:_(p0) = G_GLOBAL_VALUE @float_align8
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align8, align 8)
RetRA
...
---
name: store_i32_align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: store_i32_align1
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align1, align 1)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align1
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align1
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align1, align 1)
; MIPS32R6: RetRA
%0:_(s32) = COPY $a0
%1:_(p0) = G_GLOBAL_VALUE @i32_align1
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align1, align 1)
RetRA
...
---
name: store_i32_align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: store_i32_align2
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align2, align 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align2
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align2
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align2, align 2)
; MIPS32R6: RetRA
%0:_(s32) = COPY $a0
%1:_(p0) = G_GLOBAL_VALUE @i32_align2
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align2, align 2)
RetRA
...
---
name: store_i32_align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: store_i32_align4
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align4
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align4
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align4)
; MIPS32R6: RetRA
%0:_(s32) = COPY $a0
%1:_(p0) = G_GLOBAL_VALUE @i32_align4
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align4)
RetRA
...
---
name: store_i32_align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: store_i32_align8
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align8, align 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align8
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align8, align 8)
; MIPS32R6: RetRA
%0:_(s32) = COPY $a0
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align8, align 8)
RetRA
...

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r6 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32R6
@float_align1 = common global float 0.000000e+00, align 1
@float_align2 = common global float 0.000000e+00, align 2
@float_align4 = common global float 0.000000e+00, align 4
@float_align8 = common global float 0.000000e+00, align 8
@i32_align1 = common global i32 0, align 1
@i32_align2 = common global i32 0, align 2
@i32_align4 = common global i32 0, align 4
@i32_align8 = common global i32 0, align 8
define float @load_float_align1() {
; MIPS32-LABEL: load_float_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align1)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align1)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load_float_align1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(float_align1)
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align1)
; MIPS32R6-NEXT: lwc1 $f0, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = load float, float* @float_align1, align 1
ret float %0
}
define float @load_float_align2() {
; MIPS32-LABEL: load_float_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align2)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align2)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load_float_align2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(float_align2)
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align2)
; MIPS32R6-NEXT: lwc1 $f0, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = load float, float* @float_align2, align 2
ret float %0
}
define float @load_float_align4() {
; MIPS32-LABEL: load_float_align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align4)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align4)
; MIPS32-NEXT: lwc1 $f0, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load_float_align4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(float_align4)
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align4)
; MIPS32R6-NEXT: lwc1 $f0, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = load float, float* @float_align4, align 4
ret float %0
}
define float @load_float_align8() {
; MIPS32-LABEL: load_float_align8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align8)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align8)
; MIPS32-NEXT: lwc1 $f0, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load_float_align8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(float_align8)
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align8)
; MIPS32R6-NEXT: lwc1 $f0, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = load float, float* @float_align8, align 8
ret float %0
}
define i32 @load_i32_align1() {
; MIPS32-LABEL: load_i32_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align1)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align1)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load_i32_align1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(i32_align1)
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align1)
; MIPS32R6-NEXT: lw $2, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = load i32, i32* @i32_align1, align 1
ret i32 %0
}
define i32 @load_i32_align2() {
; MIPS32-LABEL: load_i32_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align2)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align2)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load_i32_align2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(i32_align2)
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align2)
; MIPS32R6-NEXT: lw $2, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = load i32, i32* @i32_align2, align 2
ret i32 %0
}
define i32 @load_i32_align4() {
; MIPS32-LABEL: load_i32_align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align4)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align4)
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load_i32_align4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(i32_align4)
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align4)
; MIPS32R6-NEXT: lw $2, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = load i32, i32* @i32_align4, align 4
ret i32 %0
}
define i32 @load_i32_align8() {
; MIPS32-LABEL: load_i32_align8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align8)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align8)
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load_i32_align8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(i32_align8)
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align8)
; MIPS32R6-NEXT: lw $2, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = load i32, i32* @i32_align8, align 8
ret i32 %0
}

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll

Show First 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
; MIPS32-NEXT: $BB5_4: # %cond.end ; MIPS32-NEXT: $BB5_4: # %cond.end
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload ; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1) ; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 32 ; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%0 = load i64, i64* %i64_ptr_a, align 4 %0 = load i64, i64* %i64_ptr_a, align 8
%1 = load i64, i64* %i64_ptr_b, align 4 %1 = load i64, i64* %i64_ptr_b, align 8
br i1 %cnd, label %cond.true, label %cond.false br i1 %cnd, label %cond.true, label %cond.false
cond.true: cond.true:
br label %cond.end br label %cond.end
cond.false: cond.false:
br label %cond.end br label %cond.end
cond.end: cond.end:
%cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ] %cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ]
store i64 %cond, i64* %i64_ptr_c, align 4 store i64 %cond, i64* %i64_ptr_c, align 8
ret void ret void
} }
define float @phi_float(i1 %cnd, float %a, float %b) { define float @phi_float(i1 %cnd, float %a, float %b) {
; MIPS32-LABEL: phi_float: ; MIPS32-LABEL: phi_float:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16 ; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16 ; MIPS32-NEXT: .cfi_def_cfa_offset 16
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r6 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32R6
@float_align1 = common global float 0.000000e+00, align 1
@float_align2 = common global float 0.000000e+00, align 2
@float_align4 = common global float 0.000000e+00, align 4
@float_align8 = common global float 0.000000e+00, align 8
@i32_align1 = common global i32 0, align 1
@i32_align2 = common global i32 0, align 2
@i32_align4 = common global i32 0, align 4
@i32_align8 = common global i32 0, align 8
define void @store_float_align1(float %a) {
; MIPS32-LABEL: store_float_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align1)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align1)
; MIPS32-NEXT: mfc1 $2, $f12
; MIPS32-NEXT: swl $2, 3($1)
; MIPS32-NEXT: swr $2, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store_float_align1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(float_align1)
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align1)
; MIPS32R6-NEXT: swc1 $f12, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
store float %a, float* @float_align1, align 1
ret void
}
define void @store_float_align2(float %a) {
; MIPS32-LABEL: store_float_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align2)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align2)
; MIPS32-NEXT: mfc1 $2, $f12
; MIPS32-NEXT: swl $2, 3($1)
; MIPS32-NEXT: swr $2, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store_float_align2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(float_align2)
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align2)
; MIPS32R6-NEXT: swc1 $f12, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
store float %a, float* @float_align2, align 2
ret void
}
define void @store_float_align4(float %a) {
; MIPS32-LABEL: store_float_align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align4)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align4)
; MIPS32-NEXT: swc1 $f12, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store_float_align4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(float_align4)
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align4)
; MIPS32R6-NEXT: swc1 $f12, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
store float %a, float* @float_align4, align 4
ret void
}
define void @store_float_align8(float %a) {
; MIPS32-LABEL: store_float_align8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align8)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align8)
; MIPS32-NEXT: swc1 $f12, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store_float_align8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(float_align8)
; MIPS32R6-NEXT: addiu $1, $1, %lo(float_align8)
; MIPS32R6-NEXT: swc1 $f12, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
store float %a, float* @float_align8, align 8
ret void
}
define void @store_i32_align1(i32 signext %a) {
; MIPS32-LABEL: store_i32_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align1)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align1)
; MIPS32-NEXT: swl $4, 3($1)
; MIPS32-NEXT: swr $4, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store_i32_align1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(i32_align1)
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align1)
; MIPS32R6-NEXT: sw $4, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
store i32 %a, i32* @i32_align1, align 1
ret void
}
define void @store_i32_align2(i32 signext %a) {
; MIPS32-LABEL: store_i32_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align2)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align2)
; MIPS32-NEXT: swl $4, 3($1)
; MIPS32-NEXT: swr $4, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store_i32_align2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(i32_align2)
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align2)
; MIPS32R6-NEXT: sw $4, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
store i32 %a, i32* @i32_align2, align 2
ret void
}
define void @store_i32_align4(i32 signext %a) {
; MIPS32-LABEL: store_i32_align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align4)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align4)
; MIPS32-NEXT: sw $4, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store_i32_align4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(i32_align4)
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align4)
; MIPS32R6-NEXT: sw $4, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
store i32 %a, i32* @i32_align4, align 4
ret void
}
define void @store_i32_align8(i32 signext %a) {
; MIPS32-LABEL: store_i32_align8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(i32_align8)
; MIPS32-NEXT: addiu $1, $1, %lo(i32_align8)
; MIPS32-NEXT: sw $4, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store_i32_align8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(i32_align8)
; MIPS32R6-NEXT: addiu $1, $1, %lo(i32_align8)
; MIPS32R6-NEXT: sw $4, 0($1)
; MIPS32R6-NEXT: jrc $ra
entry:
store i32 %a, i32* @i32_align8, align 8
ret void
}

llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align4 = common global float 0.000000e+00, align 4
@i32_align8 = common global i32 0, align 8
define float @load_float_align1() {
entry:
%0 = load float, float* @float_align1, align 1
ret float %0
}
define float @load_float_align4() {
entry:
%0 = load float, float* @float_align4, align 4
ret float %0
}
define i32 @load_i32_align8() {
entry:
%0 = load i32, i32* @i32_align8, align 8
ret i32 %0
}
...
---
name: load_float_align1
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_float_align1
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align1
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align1, align 1)
; MIPS32: $f0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $f0
; MIPS32R6-LABEL: name: load_float_align1
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align1
; MIPS32R6: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align1, align 1)
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $f0
%1:_(p0) = G_GLOBAL_VALUE @float_align1
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align1, align 1)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_float_align4
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_float_align4
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align4
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align4)
; MIPS32: $f0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $f0
; MIPS32R6-LABEL: name: load_float_align4
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align4
; MIPS32R6: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align4)
; MIPS32R6: $f0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $f0
%1:_(p0) = G_GLOBAL_VALUE @float_align4
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @float_align4)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_i32_align8
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i32_align8
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align8, align 8)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load_i32_align8
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32R6: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_align8, align 8)
; MIPS32R6: $v0 = COPY [[LOAD]](s32)
; MIPS32R6: RetRA implicit $v0
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
%0:_(s32) = G_LOAD %1(p0) :: (dereferenceable load 4 from @i32_align8, align 8)
$v0 = COPY %0(s32)
RetRA implicit $v0
...

llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir

Show All 28 Lines--- |
cond.end: ; preds = %cond.false, %cond.true cond.end: ; preds = %cond.false, %cond.true
%cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ] %cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ]
ret i64 %cond ret i64 %cond
} }
define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) { define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {
entry: entry:
%0 = load i64, i64* %i64_ptr_a, align 4 %0 = load i64, i64* %i64_ptr_a, align 8
%1 = load i64, i64* %i64_ptr_b, align 4 %1 = load i64, i64* %i64_ptr_b, align 8
br i1 %cnd, label %cond.true, label %cond.false br i1 %cnd, label %cond.true, label %cond.false
cond.true: ; preds = %entry cond.true: ; preds = %entry
br label %cond.end br label %cond.end
cond.false: ; preds = %entry cond.false: ; preds = %entry
br label %cond.end br label %cond.end
cond.end: ; preds = %cond.false, %cond.true cond.end: ; preds = %cond.false, %cond.true
%cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ] %cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ]
store i64 %cond, i64* %i64_ptr_c, align 4 store i64 %cond, i64* %i64_ptr_c, align 8
ret void ret void
} }
define float @phi_float(i1 %cnd, float %a, float %b) { define float @phi_float(i1 %cnd, float %a, float %b) {
entry: entry:
br i1 %cnd, label %cond.true, label %cond.false br i1 %cnd, label %cond.true, label %cond.false
cond.true: ; preds = %entry cond.true: ; preds = %entry
▲ Show 20 Lines • Show All 167 Lines • ▼ Show 20 Linesbody: |
; MIPS32-LABEL: name: phi_ambiguous_i64_in_fpr ; MIPS32-LABEL: name: phi_ambiguous_i64_in_fpr
; MIPS32: bb.0.entry: ; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS32: liveins: $a0, $a1, $a2, $a3 ; MIPS32: liveins: $a0, $a1, $a2, $a3
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2 ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3 ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
; MIPS32: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY1]](p0) :: (load 8 from %ir.i64_ptr_a, align 4) ; MIPS32: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY1]](p0) :: (load 8 from %ir.i64_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY2]](p0) :: (load 8 from %ir.i64_ptr_b, align 4) ; MIPS32: [[LOAD1:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY2]](p0) :: (load 8 from %ir.i64_ptr_b)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C]] ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2 ; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true: ; MIPS32: bb.1.cond.true:
; MIPS32: successors: %bb.3(0x80000000) ; MIPS32: successors: %bb.3(0x80000000)
; MIPS32: G_BR %bb.3 ; MIPS32: G_BR %bb.3
; MIPS32: bb.2.cond.false: ; MIPS32: bb.2.cond.false:
; MIPS32: successors: %bb.3(0x80000000) ; MIPS32: successors: %bb.3(0x80000000)
; MIPS32: bb.3.cond.end: ; MIPS32: bb.3.cond.end:
; MIPS32: [[PHI:%[0-9]+]]:fprb(s64) = G_PHI [[LOAD]](s64), %bb.1, [[LOAD1]](s64), %bb.2 ; MIPS32: [[PHI:%[0-9]+]]:fprb(s64) = G_PHI [[LOAD]](s64), %bb.1, [[LOAD1]](s64), %bb.2
; MIPS32: G_STORE [[PHI]](s64), [[COPY3]](p0) :: (store 8 into %ir.i64_ptr_c, align 4) ; MIPS32: G_STORE [[PHI]](s64), [[COPY3]](p0) :: (store 8 into %ir.i64_ptr_c)
; MIPS32: RetRA ; MIPS32: RetRA
bb.1.entry: bb.1.entry:
liveins: $a0, $a1, $a2, $a3 liveins: $a0, $a1, $a2, $a3
%4:_(s32) = COPY $a0 %4:_(s32) = COPY $a0
%1:_(p0) = COPY $a1 %1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2 %2:_(p0) = COPY $a2
%3:_(p0) = COPY $a3 %3:_(p0) = COPY $a3
%5:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.i64_ptr_a, align 4) %5:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.i64_ptr_a)
%6:_(s64) = G_LOAD %2(p0) :: (load 8 from %ir.i64_ptr_b, align 4) %6:_(s64) = G_LOAD %2(p0) :: (load 8 from %ir.i64_ptr_b)
%9:_(s32) = G_CONSTANT i32 1 %9:_(s32) = G_CONSTANT i32 1
%10:_(s32) = COPY %4(s32) %10:_(s32) = COPY %4(s32)
%8:_(s32) = G_AND %10, %9 %8:_(s32) = G_AND %10, %9
G_BRCOND %8(s32), %bb.2 G_BRCOND %8(s32), %bb.2
G_BR %bb.3 G_BR %bb.3
bb.2.cond.true: bb.2.cond.true:
G_BR %bb.4 G_BR %bb.4
bb.3.cond.false: bb.3.cond.false:
bb.4.cond.end: bb.4.cond.end:
%7:_(s64) = G_PHI %5(s64), %bb.2, %6(s64), %bb.3 %7:_(s64) = G_PHI %5(s64), %bb.2, %6(s64), %bb.3
G_STORE %7(s64), %3(p0) :: (store 8 into %ir.i64_ptr_c, align 4) G_STORE %7(s64), %3(p0) :: (store 8 into %ir.i64_ptr_c)
RetRA RetRA
... ...
--- ---
name: phi_float name: phi_float
alignment: 4 alignment: 4
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
▲ Show 20 Lines • Show All 155 Lines • Show Last 20 Lines

llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align4 = common global float 0.000000e+00, align 4
@i32_align8 = common global i32 0, align 8
define void @store_float_align1(float %a) {
entry:
store float %a, float* @float_align1, align 1
ret void
}
define void @store_float_align4(float %a) {
entry:
store float %a, float* @float_align4, align 4
ret void
}
define void @store_i32_align8(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align8, align 8
ret void
}
...
---
name: store_float_align1
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32-LABEL: name: store_float_align1
; MIPS32: liveins: $f12
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align1
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
; MIPS32: G_STORE [[COPY1]](s32), [[GV]](p0) :: (store 4 into @float_align1, align 1)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_float_align1
; MIPS32R6: liveins: $f12
; MIPS32R6: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align1
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align1, align 1)
; MIPS32R6: RetRA
%0:_(s32) = COPY $f12
%1:_(p0) = G_GLOBAL_VALUE @float_align1
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align1, align 1)
RetRA
...
---
name: store_float_align4
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; MIPS32-LABEL: name: store_float_align4
; MIPS32: liveins: $f12
; MIPS32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align4
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_float_align4
; MIPS32R6: liveins: $f12
; MIPS32R6: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @float_align4
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @float_align4)
; MIPS32R6: RetRA
%0:_(s32) = COPY $f12
%1:_(p0) = G_GLOBAL_VALUE @float_align4
G_STORE %0(s32), %1(p0) :: (store 4 into @float_align4)
RetRA
...
---
name: store_i32_align8
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: store_i32_align8
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align8, align 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store_i32_align8
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
; MIPS32R6: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @i32_align8
; MIPS32R6: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @i32_align8, align 8)
; MIPS32R6: RetRA
%0:_(s32) = COPY $a0
%1:_(p0) = G_GLOBAL_VALUE @i32_align8
G_STORE %0(s32), %1(p0) :: (store 4 into @i32_align8, align 8)
RetRA
...