[AArch64][GlobalISel] Don't always use all reg class in subreg class selection

[paquette]

Summary

Similar to D74504.

When the source is not on GPR32allRegClass or GPR64allRegClass, and we're doing a GPR subregister copy, the destination should not be on one of these register classes.

[aemerson]

LGTM.

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

if (I.isCopy()) {
     unsigned DstSize = TRI.getRegSizeInBits(*DstRC);
 
     // If we're doing a cross-bank copy on different-sized registers, we need
     // to do a bit more work.
     if (SrcSize > DstSize) {
       // We're doing a cross-bank copy into a smaller register. We need a
       // subregister copy. First, get a register class that's on the same bank
       // as the destination, but the same size as the source.
-      const TargetRegisterClass *SubregRC =
-          getMinClassForRegBank(DstRegBank, SrcSize, true);
+      //
+      // Also, note that if the source can be any GPR register, the destination
+      // can be any GPR register. If the source is in a smaller class, then we
+      // should respect that in the subregister's class as well.
+      bool SrcIsAllRegClass = SrcRC == &AArch64::GPR32allRegClass ||
+                              SrcRC == &AArch64::GPR64allRegClass;
+      const TargetRegisterClass *SubregRC = getMinClassForRegBank(
+          DstRegBank, SrcSize, SrcIsAllRegClass);
       assert(SubregRC && "Didn't get a register class for subreg?");
 
       // Get the appropriate subregister for the destination.
       unsigned SubReg = 0;
       if (!getSubRegForClass(DstRC, TRI, SubReg)) {
         LLVM_DEBUG(dbgs() << "Couldn't determine subregister for copy.\n");
         return false;
       }

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir

 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: dont_fold_shl_3
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   %copy:gpr64 = COPY $x0
   ; CHECK:   %shl:gpr64 = UBFMXri %copy, 62, 61
-  ; CHECK:   [[COPY:%[0-9]+]]:gpr64all = COPY %shl
-  ; CHECK:   [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
-  ; CHECK:   TBNZW [[COPY1]], 3, %bb.1
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY %shl.sub_32
+  ; CHECK:   TBNZW [[COPY]], 3, %bb.1
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   %second_use:gpr64sp = ORRXri %shl, 8000
   ; CHECK:   $x0 = COPY %second_use
   ; CHECK:   RET_ReallyLR implicit $x0
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0