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Differential D74504

[AArch64][GlobalISel] Try to use existing reg classes in getRegClassesForCopy
AcceptedPublic

Authored by paquette on Feb 12 2020, 1:29 PM.

Details

Reviewers
aemerson
Summary

When the source or destination of a copy already has a register class, we should use it when possible instead of computing it using getMinClassForRegBank.

We always set GetAllRegSet to true in getMinClassForRegBank when selecting copies. This is fine, but it has the side effect of adding extra copies in MIR tests, which can be annoying.

Diff Detail

Revision Contents

Diff 244261

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

Show First 20 Lines • Show All 679 Lines • ▼ Show 20 LinesgetRegClassesForCopy(MachineInstr &I, const TargetInstrInfo &TII,
// //
// FIXME: I'm not sure if this case holds true outside of copies. If it does, // FIXME: I'm not sure if this case holds true outside of copies. If it does,
// then we can pull it into the helpers that get the appropriate class for a // then we can pull it into the helpers that get the appropriate class for a
// register bank. Or make a new helper that carries along some constraint // register bank. Or make a new helper that carries along some constraint
// information. // information.
if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1)) if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1))
SrcSize = DstSize = 32; SrcSize = DstSize = 32;
return {getMinClassForRegBank(SrcRegBank, SrcSize, true), // Helper lambda to compute a register class.
getMinClassForRegBank(DstRegBank, DstSize, true)}; auto GetRC = [&MRI, &TRI](Register Reg, const RegisterBank &RB,
unsigned Size) {
// If we have a physical register, then we can't use MRI.
if (Register::isPhysicalRegister(Reg))
return TRI.getMinimalPhysRegClass(Reg);
// Check if the register already has a class.
if (const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg))
return RC;
// No class has been decided. Return a guess. We will assume that if we are
// on a GPR, that we can use any GPR (including things like SP).
return getMinClassForRegBank(RB, Size, /* GetAllRegSet = */ true);
};
const TargetRegisterClass *SrcRC = GetRC(SrcReg, SrcRegBank, SrcSize);
const TargetRegisterClass *DstRC = GetRC(DstReg, DstRegBank, DstSize);
return {SrcRC, DstRC};
} }
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) { const RegisterBankInfo &RBI) {
Register DstReg = I.getOperand(0).getReg(); Register DstReg = I.getOperand(0).getReg();
Register SrcReg = I.getOperand(1).getReg(); Register SrcReg = I.getOperand(1).getReg();
▲ Show 20 Lines • Show All 4,640 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir

Show First 20 Lines • Show All 407 Lines • ▼ Show 20 Lines bb.0:
; The mask used for the AND here is legal for producing a roW load. ; The mask used for the AND here is legal for producing a roW load.
; CHECK-LABEL: name: and_uxtw ; CHECK-LABEL: name: and_uxtw
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: %base:gpr64sp = COPY $x0 ; CHECK: %base:gpr64sp = COPY $x0
; CHECK: %imp:gpr64 = IMPLICIT_DEF ; CHECK: %imp:gpr64 = IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %imp ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %imp
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] ; CHECK: %load:gpr64 = LDRXroW %base, [[COPY1]], 0, 1 :: (load 8)
; CHECK: %load:gpr64 = LDRXroW %base, [[COPY2]], 0, 1 :: (load 8)
; CHECK: $x1 = COPY %load ; CHECK: $x1 = COPY %load
; CHECK: RET_ReallyLR implicit $x1 ; CHECK: RET_ReallyLR implicit $x1
%base:gpr(p0) = COPY $x0 %base:gpr(p0) = COPY $x0
%imp:gpr(s64) = G_IMPLICIT_DEF %imp:gpr(s64) = G_IMPLICIT_DEF
%mask:gpr(s64) = G_CONSTANT i64 4294967295 %mask:gpr(s64) = G_CONSTANT i64 4294967295
%and:gpr(s64) = G_AND %imp, %mask %and:gpr(s64) = G_AND %imp, %mask
%c:gpr(s64) = G_CONSTANT i64 8 %c:gpr(s64) = G_CONSTANT i64 8
%mul:gpr(s64) = G_MUL %c, %and %mul:gpr(s64) = G_MUL %c, %and
%ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64) %ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64)
%load:gpr(s64) = G_LOAD %ptr(p0) :: (load 8) %load:gpr(s64) = G_LOAD %ptr(p0) :: (load 8)
$x1 = COPY %load(s64) $x1 = COPY %load(s64)
RET_ReallyLR implicit $x1 RET_ReallyLR implicit $x1
... ...

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# #
# Check folding an AND into a G_BRCOND which has been matched as a TB(N)Z. # Check folding an AND into a G_BRCOND which has been matched as a TB(N)Z.
... ...
--- ---
name: fold_and_rhs name: fold_and_rhs
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: fold_and_rhs ; CHECK-LABEL: name: fold_and_rhs
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBNZW [[COPY]], 3, %bb.1
; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8 %bit:gpr(s64) = G_CONSTANT i64 8
Show All 17 Lines
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: fold_and_lhs ; CHECK-LABEL: name: fold_and_lhs
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBNZW [[COPY]], 3, %bb.1
; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8 %bit:gpr(s64) = G_CONSTANT i64 8
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regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: dont_fold_and ; CHECK-LABEL: name: dont_fold_and
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64 = COPY $x0 ; CHECK: %copy:gpr64 = COPY $x0
; CHECK: %fold_me:gpr64sp = ANDXri %copy, 4098 ; CHECK: %fold_me:gpr64sp = ANDXri %copy, 4098
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %fold_me ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %fold_me
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] ; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: TBNZW [[COPY2]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8 %bit:gpr(s64) = G_CONSTANT i64 8
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llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Linesbody: |
; CHECK-LABEL: name: dont_fold_more_than_one_use ; CHECK-LABEL: name: dont_fold_more_than_one_use
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: %copy:gpr32 = COPY $w0 ; CHECK: %copy:gpr32 = COPY $w0
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %copy, %subreg.sub_32 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %copy, %subreg.sub_32
; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31 ; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %zext ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %zext
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] ; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: TBNZW [[COPY2]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: $x0 = COPY %zext ; CHECK: $x0 = COPY %zext
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s32) = COPY $w0 %copy:gpr(s32) = COPY $w0
Show All 11 Lines

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# #
# Check folding a G_SHL into a G_BRCOND which has been matched as a TB(N)Z. # Check folding a G_SHL into a G_BRCOND which has been matched as a TB(N)Z.
... ...
--- ---
name: fold_shl name: fold_shl
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: fold_shl ; CHECK-LABEL: name: fold_shl
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBNZW [[COPY]], 2, %bb.1
; CHECK: TBNZW [[COPY1]], 2, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8 %bit:gpr(s64) = G_CONSTANT i64 8
Show All 18 Lines
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: dont_fold_shl_1 ; CHECK-LABEL: name: dont_fold_shl_1
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64 = COPY $x0 ; CHECK: %copy:gpr64 = COPY $x0
; CHECK: %fold_me:gpr64 = UBFMXri %copy, 59, 58 ; CHECK: %fold_me:gpr64 = UBFMXri %copy, 59, 58
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %fold_me ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %fold_me
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] ; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: TBNZW [[COPY2]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8 %bit:gpr(s64) = G_CONSTANT i64 8
Show All 19 Lines
body: | body: |
; CHECK-LABEL: name: dont_fold_shl_2 ; CHECK-LABEL: name: dont_fold_shl_2
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64 = COPY $x0 ; CHECK: %copy:gpr64 = COPY $x0
; CHECK: %fold_cst:gpr64 = MOVi64imm -5 ; CHECK: %fold_cst:gpr64 = MOVi64imm -5
; CHECK: %fold_me:gpr64 = LSLVXr %copy, %fold_cst ; CHECK: %fold_me:gpr64 = LSLVXr %copy, %fold_cst
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %fold_me ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %fold_me
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] ; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: TBNZW [[COPY2]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8 %bit:gpr(s64) = G_CONSTANT i64 8
Show All 19 Lines
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: dont_fold_shl_3 ; CHECK-LABEL: name: dont_fold_shl_3
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64 = COPY $x0 ; CHECK: %copy:gpr64 = COPY $x0
; CHECK: %shl:gpr64 = UBFMXri %copy, 62, 61 ; CHECK: %shl:gpr64 = UBFMXri %copy, 62, 61
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %shl ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %shl
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] ; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: TBNZW [[COPY2]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: %second_use:gpr64sp = ORRXri %shl, 8000 ; CHECK: %second_use:gpr64sp = ORRXri %shl, 8000
; CHECK: $x0 = COPY %second_use ; CHECK: $x0 = COPY %second_use
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
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alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: fold_ashr_in_range ; CHECK-LABEL: name: fold_ashr_in_range
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBNZW [[COPY]], 4, %bb.1
; CHECK: TBNZW [[COPY1]], 4, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8 %bit:gpr(s64) = G_CONSTANT i64 8
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llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
... ...
--- ---
name: fold_trunc name: fold_trunc
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: fold_trunc ; CHECK-LABEL: name: fold_trunc
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBNZW [[COPY]], 3, %bb.1
; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s32) = G_CONSTANT i32 8 %bit:gpr(s32) = G_CONSTANT i32 8
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llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
... ...
--- ---
name: flip_eq name: flip_eq
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: flip_eq ; CHECK-LABEL: name: flip_eq
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBNZW [[COPY]], 3, %bb.1
; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
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alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: flip_ne ; CHECK-LABEL: name: flip_ne
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBZW [[COPY]], 3, %bb.1
; CHECK: TBZW [[COPY1]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
; Same as eq case, but we should get a TBZW instead. ; Same as eq case, but we should get a TBZW instead.
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alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: dont_flip_eq ; CHECK-LABEL: name: dont_flip_eq
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBZW [[COPY]], 3, %bb.1
; CHECK: TBZW [[COPY1]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
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alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: dont_flip_ne ; CHECK-LABEL: name: dont_flip_ne
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBNZW [[COPY]], 3, %bb.1
; CHECK: TBNZW [[COPY1]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
; Same as eq case, but we should get a TBNZW instead. ; Same as eq case, but we should get a TBNZW instead.
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alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: xor_chain ; CHECK-LABEL: name: xor_chain
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64all = COPY $x0 ; CHECK: %copy:gpr64all = COPY $x0
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK: TBZW [[COPY]], 3, %bb.1
; CHECK: TBZW [[COPY1]], 3, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%bit:gpr(s64) = G_CONSTANT i64 8 %bit:gpr(s64) = G_CONSTANT i64 8
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llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir

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tracksRegLiveness: true tracksRegLiveness: true
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0: bb.0:
liveins: $x1, $x2 liveins: $x1, $x2
; CHECK-LABEL: name: add_and_s32_to_s64 ; CHECK-LABEL: name: add_and_s32_to_s64
; CHECK: liveins: $x1, $x2 ; CHECK: liveins: $x1, $x2
; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x1 ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x1
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
; CHECK: %add_lhs:gpr64sp = COPY $x2 ; CHECK: %add_lhs:gpr64sp = COPY $x2
; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16 ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY1]], 16
; CHECK: $x3 = COPY %res ; CHECK: $x3 = COPY %res
; CHECK: RET_ReallyLR implicit $x3 ; CHECK: RET_ReallyLR implicit $x3
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
%mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff %mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff
%ext:gpr(s64) = G_AND %1(s64), %mask %ext:gpr(s64) = G_AND %1(s64), %mask
%add_lhs:gpr(s64) = COPY $x2 %add_lhs:gpr(s64) = COPY $x2
%res:gpr(s64) = G_ADD %add_lhs, %ext %res:gpr(s64) = G_ADD %add_lhs, %ext
$x3 = COPY %res(s64) $x3 = COPY %res(s64)
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