[PowerPC][AIX] Spill and restore the non-volatile condition register bits.

[sfertile]

Summary

Extends the existing support for spilling and restoring the condition register to the linkage area for 32-bit targets, and enable for AIX.

[sfertile]

• Add missed 32-bit AIX mir test.
• Update comment on creating fixed stack object to linkage area to include AIX.
• Fix offset fixed stack object for crsaves refrences at for aix32.

[sfertile]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

2339

I didn't realize while working on this patch but I think I can separate this part of the change into a preceding NFC patch. Going to try that out now and commit it if it can be done NFC.

[cebowleratibm]

I would like to see some test coverage for the AIX CRSave assembly, whether we adapt the tests you've already updated or add a separate test. It seems 64-bit PPC Linux has a better way of handling a single CR save. If we choose not to use the same approach on AIX I'd like to understand why.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

744

const

926–927

Suggest "assert(IsPPC64)" here.

928

Why do we use MFOCRF8 for 64-bit Linux with 1 CR save but not on AIX?

952

I can't help but notice this block of logic is redundant to the block at 946. Can this be commoned under an "if (MustSaveCR)" block?

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

932

"thhe"

llvm/test/CodeGen/PowerPC/aix32-crsave.mir

2

I'd rather see an aix-crsave that handles both 32/64 or one crsave test that handles all subtargets.

22

Can you use CHECK-LABEL to ensure the expected block binds to the intended section?

llvm/test/CodeGen/PowerPC/ppc64-alloca-crspill.ll

2

I think it makes sense to change this to "alloca-crspill.ll" and add the 32-bit expected output for AIX.

[sfertile]

• Add const on local
• add an assert to express the codegen inside an if is meant for 64-bit only.
• add an aix-crspill test which checks the assembly output for both 64-bit and 32-bit AIX.
• Use CHECK-LABEL in aix32-crspill.mir test to restict the scope of other CHECK directives.
• Add checking of the fixed stack object in ppc64-crsave.mir test to match the aix32 test.

Forgot to exetend the alloca test to include 32-bit AIX.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

928

Because I'm not sure if its safe to do so on AIX. The V2 ELF ABI specifically allows saving only the clobbered crfields, the V1 ELF ABI does not. I can't find any documentation for AIX that specifies whether its safe to save only the clobbered fields, or if CR2,CR3 and CR4 must all be saved. If we are allowed to save a single field but save the entire register anyway we are pessimistically correct, if we have to save all 3 non-volatile cr fields and we only save the clobbered ones then our codegen is incorrect, so unless we can verify using 'mfocrf' is allowed on AIX we have to match the ELF V1 implementation.

FWIW I tested out clobbering a CR field with both XL and gcc on AIX and both use 'mfcr`, so I strongly doubt we can save only the clobbered non-volatile fields.

952

I don't think so because of the ordering with respect to the 'mflr' instruction inserted at line 961 above. I could pull the code out into a static helper or lambda if you like though.

llvm/test/CodeGen/PowerPC/aix32-crsave.mir

2

I added this test to mirror the ppc64 test. I can't handle both 32-bit and 64-bit targets with the same input mir. I think its important to have a test with mir as input which runs only the prologepilog pass to highlight exactly what is expected from the pass. I've added a separate IR to assembly test that exercises both 32-bit and 64-bit codegen on AIX.

22

Good suggestion. updated.

[sfertile]

• Rebased to pick up NFC commit for the ELF 32 cr save changes.
• Extended the alloca + cr save test to include 32-bit AIX.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

10

Usually, the default cpu level we set in the testcase is pwr4, can I ask why we want to test pwr7 here instead?

18

In case we might forget to update the testcase when we support AIX, can we leave an assertion in the code instead?

[sfertile]

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

10

Its just to match the ELF V1 runstep. There should be no particular difference between pwr4 and pwr7 for this test.

18

In what code?

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

1573–1574

If we don't expect this block is PPC64 bit only, should we remove the comment as well?

1631

same comment as above

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

10

I see. I slightly prefer checking pwr4 here though. Because if we are not consistent with our default cpu level, people review this in the future may have same doubt as me Is pwr7 triggering anything special in this testcase?

18

Sorry, I thought there was some boilerplate of save and restores of the callee saved gpr for AIX based on properly implement, bt it seems I am wrong.

34

Does this id difference matter? Can we use regex to replace it and combine these two lines?

70

Same comment as above

[sfertile]

• Removed stale comments.
• Renamed the check prefixes in the 64-bit crsave test related to mfocr and` mfcr` difference becuase it erroneously made it seem the difference was due to power8 vs power7 ISA.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

1573–1574

Good catch.

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

10

Good point. I picked poor names for the related checks too becuase PWR7/PWR8 makes it seem like only Power8 has the mfocrf instruction which isn't the case. Its just that the V2 abi allows saving a single field while the other ABIS do not (AFAIK). I've change the aix test to run for power4, updated the check prefixes and added a comment to help clear it up.

18

I see. So the problem is we don't flag the registers as having a fixed spill offset, which causes us to fall into the target independent spill/restore code which does something completely sensible but not ABI compliant. I don't want to disable spilling csrs completely because it will block a lot of other meaningful work: for example nothing in spec or lnt would compile anymore. I already have a follow on patch that fixes them that I will post once I commit this patch, so it won't be forgotten :)

34

Its not important now, but when I fix the callee saved gprs/fprs for AIX I expect them to end up with the same id: We are creating a stack object for the gpr csr when we should be creating a fixed stack object for it. I intend to update the test to consolidate all the ELF/AIX checks into normal CHECKS as part of that work.

[cebowleratibm]

I believe the current patch is sound and correct. I had one test suggestion and one suggestion to use a lambda to reuse some of the cr spill logic.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

952

I think the lambda is a good idea.

1770–1771

With removal of isSVR4ABI() on this code path, presumably this code behaves differently for 32-bit SVR4. Does this comment need to be updated or is this a bug?

llvm/test/CodeGen/PowerPC/aix-crspill.ll

48

I like this test because it validates we apply the correct mask on the restore, though I think a test that kills all 3 cr bits is also meaningful for assembly..

[sfertile]

• Added a lambda for building the instruction which moves the condition register into a scratch register to avoid dupication.
• Added an IR --> assembly test that verifies we restore all 3 non-volatile cr-fields.
• Removed a couple stale comments, and reworded another comment.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

1770–1771

Good catch, updated the comment.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix32-crsave.mir

66

formatting

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

88

formatting

[sfertile]

Fix formatting of CHECK lines in several of the lit tests.

[Xiangling_L]

LGTM with a minor comment

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

929

minor issue: inconsistency between how to get instruction TII.get(PPC::MFOCRF8) and MoveFromCondRegInst?

[cebowleratibm]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

929

I think the current code is the preferred form. I had asked for the IsPPC64 assertion above to clarify to the reader that it's ok to hard code MFOCRF8.

[sfertile]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

929

Like Chris says: MoveFromCondRegInst --> opcode depends on if we are targeting 32-bit or 64-bit codegen, while the hard-coded opcode is to call out explicitly that this code is 64-bit only (in conjunction with the assert).

llvm/lib/Target/PowerPC/PPCFrameLowering.h

public:
   /// getFramePointerSaveOffset - Return the previous frame offset to save the
   /// frame pointer.
   unsigned getFramePointerSaveOffset() const;
 
   /// getBasePointerSaveOffset - Return the previous frame offset to save the
   /// base pointer.
   unsigned getBasePointerSaveOffset() const;
 
-  /// getCRSaveOffset - Return the previous frame offset to save the
-  /// CR register.
-  unsigned getCRSaveOffset() const { return CRSaveOffset; }
-
   /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
   ///
   unsigned getLinkageSize() const { return LinkageSize; }
 
   const SpillSlot *
   getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
 
   bool enableShrinkWrapping(const MachineFunction &MF) const override;

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

 
 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
   // SVR4 ABI: First slot in the general register save area.
   return STI.isPPC64()
              ? -16U
              : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
 }
 
-static unsigned computeCRSaveOffset() {
-  // The condition register save offset needs to be updated for AIX PPC32.
-  return 8;
+static unsigned computeCRSaveOffset(const PPCSubtarget &STI) {
+  return (STI.isAIXABI() && !STI.isPPC64()) ? 4 : 8;
 }
 
 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
                           STI.getPlatformStackAlignment(), 0),
       Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
       TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
       FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
       LinkageSize(computeLinkageSize(Subtarget)),
       BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)),
-      CRSaveOffset(computeCRSaveOffset()) {}
+      CRSaveOffset(computeCRSaveOffset(Subtarget)) {}
 
 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
     unsigned &NumEntries) const {
   // Early exit if not using the SVR4 ABI.
   if (!Subtarget.isSVR4ABI()) {
     NumEntries = 0;
     return nullptr;
void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
   const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
 
   MachineModuleInfo &MMI = MF.getMMI();
   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
   DebugLoc dl;
-  bool needsCFI = MF.needsFrameMoves();
+  // AIX assembler does not support cfi directives.
+  const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI();
 
   // Get processor type.
   bool isPPC64 = Subtarget.isPPC64();
   // Get the ABI.
   bool isSVR4ABI = Subtarget.isSVR4ABI();
   bool isAIXABI = Subtarget.isAIXABI();
   bool isELFv2ABI = Subtarget.isELFv2ABI();
   assert((isSVR4ABI || isAIXABI) && "Unsupported PPC ABI.");
void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
                                                  : PPC::ORI );
   const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
                                               : PPC::OR );
   const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
                                                             : PPC::SUBFC);
   const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
                                                                : PPC::SUBFIC);
+  const MCInstrDesc &MoveFromCondRegInst = TII.get(isPPC64 ? PPC::MFCR8
+                                                           : PPC::MFCR);
+  const MCInstrDesc &StoreWordInst = TII.get(isPPC64 ? PPC::STW8 : PPC::STW);
 
   // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
   // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
   // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
   // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
   assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
          "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
 
void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   if (HasBP && MaxAlign > 1)
     assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
            "Invalid alignment!");
 
   // Frames of 32KB & larger require special handling because they cannot be
   // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
   bool isLargeFrame = !isInt<16>(NegFrameSize);
 
-  assert((isPPC64 || !MustSaveCR) &&
-         "Prologue CR saving supported only in 64-bit mode");
-
-  if (MustSaveCR && isAIXABI)
-    report_fatal_error("Prologue CR saving is unimplemented on AIX.");
-
   // Check if we can move the stack update instruction (stdu) down the prologue
   // past the callee saves. Hopefully this will avoid the situation where the
   // saves are waiting for the update on the store with update to complete.
   MachineBasicBlock::iterator StackUpdateLoc = MBBI;
   bool MovingStackUpdateDown = false;
 
   // Check if we can move the stack update.
   if (stackUpdateCanBeMoved(MF)) {
if (MovingStackUpdateDown) {
       for (CalleeSavedInfo CSI : Info) {
         int FrIdx = CSI.getFrameIdx();
         if (FrIdx < 0)
           MFI.setObjectOffset(FrIdx, MFI.getObjectOffset(FrIdx) + NegFrameSize);
       }
     }
   }
 
-  // If we need to spill the CR and the LR but we don't have two separate
-  // registers available, we must spill them one at a time
-  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
+  // Where in the prologue we move the CR fields depends on how many scratch
+  // registers we have, and if we need to save the link register or not. This
+  // lambda is to avoid duplicating the logic in 2 places.
+  auto BuildMoveFromCR = [&]() {
+    if (isELFv2ABI && MustSaveCRs.size() == 1) {
     // In the ELFv2 ABI, we are not required to save all CR fields.
-    // If only one or two CR fields are clobbered, it is more efficient to use
-    // mfocrf to selectively save just those fields, because mfocrf has short
+    // If only one CR field is clobbered, it is more efficient to use
+    // mfocrf to selectively save just that field, because mfocrf has short
     // latency compares to mfcr.
-    unsigned MfcrOpcode = PPC::MFCR8;
-    unsigned CrState = RegState::ImplicitKill;
-    if (isELFv2ABI && MustSaveCRs.size() == 1) {
-      MfcrOpcode = PPC::MFOCRF8;
-      CrState = RegState::Kill;
-    }
+      assert(isPPC64 && "V2 ABI is 64-bit only.");
       MachineInstrBuilder MIB =
-      BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
-    for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
-      MIB.addReg(MustSaveCRs[i], CrState);
-    BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
+          BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg);
+      MIB.addReg(MustSaveCRs[0], RegState::Kill);
+    } else {
+      MachineInstrBuilder MIB =
+          BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg);
+      for (unsigned CRfield : MustSaveCRs)
+        MIB.addReg(CRfield, RegState::ImplicitKill);
+    }
+  };
+
+  // If we need to spill the CR and the LR but we don't have two separate
+  // registers available, we must spill them one at a time
+  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
+    BuildMoveFromCR();
+    BuildMI(MBB, MBBI, dl, StoreWordInst)
         .addReg(TempReg, getKillRegState(true))
-      .addImm(getCRSaveOffset())
+        .addImm(CRSaveOffset)
         .addReg(SPReg);
   }
 
   if (MustSaveLR)
     BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
 
-  if (MustSaveCR &&
-      !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
-    // In the ELFv2 ABI, we are not required to save all CR fields.
-    // If only one or two CR fields are clobbered, it is more efficient to use
-    // mfocrf to selectively save just those fields, because mfocrf has short
-    // latency compares to mfcr.
-    unsigned MfcrOpcode = PPC::MFCR8;
-    unsigned CrState = RegState::ImplicitKill;
-    if (isELFv2ABI && MustSaveCRs.size() == 1) {
-      MfcrOpcode = PPC::MFOCRF8;
-      CrState = RegState::Kill;
-    }
-    MachineInstrBuilder MIB =
-      BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
-    for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
-      MIB.addReg(MustSaveCRs[i], CrState);
-  }
+  if (MustSaveCR && !(SingleScratchReg && MustSaveLR))
+    BuildMoveFromCR();
 
   if (HasRedZone) {
     if (HasFP)
       BuildMI(MBB, MBBI, dl, StoreInst)
         .addReg(FPReg)
         .addImm(FPOffset)
         .addReg(SPReg);
     if (FI->usesPICBase())
void PPCFrameLowering::emitPrologue(MachineFunction &MF,
 
   if (MustSaveLR)
     BuildMI(MBB, StackUpdateLoc, dl, StoreInst)
       .addReg(ScratchReg, getKillRegState(true))
       .addImm(LROffset)
       .addReg(SPReg);
 
   if (MustSaveCR &&
-      !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
+      !(SingleScratchReg && MustSaveLR)) {
     assert(HasRedZone && "A red zone is always available on PPC64");
-    BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
+    BuildMI(MBB, MBBI, dl, StoreWordInst)
       .addReg(TempReg, getKillRegState(true))
-      .addImm(getCRSaveOffset())
+      .addImm(CRSaveOffset)
       .addReg(SPReg);
   }
 
   // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
   if (!FrameSize)
     return;
 
   // Adjust stack pointer: r1 += NegFrameSize.
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
       // For 64-bit SVR4 when we have spilled CRs, the spill location
       // is SP+8, not a frame-relative slot.
       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
         // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
         // the whole CR word.  In the ELFv2 ABI, every CR that was
         // actually saved gets its own CFI record.
         unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
         unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
-            nullptr, MRI->getDwarfRegNum(CRReg, true), getCRSaveOffset()));
+            nullptr, MRI->getDwarfRegNum(CRReg, true), CRSaveOffset));
         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
             .addCFIIndex(CFIIndex);
         continue;
       }
 
       if (CSI[I].isSpilledToReg()) {
         unsigned SpilledReg = CSI[I].getDstReg();
         unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister(
void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
   const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
                                               : PPC::OR );
   const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
                                                   : PPC::ORI );
   const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
                                                    : PPC::ADDI );
   const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
                                                 : PPC::ADD4 );
-
+  const MCInstrDesc& LoadWordInst = TII.get( isPPC64 ? PPC::LWZ8
+                                                     : PPC::LWZ);
+  const MCInstrDesc& MoveToCRInst = TII.get( isPPC64 ? PPC::MTOCRF8
+                                                     : PPC::MTOCRF);
   int LROffset = getReturnSaveOffset();
 
   int FPOffset = 0;
 
   // Using the same bool variable as below to suppress compiler warnings.
   bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,
                                               &TempReg);
   assert(SingleScratchReg &&
if (FI->hasFastCall()) {
         .addReg(SPReg);
     }
   }
   assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
   // If there is no red zone, ScratchReg may be needed for holding a useful
   // value (although not the base register). Make sure it is not overwritten
   // too early.
 
-  assert((isPPC64 || !MustSaveCR) &&
-         "Epilogue CR restoring supported only in 64-bit mode");
-
   // If we need to restore both the LR and the CR and we only have one
   // available scratch register, we must do them one at a time.
   if (MustSaveCR && SingleScratchReg && MustSaveLR) {
     // Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
     // is live here.
     assert(HasRedZone && "Expecting red zone");
-    BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
-      .addImm(getCRSaveOffset())
+    BuildMI(MBB, MBBI, dl, LoadWordInst, TempReg)
+      .addImm(CRSaveOffset)
       .addReg(SPReg);
     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
+      BuildMI(MBB, MBBI, dl, MoveToCRInst, MustSaveCRs[i])
         .addReg(TempReg, getKillRegState(i == e-1));
   }
 
   // Delay restoring of the LR if ScratchReg is needed. This is ok, since
   // LR is stored in the caller's stack frame. ScratchReg will be needed
   // if RBReg is anything other than SP. We shouldn't use ScratchReg as
   // a base register anyway, because it may happen to be R0.
   bool LoadedLR = false;
   if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
     BuildMI(MBB, StackUpdateLoc, dl, LoadInst, ScratchReg)
       .addImm(LROffset+SPAdd)
       .addReg(RBReg);
     LoadedLR = true;
   }
 
   if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
-    // This will only occur for PPC64.
-    assert(isPPC64 && "Expecting 64-bit mode");
     assert(RBReg == SPReg && "Should be using SP as a base register");
-    BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
-      .addImm(getCRSaveOffset())
+    BuildMI(MBB, MBBI, dl, LoadWordInst, TempReg)
+      .addImm(CRSaveOffset)
       .addReg(RBReg);
   }
 
   if (HasFP) {
     // If there is red zone, restore FP directly, since SP has already been
     // restored. Otherwise, restore the value of FP into ScratchReg.
     if (HasRedZone || RBReg == SPReg)
       BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
if (RBReg != SPReg || SPAdd != 0) {
     // Now load the LR from the caller's stack frame.
     if (MustSaveLR && !LoadedLR)
       BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
         .addImm(LROffset)
         .addReg(SPReg);
   }
 
   if (MustSaveCR &&
-      !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
+      !(SingleScratchReg && MustSaveLR))
     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
-      BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
+      BuildMI(MBB, MBBI, dl, MoveToCRInst, MustSaveCRs[i])
         .addReg(TempReg, getKillRegState(i == e-1));
 
   if (MustSaveLR)
     BuildMI(MBB, StackUpdateLoc, dl, MTLRInst).addReg(ScratchReg);
 
   // Callee pop calling convention. Pop parameter/linkage area. Used for tail
   // call optimization
   if (IsReturnBlock) {
if (FI->usesPICBase())
     SavedRegs.reset(PPC::R30);
 
   // Reserve stack space to move the linkage area to in case of a tail call.
   int TCSPDelta = 0;
   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
       (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
     MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
   }
 
-  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
-  // function uses CR 2, 3, or 4. For 64-bit SVR4 we create a FixedStack
+  // Allocate the nonvolatile CR spill slot iff the function uses CR 2, 3, or 4.
+  // For 64-bit SVR4, and all flavors of AIX we create a FixedStack
   // object at the offset of the CR-save slot in the linkage area. The actual
   // save and restore of the condition register will be created as part of the
   // prologue and epilogue insertion, but the FixedStack object is needed to
   // keep the CalleSavedInfo valid.
-  if (Subtarget.isSVR4ABI() &&
-      (SavedRegs.test(PPC::CR2) || SavedRegs.test(PPC::CR3) ||
+  if ((SavedRegs.test(PPC::CR2) || SavedRegs.test(PPC::CR3) ||
        SavedRegs.test(PPC::CR4))) {
     const uint64_t SpillSize = 4; // Condition register is always 4 bytes.
-    const int64_t SpillOffset = Subtarget.isPPC64() ? 8 : -4;
+    const int64_t SpillOffset =
+        Subtarget.isPPC64() ? 8 : Subtarget.isAIXABI() ? 4 : -4;
     int FrameIdx =
         MFI.CreateFixedObject(SpillSize, SpillOffset,
                               /* IsImmutable */ true, /* IsAliased */ false);
     FI->setCRSpillFrameIndex(FrameIdx);
   }
 }
 
 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
bool PPCFrameLowering::assignCalleeSavedSpillSlots(
   }
   return AllSpilledToReg;
 }
 
 bool PPCFrameLowering::spillCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
     ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
 
-  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
-  // Return false otherwise to maintain pre-existing behavior.
-  if (!Subtarget.isSVR4ABI())
-    return false;
-
   MachineFunction *MF = MBB.getParent();
   const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
   PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
   bool MustSaveTOC = FI->mustSaveTOC();
   DebugLoc DL;
   bool CRSpilled = false;
   MachineInstrBuilder CRMIB;
 
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
 
     // The actual spill will happen in the prologue.
     if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
       continue;
 
     // Insert the spill to the stack frame.
     if (IsCRField) {
       PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
-      if (Subtarget.isPPC64()) {
+      if (!Subtarget.is32BitELFABI()) {
         // The actual spill will happen at the start of the prologue.
         FuncInfo->addMustSaveCR(Reg);
       } else {
         CRSpilled = true;
         FuncInfo->setSpillsCR();
 
         // 32-bit:  FP-relative.  Note that we made sure CR2-CR4 all have
         // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
static bool isCalleeSavedCR(unsigned Reg) {
   return PPC::CR2 == Reg || Reg == PPC::CR3 || Reg == PPC::CR4;
 }
 
 bool
 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         std::vector<CalleeSavedInfo> &CSI,
                                         const TargetRegisterInfo *TRI) const {
-
-  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
-  // Return false otherwise to maintain pre-existing behavior.
-  if (!Subtarget.isSVR4ABI())
-    return false;
-
   MachineFunction *MF = MBB.getParent();
   const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
   PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
   bool MustSaveTOC = FI->mustSaveTOC();
   bool CR2Spilled = false;
   bool CR3Spilled = false;
   bool CR4Spilled = false;
   unsigned CSIIndex = 0;
if (Reg == PPC::CR2) {
       continue;
     } else if (Reg == PPC::CR3) {
       CR3Spilled = true;
       continue;
     } else if (Reg == PPC::CR4) {
       CR4Spilled = true;
       continue;
     } else {
-      // When we first encounter a non-CR register after seeing at
+      // On 32-bit ELF when we first encounter a non-CR register after seeing at
       // least one CR register, restore all spilled CRs together.
       if (CR2Spilled || CR3Spilled || CR4Spilled) {
         bool is31 = needsFP(*MF);
         restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled, MBB, I, CSI,
                    CSIIndex);
         CR2Spilled = CR3Spilled = CR4Spilled = false;
       }
 
       if (CSI[i].isSpilledToReg()) {
         DebugLoc DL;
         NumPEReloadVSR++;

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
              .addReg(Reg, RegState::Kill);
 
   // Discard the pseudo instruction.
   MBB.erase(II);
 }
 
 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
                                            unsigned Reg, int &FrameIdx) const {
-  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
-  // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
-  // ABI, return true to prevent allocating an additional frame slot.
-  // For 64-bit, the CR save area is in the linkage area at SP+8; but we have
-  // created a FrameIndex to that spill slot to keep the CalleSaveInfos valid.
-  // For 32-bit, we have previously created the stack slot if needed, so return
-  // its FrameIdx.
-  if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
+  // For the nonvolatile condition registers (CR2, CR3, CR4) return true to
+  // prevent allocating an additional frame slot.
+  // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8,
+  // for 32-bit AIX the CR save area is in the linkage area at SP+4.
+  // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos
+  // valid.
+  // For 32-bit ELF, we have previously created the stack slot if needed, so
+  // return its FrameIdx.
+  if (PPC::CR2 <= Reg && Reg <= PPC::CR4) {
     FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
     return true;
   }
   return false;
 }
 
 // If the offset must be a multiple of some value, return what that value is.
 static unsigned offsetMinAlignForOpcode(unsigned OpC) {

llvm/test/CodeGen/PowerPC/aix-crspill.ll

+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -mcpu=pwr4 --mattr=-altivec \
+; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=64BIT %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -mcpu=pwr4 --mattr=-altivec \
+; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
+
+define dso_local signext i32 @killOne(i32 signext %i) {
+entry:
+  tail call void asm sideeffect "# Clobber CR", "~{cr4}"()
+  %call = call signext i32 @do_something(i32 %i)
+  ret i32 %call
+}
+
+define dso_local signext i32 @killAll(i32 signext %i) {
+entry:
+  tail call void asm sideeffect "# Clobber CR", "~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" ()
+  %call = call signext i32 @do_something(i32 %i)
+  ret i32 %call
+}
+
+declare signext i32 @do_something(i32 signext)
+
+; 64BIT-LABEL: .killOne:
+
+; 64BIT:       mflr 0
+; 64BIT-NEXT:  std 0, 16(1)
+; 64BIT-NEXT:  mfcr 12
+; 64BIT-NEXT:  stw 12, 8(1)
+; 64BIT:       stdu 1, -112(1)
+
+; 64BIT:       # Clobber CR
+; 64BIT:       bl .do_something
+
+; 64BIT:       addi 1, 1, 112
+; 64BIT-NEXT:  ld 0, 16(1)
+; 64BIT-NEXT:  lwz 12, 8(1)
+; 64BIT-NEXT:  mtlr 0
+; 64BIT-NEXT:  mtocrf 8, 12
+; 64BIT:       blr
+
+; 32BIT-LABEL: .killOne:
+
+; 32BIT:       mflr 0
+; 32BIT-NEXT:  stw 0, 8(1)
+; 32BIT-NEXT:  mfcr 12
+; 32BIT-NEXT:  stw 12, 4(1)
+; 32BIT:       stwu 1, -64(1)
+
+; 32BIT:       # Clobber CR
+; 32BIT:       bl .do_something
+
+; 32BIT:       addi 1, 1, 64
+; 32BIT-NEXT:  lwz 0, 8(1)
+; 32BIT-NEXT:  lwz 12, 4(1)
+; 32BIT-NEXT:  mtlr 0
+; 32BIT-NEXT:  mtocrf 8, 12
+; 32BIT:       blr
+
+
+; 64BIT-LABEL: .killAll:
+
+; 64BIT:        addi 1, 1, 112
+; 64BIT-NEXT:   ld 0, 16(1)
+; 64BIT-NEXT:   lwz 12, 8(1)
+; 64BIT-NEXT:   mtlr 0
+; 64BIT-NEXT:   mtocrf 32, 12
+; 64BIT-NEXT:   mtocrf 16, 12
+; 64BIT-NEXT:   mtocrf 8, 12
+; 64BIT-NEXT:   blr
+
+
+; 32BIT-LABEL: .killAll:
+
+; 32BIT:        addi 1, 1, 64
+; 32BIT-NEXT:   lwz 0, 8(1)
+; 32BIT-NEXT:   lwz 12, 4(1)
+; 32BIT-NEXT:   mtlr 0
+; 32BIT-NEXT:   mtocrf 32, 12
+; 32BIT-NEXT:   mtocrf 16, 12
+; 32BIT-NEXT:   mtocrf 8, 12
+; 32BIT-NEXT:   blr

llvm/test/CodeGen/PowerPC/aix32-crsave.mir

+# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
+# RUN: FileCheck %s --check-prefixes=CHECK
+
+---
+name:            CRMultiSave
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$r3', virtual-reg: '' }
+body:             |
+  bb.0.entry:
+    liveins: $r3
+    renamable $r29 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+    renamable $cr2lt = COPY $cr0gt
+    renamable $cr4lt = COPY $cr0gt
+    renamable $r3 = COPY $r29
+    BLR implicit $lr, implicit $rm, implicit $r3
+
+    ; CHECK-LABEL: fixedStack:
+    ; CHECK:       - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
+    ; CHECK-NEXT:      isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
+    ; CHECK-NEXT:      callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
+    ; CHECK-NEXT:      debug-info-location: '' }
+    ; CHECK-LABEL: stack:
+
+    ; CHECK:      bb.0.entry:
+    ; CHECK-NEXT:  liveins: $r3, $r29, $cr2, $cr4
+
+    ; CHECK:      $r12 = MFCR implicit killed $cr2, implicit killed $cr4
+    ; CHECK-NEXT: STW killed $r12, 4, $r1
+
+    ; CHECK:      $r12 = LWZ 4, $r1
+    ; CHECK-NEXT: $cr2 = MTOCRF $r12
+    ; CHECK-NEXT: $cr4 = MTOCRF killed $r12
+
+...
+---
+name:            CR3Save
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$r3', virtual-reg: '' }
+body:             |
+  bb.0.entry:
+    liveins: $r3
+    renamable $r14 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+    renamable $cr3lt = COPY $cr0gt
+    renamable $r3 = COPY $r14
+    BLR implicit $lr, implicit $rm, implicit $r3
+
+    ; CHECK-LABEL: fixedStack:
+    ; CHECK:       - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
+    ; CHECK-NEXT:      isImmutable: true, isAliased: false, callee-saved-register: '$cr3',
+    ; CHECK-NEXT:      callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
+    ; CHECK-NEXT:      debug-info-location: '' }
+    ; CHECK-LABEL: stack:
+
+    ; CHECK:      bb.0.entry:
+    ; CHECK-NEXT:   liveins: $r3, $r14, $cr3
+
+    ; CHECK:      $r12 = MFCR implicit killed $cr3
+    ; CHECK-NEXT: STW killed $r12, 4, $r1
+
+    ; CHECK:      $r12 = LWZ 4, $r1
+    ; CHECK-NEXT: $cr3 = MTOCRF killed $r12

llvm/test/CodeGen/PowerPC/alloca-crspill.ll

+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu --verify-machineinstrs \
+; RUN: -stop-after=prologepilog < %s | FileCheck \
+; RUN: --check-prefixes=CHECK,CHECK64,ELFV2 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -mcpu=pwr4 \
+; RUN: --verify-machineinstrs --mattr=-altivec -stop-after=prologepilog < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,CHECK64,V1ANDAIX  %s
+
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 --verify-machineinstrs \
+; RUN: -stop-after=prologepilog < %s | FileCheck \
+; RUN: --check-prefixes=CHECK,CHECK64,V1ANDAIX %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -mcpu=pwr4 \
+; RUN: --verify-machineinstrs --mattr=-altivec -stop-after=prologepilog < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,CHECK32  %s
+
+define dso_local signext i32 @test(i32 signext %n) {
+entry:
+  %conv = sext i32 %n to i64
+  %0 = alloca double, i64 %conv, align 16
+  tail call void asm sideeffect "", "~{cr2}"()
+  %call = call signext i32 @do_something(double* nonnull %0)
+  ret i32 %call
+}
+
+declare signext i32 @do_something(double*)
+
+; CHECK: name:            test
+; CHECK: alignment:       16
+; CHECK: liveins:
+; CHECK64:   - { reg: '$x3', virtual-reg: '' }
+; CHECK32:   - { reg: '$r3', virtual-reg: '' }
+
+; ELFV2:    stackSize:       48
+; V1ANDAIX: stackSize:       128
+; CHECK32:  stackSize:       80
+
+; ELFV2:    maxCallFrameSize: 32
+; V1ANDAIX: maxCallFrameSize: 112
+; CHECK32:  maxCallFrameSize: 64
+
+; CHECK64:      fixedStack:
+; CHECK64-NEXT:   - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
+; CHECK64-NEXT:       isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
+; CHECK64-NEXT:       callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
+; CHECK64-NEXT:       debug-info-location: '' }
+; CHECK64-NEXT:   - { id: 1, type: default, offset: -8, size: 8, alignment: 8, stack-id: default,
+; CHECK64-NEXT:       isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+; CHECK64-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+; CHECK64-NEXT: stack:
+; CHECK64-NEXT:   - { id: 0, name: '<unnamed alloca>', type: variable-sized, offset: -8,
+; CHECK64-NEXT:       alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+; CHECK64-NEXT:       local-offset: 0, debug-info-variable: '', debug-info-expression: '',
+; CHECK64-NEXT:       debug-info-location: '' }
+; CHECK64-NEXT:   - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8,
+; CHECK64-NEXT:       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+; CHECK64-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+
+; CHECK32:      fixedStack:
+; CHECK32-NEXT:   - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
+; CHECK32-NEXT:       isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
+; CHECK32-NEXT:       callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
+; CHECK32-NEXT:       debug-info-location: '' }
+; CHECK32-NEXT:   - { id: 1, type: default, offset: -4, size: 4, alignment: 4, stack-id: default,
+; CHECK32-NEXT:       isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+; CHECK32-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+; CHECK32-NEXT: stack:
+; CHECK32-NEXT:   - { id: 0, name: '<unnamed alloca>', type: variable-sized, offset: -4,
+; CHECK32-NEXT:       alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+; CHECK32-NEXT:       local-offset: 0, debug-info-variable: '', debug-info-expression: '',
+; CHECK32-NEXT:       debug-info-location: '' }
+; CHECK32-NEXT:   - { id: 1, name: '', type: default, offset: -8, size: 4, alignment: 4,
+; CHECK32-NEXT:       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+; CHECK32-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+
+; CHECK64:      bb.0.entry:
+; CHECK64-NEXT:  liveins: $x3, $cr2
+
+; Prologue:
+; CHECK64:         $x0 = MFLR8 implicit $lr8
+; ELFV2-NEXT:      $x12 = MFOCRF8 killed $cr2
+; V1ANDAIX-NEXT:   $x12 = MFCR8 implicit killed $cr2
+; CHECK64-DAG:     STD $x31, -8, $x1
+; CHECK64-DAG:     STD killed $x0, 16, $x1
+; CHECK64-DAG:     STW8 killed $x12, 8, $x1
+
+; ELFV2-NEXT:      $x1 = STDU $x1, -48, $x1
+; V1ANDAIX-NEXT:   x1 = STDU $x1, -128, $x1
+
+; CHECK64:         $x31 = OR8 $x1, $x1
+
+; ELFV2:    $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 48
+; V1ANDAIX: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 128
+; CHECK64:  $x1 = STDUX killed $[[ORIGSP]], $x1, killed $x{{[0-9]}}
+; CHECK64:  INLINEASM {{.*}} early-clobber $cr2
+; CHECK64:  BL8_NOP
+
+
+; Epilogue:
+; CHECK64:       $x1 = LD 0, $x1
+; CHECK64-DAG:   $x0 = LD 16, $x1
+; CHECK64-DAG:   $x12 = LWZ8 8, $x1
+; CHECK64-DAG:   $x31 = LD -8, $x1
+; CHECK64:       $cr2 = MTOCRF8 killed $x12
+; CHECK64-NEXT:  MTLR8 $x0, implicit-def $lr8
+; CHECK64-NEXT:  BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+; CHECK32:       bb.0.entry:
+; CHECK32-NEXT:    liveins: $r3, $cr2
+
+; Prologue:
+; CHECK32:       $r0 = MFLR implicit $lr
+; CHECK32-NEXT:  $r12 = MFCR implicit killed $cr2
+; CHECK32-DAG:   STW $r31, -4, $r1
+; CHECK32-DAG:   STW killed $r0, 8, $r1
+; CHECK32-DAG:   STW killed $r12, 4, $r1
+; CHECK32:       $r1 = STWU $r1, -80, $r1
+
+; CHECK32:       $r31 = OR $r1, $r1
+; CHECK32:       $[[ORIGSP:r[0-9]+]] = ADDI $r31, 80
+; CHECK32:       $r1 = STWUX killed $[[ORIGSP]], $r1, killed $r{{[0-9]}}
+; CHECK32:       INLINEASM {{.*}} early-clobber $cr2
+; CHECK32:       BL_NOP
+
+; Epilogue:
+; CHECK32:       $r1 = LWZ 0, $r1
+; CHECK32-DAG:   $r0 = LWZ 8, $r1
+; CHECK32-DAG:   $r12 = LWZ 4, $r1
+; CHECK32-DAG:   $r31 = LWZ -4, $r1
+; CHECK32:       $cr2 = MTOCRF killed $r12
+; CHECK32-NEXT:  MTLR $r0, implicit-def $lr
+; CHECK32-NEXT:  BLR implicit $lr, implicit $rm, implicit $r3

llvm/test/CodeGen/PowerPC/ppc64-alloca-crspill.ll

-; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu --verify-machineinstrs \
-; RUN: -stop-after=prologepilog < %s | FileCheck %s
-
-define dso_local signext i32 @test(i32 signext %n) {
-entry:
-  %conv = sext i32 %n to i64
-  %0 = alloca double, i64 %conv, align 16
-  tail call void asm sideeffect "", "~{cr2}"()
-  %call = call signext i32 @do_something(double* nonnull %0)
-  ret i32 %call
-}
-
-declare signext i32 @do_something(double*)
-
-; CHECK: name:            test
-; CHECK: alignment:       16
-; CHECK: liveins:
-; CHECK:   - { reg: '$x3', virtual-reg: '' }
-; CHECK: stackSize:       48
-; CHECK: maxCallFrameSize: 32
-
-; CHECK:      fixedStack:
-; CHECK-NEXT:   - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
-; CHECK-NEXT:       isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
-; CHECK-NEXT:       callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
-; CHECK-NEXT:       debug-info-location: '' }
-; CHECK-NEXT:   - { id: 1, type: default, offset: -8, size: 8, alignment: 8, stack-id: default,
-; CHECK-NEXT:       isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
-; CHECK-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-
-; CHECK-NEXT: stack:
-; CHECK-NEXT:   - { id: 0, name: '<unnamed alloca>', type: variable-sized, offset: -8,
-; CHECK-NEXT:       alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
-; CHECK-NEXT:       local-offset: 0, debug-info-variable: '', debug-info-expression: '',
-; CHECK-NEXT:       debug-info-location: '' }
-; CHECK-NEXT:   - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8,
-; CHECK-NEXT:       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
-; CHECK-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-
-; CHECK:      bb.0.entry:
-; CHECK-NEXT:  liveins: $x3, $cr2
-
-; Prologue:
-; CHECK:       $x0 = MFLR8 implicit $lr8
-; CHECK-NEXT:  $x12 = MFOCRF8 killed $cr2
-; CHECK-DAG:   STD $x31, -8, $x1
-; CHECK-DAG:   STD killed $x0, 16, $x1
-; CHECK-DAG:   STW8 killed $x12, 8, $x1
-; CHECK-NEXT:  $x1 = STDU $x1, -48, $x1
-; CHECK:       $x31 = OR8 $x1, $x1
-
-; CHECK: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 48
-; CHECK: $x1 = STDUX killed $[[ORIGSP]], $x1, killed $x{{[0-9]}}
-; CHECK: INLINEASM {{.*}} early-clobber $cr2
-; CHECK: BL8_NOP @do_something
-
-
-; Epilogue:
-; CHECK:       $x1 = LD 0, $x1
-; CHECK-DAG:   $x0 = LD 16, $x1
-; CHECK-DAG:   $x12 = LWZ8 8, $x1
-; CHECK-DAG:   $x31 = LD -8, $x1
-; CHECK:       $cr2 = MTOCRF8 killed $x12
-; CHECK-NEXT:  MTLR8 $x0, implicit-def $lr8
-; CHECK-NEXT:  BLR8 implicit $lr8, implicit $rm, implicit $x3
-

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

 # RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK,PWR8
+# RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE,ELF
 
 # RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK,PWR7
+# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL,ELF
+
+
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
+# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
+# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
+
+# TODO FIXME: We only check the save and restores of the callee saved gpr for
+# ELF becuase AIX callee saved registers haven't been properly implemented yet.
 
 ---
 name:            CRAllSave
 alignment:       16
 tracksRegLiveness: true
 liveins:
   - { reg: '$x3', virtual-reg: '' }
 body:             |
   bb.0.entry:
     liveins: $x3
     renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
     renamable $cr2lt = COPY $cr0gt
     renamable $cr4lt = COPY $cr0gt
     renamable $x3 = COPY $x29
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
+    ; CHECK-LABEL: fixedStack:
+    ; ELF:          - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
+    ; AIX:          - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
+    ; CHECK:            isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
+    ; CHECK-NEXT:       callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
+    ; CHECK-NEXT:       debug-info-location: '' }
+    ; CHECK-LABEL:  stack:
+
     ; Verify the proper live-ins have been added in the prologue.
     ; CHECK:    liveins: $x3, $x29, $cr2, $cr4
 
     ; CHECK:     $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
-    ; CHECK-DAG: STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.0)
+    ; ELF-DAG:   STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.0)
     ; CHECK-DAG: STW8 killed $x12, 8, $x1
 
-    ; CHECK:     $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.0)
+    ; ELF:       $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.0)
     ; CHECK:     $x12 = LWZ8 8, $x1
     ; CHECK:     $cr2 = MTOCRF8 $x12
     ; CHECK:     $cr4 = MTOCRF8 killed $x12
 
-
 ...
 ---
 name:            CR2Save
 alignment:       16
 tracksRegLiveness: true
 liveins:
   - { reg: '$x3', virtual-reg: '' }
 body:             |
   bb.0.entry:
     liveins: $x3
     renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
     renamable $cr2lt = COPY $cr0gt
     renamable $x3 = COPY $x14
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
-    ; CHECK: CR2Save
+    ; CHECK-LABEL: CR2Save
+
+    ; CHECK-LABEL: fixedStack:
+    ; ELF:          - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
+    ; AIX:          - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
+    ; CHECK:            isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
+    ; CHECK-NEXT:       callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
+    ; CHECK-NEXT:       debug-info-location: '' }
+    ; CHECK-LABEL:  stack:
+
     ; Verify the proper live-ins have been added in the prologue.
     ; CHECK:    liveins: $x3, $x14, $cr2
 
-    ; PWR8:     $x12 = MFOCRF8 killed $cr2
-    ; PWR7:     $x12 = MFCR8 implicit killed $cr2
+    ; ELF V2 ABI allows saving only the clobbered cr fields,
+    ; whereas the other ABIs do not.
+    ; SAVEONE:     $x12 = MFOCRF8 killed $cr2
+    ; SAVEALL:     $x12 = MFCR8 implicit killed $cr2
 
-    ; CHECK-DAG: STD killed $x14, -144, $x1 :: (store 8 into %fixed-stack.0, align 16)
+    ; ELF-DAG:   STD killed $x14, -144, $x1 :: (store 8 into %fixed-stack.0, align 16)
     ; CHECK-DAG: STW8 killed $x12, 8, $x1
 
-    ; CHECK:     $x14 = LD -144, $x1 :: (load 8 from %fixed-stack.0, align 16)
+    ; ELF:       $x14 = LD -144, $x1 :: (load 8 from %fixed-stack.0, align 16)
     ; CHECK:     $x12 = LWZ8 8, $x1
     ; CHECK:     $cr2 = MTOCRF8 killed $x12
 
 
 ...