[TargetInstrInfo] Add the isCandidateForCallSiteEntry()

[djtodoro]

Summary

Define the isCandidateForCallSiteEntry() that should define instructions that are candidates for the call site info.
Override the virtual method for the x86, ARM and AARCH64 targets.

[vsk]

Hey @djtodoro, thanks for doing this. This patch takes a whitelisting approach, and might be tricky to test. I'm also not sure how to check that it is exhaustively correct.

I had in mind (what seems to me to be) a simpler/generic blacklisting approach. I hope you don't mind, I implemented the alternative in https://reviews.llvm.org/D74159. I believe the rest of your patches in this stack could be rebased on D74159 easily.

[djtodoro]

Sounds good to me, if the D74159 defines all the instructions we want to avoid.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
   /// immediate value and a physical register, and stores the result in
   /// the given physical register \c Reg, return a pair of the source
   /// register and the offset which has been added.
   virtual Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
                                               Register Reg) const {
     return None;
   }
 
+  /// Return true if the \c MI is a candidate for the call site info
+  /// (the 'callSites:') production.
+  virtual bool isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                           bool IgnoreBundle = false) const {
+    return false;
+  }
+
   /// Store the specified register of the given register class to the specified
   /// stack frame index. The store instruction is to be added to the given
   /// machine basic block before the specified machine instruction. If isKill
   /// is true, the register operand is the last use and must be marked kill.
   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    Register SrcReg, bool isKill, int FrameIndex,
                                    const TargetRegisterClass *RC,

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

if (Before == BB->end()) {
       // There were no prior instructions; the new ones must start at the
       // beginning of the block.
       MI = &Emitter.getBlock()->instr_front();
     } else {
       // Return first instruction after the pre-existing instructions.
       MI = &*std::next(Before);
     }
 
-    if (MI->isCall() && DAG->getTarget().Options.EnableDebugEntryValues)
+    if (TII->isCandidateForCallSiteEntry(*MI) &&
+        DAG->getTarget().Options.EnableDebugEntryValues)
       MF.addCallArgsForwardingRegs(MI, DAG->getSDCallSiteInfo(Node));
 
     return MI;
   };
 
   // If this is the first BB, emit byval parameter dbg_value's.
   if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
     SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();

llvm/lib/Target/AArch64/AArch64InstrInfo.h

public:
   static bool isSEHInstruction(const MachineInstr &MI);
 
   Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
                                       Register Reg) const override;
 
   Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
                                                  Register Reg) const override;
 
+  /// Return true if the \c MI is a candidate for the call site info
+  /// (the 'callSites:') production.
+  bool isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                   bool IgnoreBundle = false) const override;
+
 #define GET_INSTRINFO_HELPER_DECLS
 #include "AArch64GenInstrInfo.inc"
 
 protected:
   /// If the specific machine instruction is an instruction that moves/copies
   /// value from one register to another register return destination and source
   /// registers as machine operands.
   Optional<DestSourcePair>

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

AArch64InstrInfo::describeLoadedValue(const MachineInstr &MI,
   case AArch64::ORRWrs:
   case AArch64::ORRXrs:
     return describeORRLoadedValue(MI, Reg, this, TRI);
   }
 
   return TargetInstrInfo::describeLoadedValue(MI, Reg);
 }
 
+bool AArch64InstrInfo::isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                                   bool IgnoreBundle) const {
+  bool IsCall = IgnoreBundle ? MI.isCall(MachineInstr::IgnoreBundle) :
+                               MI.isCall();
+  if (!IsCall)
+    return false;
+
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case AArch64::BL:
+  case AArch64::BLR:
+  case AArch64::TCRETURNdi:
+  case AArch64::TCRETURNri:
+  case AArch64::TLSDESC_CALLSEQ:
+    return true;
+  }
+}
+
 #define GET_INSTRINFO_HELPERS
 #include "AArch64GenInstrInfo.inc"

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

unsigned getFramePred(const MachineInstr &MI) const {
     // 2 - predicate code (like ARMCC::AL)
     // - added by predOps:
     // 3 - predicate reg
     return MI.getOperand(3).getReg();
   }
 
   Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
                                       Register Reg) const override;
+
+  /// Return true if the \c MI is a candidate for the call site info
+  /// (the 'callSites:') production.
+  bool isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                   bool IgnoreBundle = false) const override;
 };
 
 /// Get the operands corresponding to the given \p Pred value. By default, the
 /// predicate register is assumed to be 0 (no register), but you can pass in a
 /// \p PredReg if that is not the case.
 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
                                                     unsigned PredReg = 0) {
   return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Optional<RegImmPair> ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
   if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
       !MI.getOperand(2).isImm())
     return None;
 
   Offset = MI.getOperand(2).getImm() * Sign;
   return RegImmPair{MI.getOperand(1).getReg(), Offset};
 }
 
+bool ARMBaseInstrInfo::isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                                   bool IgnoreBundle) const {
+  bool IsCall = IgnoreBundle ? MI.isCall(MachineInstr::IgnoreBundle) :
+                               MI.isCall();
+  if (!IsCall)
+    return false;
+
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case ARM::BL:
+  case ARM::BLX:
+  case ARM::BL_pred:
+  case ARM::TCRETURNdi:
+  case ARM::TCRETURNri:
+  case ARM::tTAILJMPd:
+  case ARM::tTAILJMPdND:
+    return true;
+  }
+}
+
 bool llvm::registerDefinedBetween(unsigned Reg,
                                   MachineBasicBlock::iterator From,
                                   MachineBasicBlock::iterator To,
                                   const TargetRegisterInfo *TRI) {
   for (auto I = From; I != To; ++I)
     if (I->modifiesRegister(Reg, TRI))
       return true;
   return false;

llvm/lib/Target/X86/X86InstrInfo.h

#include "X86GenInstrInfo.inc"
 
   static bool hasLockPrefix(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & X86II::LOCK;
   }
 
   Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
                                                  Register Reg) const override;
 
+  /// Return true if the \c MI is a candidate for the call site info
+  /// (the 'callSites:') production.
+  bool isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                   bool IgnoreBundle = false) const override;
+
 protected:
   /// Commutes the operands in the given instruction by changing the operands
   /// order and/or changing the instruction's opcode and/or the immediate value
   /// operand.
   ///
   /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
   /// to be commuted.
   ///

llvm/lib/Target/X86/X86InstrInfo.cpp

 
 Optional<DestSourcePair>
 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
   if (MI.isMoveReg())
     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
   return None;
 }
 
+bool X86InstrInfo::isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                               bool IgnoreBundle) const {
+  bool IsCall = IgnoreBundle ? MI.isCall(MachineInstr::IgnoreBundle) :
+                               MI.isCall();
+  if (!IsCall)
+    return false;
+
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case X86::CALL64pcrel32:
+  case X86::CALLpcrel32:
+  case X86::CALL64m:
+  case X86::CALL32m:
+  case X86::CALL64r:
+  case X86::CALL32r:
+  case X86::TAILJMPd64:
+  case X86::TAILJMPd:
+  case X86::TAILJMPd64_CC:
+  case X86::TAILJMPd_CC:
+  case X86::TCRETURNdi64:
+  case X86::TCRETURNri64:
+  case X86::TCRETURNmi64:
+  case X86::TCRETURNdi:
+  case X86::TCRETURNri:
+  case X86::TCRETURNmi:
+    return true;
+  }
+}
+
 static unsigned getLoadStoreRegOpcode(unsigned Reg,
                                       const TargetRegisterClass *RC,
                                       bool isStackAligned,
                                       const X86Subtarget &STI,
                                       bool load) {
   bool HasAVX = STI.hasAVX();
   bool HasAVX512 = STI.hasAVX512();
   bool HasVLX = STI.hasVLX();