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Differential D73748

[AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg
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Authored by paquette on Jan 30 2020, 3:09 PM.

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aemerson
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rGb9bf9305d108: [AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg
Summary

When you encounter a G_TRUNC, you are moving from a larger type to a smaller type.

Asking for the i-th bit on a larger value is the same as asking for the i-th bit on a smaller value.




So, we should always be able to walk through G_TRUNC when computing the bit for a TB(N)Z.
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paquette created this revision.Jan 30 2020, 3:09 PM
Herald added a project: Restricted Project.  ·  View Herald TranscriptJan 30 2020, 3:09 PM
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, rovka.  ·  View Herald Transcript
aemerson accepted this revision.Jan 31 2020, 10:19 AM
LGTM.
This revision is now accepted and ready to land.Jan 31 2020, 10:19 AM
Closed by commit rGb9bf9305d108: [AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg (authored by paquette).  ·  Explain WhyJan 31 2020, 11:12 AM
This revision was automatically updated to reflect the committed changes.
Revision Contents
PathSize
llvm/
lib/
Target/
AArch64/
6 lines
test/
CodeGen/
AArch64/
GlobalISel/
35 lines
Diff 241598
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
Show First 20 Lines • Show All 992 Lines • ▼ Show 20 Lines
/// Return a register which can be used as a bit to test in a TB(N)Z.
/// Return a register which can be used as a bit to test in a TB(N)Z.

static Register getTestBitReg(Register Reg, MachineRegisterInfo &MRI) {
static Register getTestBitReg(Register Reg, MachineRegisterInfo &MRI) {

  assert(Reg.isValid() && "Expected valid register!");
  assert(Reg.isValid() && "Expected valid register!");

  while (MachineInstr *MI = getDefIgnoringCopies(Reg, MRI)) {
  while (MachineInstr *MI = getDefIgnoringCopies(Reg, MRI)) {

    unsigned Opc = MI->getOpcode();
    unsigned Opc = MI->getOpcode();

    Register NextReg;
    Register NextReg;




    // (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
    // (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.

    if (Opc == TargetOpcode::G_ANYEXT || Opc == TargetOpcode::G_ZEXT)
    //

    // (tbz (trunc x), b) -> (tbz x, b) is always safe, because the bit number

    // on the truncated x is the same as the bit number on x.

    if (Opc == TargetOpcode::G_ANYEXT || Opc == TargetOpcode::G_ZEXT ||

        Opc == TargetOpcode::G_TRUNC)

      NextReg = MI->getOperand(1).getReg();
      NextReg = MI->getOperand(1).getReg();




    // Did we find something worth folding?
    // Did we find something worth folding?

    if (!NextReg.isValid() || !MRI.hasOneUse(NextReg))
    if (!NextReg.isValid() || !MRI.hasOneUse(NextReg))

      break;
      break;




    // NextReg is worth folding. Keep looking.
    // NextReg is worth folding. Keep looking.

    Reg = NextReg;
    Reg = NextReg;

▲ Show 20 Lines • Show All 4,138 Lines • Show Last 20 Lines
llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir
  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

...

---

name:            fold_trunc

alignment:       4

legalized:       true

regBankSelected: true

tracksRegLiveness: true

body:             |

  ; CHECK-LABEL: name: fold_trunc

  ; CHECK: bb.0:

  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)

  ; CHECK:   liveins: $x0

  ; CHECK:   %copy:gpr64all = COPY $x0

  ; CHECK:   [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32

  ; CHECK:   [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]

  ; CHECK:   TBNZW [[COPY1]], 3, %bb.1

  ; CHECK:   B %bb.0

  ; CHECK: bb.1:

  ; CHECK:   RET_ReallyLR

  bb.0:

    successors: %bb.0, %bb.1

    liveins: $x0

    %copy:gpr(s64) = COPY $x0

    %bit:gpr(s32) = G_CONSTANT i32 8

    %zero:gpr(s32) = G_CONSTANT i32 0

    %fold_me:gpr(s32) = G_TRUNC %copy(s64)

    %and:gpr(s32) = G_AND %fold_me, %bit

    %cmp:gpr(s32) = G_ICMP intpred(ne), %and(s32), %zero

    %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)

    G_BRCOND %cmp_trunc(s1), %bb.1

    G_BR %bb.0

  bb.1:

    RET_ReallyLR