This NFC(ish*) patch defers the decision on which DW_OP_pieces to emit when composing a superregister out of subregisters to addMachineRegExpression. This is in preparation of https://reviews.llvm.org/D73283.
This patch also removes the now redundant MaxSize parameter.
*) One could construct a target in which a superregister could not be fully covered by subregsiters, in which case this code gives up instead of emitting an undefined DW_OP_piece.
Now when we got the offset included in the Register struct we could assert that subregister pieces are ordered from least significant to most significant in the DwardRegs vector:
I think that as a follow up we should consider if the iteration order should be reversed for big endian targets (at least we need to do it for our out-of-tree target, since in DWARF the pieces should be in increasing memory order). That would ofcourse make such an assertion to fail, as well as complicating the SubRegBits calculcation a little bit.