[AArch64][GlobalISel] Don't bail out of the select(cmp(a, b)) -> csel optimization with multiple users.

[aemerson]

Summary

It can still be beneficial to do the optimization if the result of the compare is used by *another* select.

[paquette]

LGTM

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
   //
   // Rather than emitting both of the rather long sequences in the standard
   // G_FCMP/G_SELECT select methods.
 
   // First, check if the condition is defined by a compare.
   MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg());
   while (CondDef) {
     // We can only fold if all of the defs have one use.
-    if (!MRI.hasOneUse(CondDef->getOperand(0).getReg()))
+    Register CondDefReg = CondDef->getOperand(0).getReg();
+    if (!MRI.hasOneUse(CondDefReg)) {
+      // Unless it's another select.
+      for (auto UI = MRI.use_instr_begin(CondDefReg), UE = MRI.use_instr_end();
+           UI != UE; ++UI) {
+        if (CondDef == &*UI)
+          continue;
+        if (UI->getOpcode() != TargetOpcode::G_SELECT)
           return false;
+      }
+    }
 
     // We can skip over G_TRUNC since the condition is 1-bit.
     // Truncating/extending can have no impact on the value.
     unsigned Opc = CondDef->getOpcode();
     if (Opc != TargetOpcode::COPY && Opc != TargetOpcode::G_TRUNC)
       break;
 
     // Can't see past copies from physregs.

llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 #
 # Verify the following:
 #
 # - We can fold compares into selects.
-# - This only happens when the result of the compare is only used by the select.
+# - This only happens when the result of the compare is only used by selects.
 #
 # Also verify that, for now:
 #
 # - We only support condition flags that require a single instruction.
 #
 
 ...
 ---
bb.0:
     %6:fpr(s1) = COPY %3(s1)
     %4:fpr(s32) = G_SELECT %6(s1), %2, %1
     $w1 = COPY %5(s32)
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...
 ---
+name:            fcmp_more_than_one_select
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $s1, $w1
+
+    ; CHECK-LABEL: name: fcmp_more_than_one_select
+    ; CHECK: liveins: $s0, $s1, $w1
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
+    ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+    ; CHECK: [[FCSELSrrr1:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
+    ; CHECK: $s0 = COPY [[FCSELSrrr]]
+    ; CHECK: $s1 = COPY [[FCSELSrrr1]]
+    ; CHECK: RET_ReallyLR implicit $s0
+    %0:fpr(s32) = COPY $s0
+    %1:fpr(s32) = COPY $s1
+    %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
+    %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
+    %3:gpr(s1) = G_TRUNC %5(s32)
+    %6:fpr(s1) = COPY %3(s1)
+    %4:fpr(s32) = G_SELECT %6(s1), %2, %1
+    %7:fpr(s32) = G_SELECT %6(s1), %1, %2
+    $s0 = COPY %4(s32)
+    $s1 = COPY %7(s32)
+    RET_ReallyLR implicit $s0
+
+...
+---
 name:            using_icmp
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $s0, $w0