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Differential D73483

[AMDGPU] fixed divergence driven shift operations selection
ClosedPublic

Authored by alex-t on Jan 27 2020, 7:55 AM.

Details

Reviewers
arsenm
rampitec
Commits
rG5df1ac7846c8: [AMDGPU] fixed divergence driven shift operations selection
Summary

change https://reviews.llvm.org/D64725 removes “isDivergent” predicates from the scalar shifts.
As a result we easy can select S_LSHL_B32 for divergent arguments.

Diff Detail

Event Timeline

alex-t created this revision.Jan 27 2020, 7:55 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 27 2020, 7:55 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald Transcript
rampitec added a comment.Jan 27 2020, 10:25 AM

Is there a test for scalar selection?

llvm/lib/Target/AMDGPU/VOP2Instructions.td
548

Any tests for GFX10 on this?

llvm/lib/Target/AMDGPU/VOP3Instructions.td
388

Any tests for GFX10 on this?

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
2

Ugh... Fiji is GFX8. Instead of dropping test for tahiti just fix the check-prefix for fiji.

alex-t updated this revision to Diff 241120.Jan 29 2020, 5:17 AM
alex-t marked 2 inline comments as done.

divergence driven selection test for shift operations added
tests updated

llvm/lib/Target/AMDGPU/VOP2Instructions.td
548

Will be an assertion "Opcode does not exist on target"

llvm/lib/Target/AMDGPU/VOP3Instructions.td
388

Will be an assertion "Opcode does not exist on target"

rampitec added inline comments.Jan 29 2020, 10:35 AM
llvm/lib/Target/AMDGPU/VOP2Instructions.td
548

But we need a gfx10 test to check proper selection of IR shifts. I do not see these tests.

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
982

It does not belong to this change. Please generate a proper diff.

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
2

Please return the dropped tahiti run line.

llvm/test/CodeGen/AMDGPU/shift-select.ll
2

Please add another line for gfx1010.

57

You also need tests for i64.

69

Newline.

arsenm mentioned this in D73659: [GlobalISel] Add new combine to convert G_MUL to G_SHL..Jan 29 2020, 12:58 PM
alex-t updated this revision to Diff 241451.Jan 30 2020, 7:29 AM

Diff corrected. GFX10 test added.

arsenm added a comment.Jan 30 2020, 7:42 AM

I expected this to fix the test XFAIL'd in c12f046eb96f8462b3fd3889344ba344de5ace1f, but it seems to to have?

rampitec added inline comments.Jan 30 2020, 9:57 AM
llvm/test/CodeGen/AMDGPU/shift-select.ll
57

Would be LGTM if there were i64 tests.

alex-t added a comment.Jan 31 2020, 3:09 AM
In D73483#1849587, @arsenm wrote:

I expected this to fix the test XFAIL'd in c12f046eb96f8462b3fd3889344ba344de5ace1f, but it seems to to have?

I haven't seen any tests XFAIL'd by this c12f046eb96f8462b3fd3889344ba344de5ace1f commit.
What did you mean? Could you explain please?

alex-t updated this revision to Diff 241692.Jan 31 2020, 4:42 AM

i64 tests added

arsenm added a comment.Jan 31 2020, 6:03 AM
In D73483#1851394, @alex-t wrote:
In D73483#1849587, @arsenm wrote:

I expected this to fix the test XFAIL'd in c12f046eb96f8462b3fd3889344ba344de5ace1f, but it seems to to have?

I haven't seen any tests XFAIL'd by this c12f046eb96f8462b3fd3889344ba344de5ace1f commit.
What did you mean? Could you explain please?

test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll is now XFAILed

alex-t updated this revision to Diff 241723.Jan 31 2020, 6:58 AM

llvm.amdgcn.update.dpp test updated

arsenm accepted this revision.Jan 31 2020, 7:10 AM
This revision is now accepted and ready to land.Jan 31 2020, 7:10 AM
Closed by commit rG5df1ac7846c8: [AMDGPU] fixed divergence driven shift operations selection (authored by alex-t). · Explain WhyJan 31 2020, 9:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 241120

llvm/lib/Target/AMDGPU/SOPInstructions.td

Show First 20 Lines • Show All 407 Lines • ▼ Show 20 Linesclass UniformUnaryFrag<SDPatternOperator Op> : PatFrag <
(Op $src0), (Op $src0),
[{ return !N->isDivergent(); }] [{ return !N->isDivergent(); }]
>; >;
class UniformBinFrag<SDPatternOperator Op> : PatFrag < class UniformBinFrag<SDPatternOperator Op> : PatFrag <
(ops node:$src0, node:$src1), (ops node:$src0, node:$src1),
(Op $src0, $src1), (Op $src0, $src1),
[{ return !N->isDivergent(); }] [{ return !N->isDivergent(); }]
>; > {
let GISelPredicateCode = [{return true;}];
}
let Defs = [SCC] in { // Carry out goes to SCC let Defs = [SCC] in { // Carry out goes to SCC
let isCommutable = 1 in { let isCommutable = 1 in {
def S_ADD_U32 : SOP2_32 <"s_add_u32">; def S_ADD_U32 : SOP2_32 <"s_add_u32">;
def S_ADD_I32 : SOP2_32 <"s_add_i32", def S_ADD_I32 : SOP2_32 <"s_add_i32",
[(set i32:$sdst, (UniformBinFrag<add> SSrc_b32:$src0, SSrc_b32:$src1))] [(set i32:$sdst, (UniformBinFrag<add> SSrc_b32:$src0, SSrc_b32:$src1))]
>; >;
} // End isCommutable = 1 } // End isCommutable = 1
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
} // End Defs = [SCC] } // End Defs = [SCC]
// Use added complexity so these patterns are preferred to the VALU patterns. // Use added complexity so these patterns are preferred to the VALU patterns.
let AddedComplexity = 1 in { let AddedComplexity = 1 in {
let Defs = [SCC] in { let Defs = [SCC] in {
// TODO: b64 versions require VOP3 change since v_lshlrev_b64 is VOP3 // TODO: b64 versions require VOP3 change since v_lshlrev_b64 is VOP3
def S_LSHL_B32 : SOP2_32 <"s_lshl_b32", def S_LSHL_B32 : SOP2_32 <"s_lshl_b32",
[(set SReg_32:$sdst, (shl (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))] [(set SReg_32:$sdst, (UniformBinFrag<shl> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>; >;
def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64", def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64",
[(set SReg_64:$sdst, (shl (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))] [(set SReg_64:$sdst, (UniformBinFrag<shl> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
>; >;
def S_LSHR_B32 : SOP2_32 <"s_lshr_b32", def S_LSHR_B32 : SOP2_32 <"s_lshr_b32",
[(set SReg_32:$sdst, (srl (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))] [(set SReg_32:$sdst, (UniformBinFrag<srl> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>; >;
def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64", def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64",
[(set SReg_64:$sdst, (srl (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))] [(set SReg_64:$sdst, (UniformBinFrag<srl> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
>; >;
def S_ASHR_I32 : SOP2_32 <"s_ashr_i32", def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
[(set SReg_32:$sdst, (sra (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))] [(set SReg_32:$sdst, (UniformBinFrag<sra> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>; >;
def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64", def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",
[(set SReg_64:$sdst, (sra (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))] [(set SReg_64:$sdst, (UniformBinFrag<sra> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
>; >;
} // End Defs = [SCC] } // End Defs = [SCC]
def S_BFM_B32 : SOP2_32 <"s_bfm_b32", def S_BFM_B32 : SOP2_32 <"s_bfm_b32",
[(set i32:$sdst, (UniformBinFrag<AMDGPUbfm> i32:$src0, i32:$src1))]>; [(set i32:$sdst, (UniformBinFrag<AMDGPUbfm> i32:$src0, i32:$src1))]>;
def S_BFM_B64 : SOP2_64_32_32 <"s_bfm_b64">; def S_BFM_B64 : SOP2_64_32_32 <"s_bfm_b64">;
// TODO: S_MUL_I32 require V_MUL_LO_I32 from VOP3 change // TODO: S_MUL_I32 require V_MUL_LO_I32 from VOP3 change
▲ Show 20 Lines • Show All 1,128 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/VOP2Instructions.td

Show First 20 Lines • Show All 535 Lines • ▼ Show 20 Lines
defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>; defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
let SubtargetPredicate = isGFX6GFX7 in { let SubtargetPredicate = isGFX6GFX7 in {
defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>; defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>; defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
} // End SubtargetPredicate = isGFX6GFX7 } // End SubtargetPredicate = isGFX6GFX7
let SubtargetPredicate = isGFX6GFX7GFX10 in {
let isCommutable = 1 in { let isCommutable = 1 in {
let SubtargetPredicate = isGFX6GFX7GFX10 in {
defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>; defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>;
defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_I32_I32_I32, srl>;
defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_I32_I32_I32, sra>;
defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_I32_I32_I32, shl>;
} // End isCommutable = 1
} // End SubtargetPredicate = isGFX6GFX7GFX10 } // End SubtargetPredicate = isGFX6GFX7GFX10
let SubtargetPredicate = isGFX6GFX7 in {
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Any tests for GFX10 on this?

rampitec: Any tests for GFX10 on this?
alex-tAuthorUnsubmitted
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Will be an assertion "Opcode does not exist on target"

alex-t: Will be an assertion "Opcode does not exist on target"
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But we need a gfx10 test to check proper selection of IR shifts. I do not see these tests.

rampitec: But we need a gfx10 test to check proper selection of IR shifts. I do not see these tests.
defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
} // End SubtargetPredicate = isGFX6GFX7
} // End isCommutable = 1
class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
GCNPat< GCNPat<
(getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1), (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
!if(!cast<Commutable_REV>(Inst).IsOrig, !if(!cast<Commutable_REV>(Inst).IsOrig,
(Inst $src0, $src1), (Inst $src0, $src1),
(Inst $src1, $src0) (Inst $src1, $src0)
) )
▲ Show 20 Lines • Show All 1,036 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/VOP3Instructions.td

Show First 20 Lines • Show All 379 Lines • ▼ Show 20 Lines
def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
} // End Constraints = "@earlyclobber $vdst" } // End Constraints = "@earlyclobber $vdst"
def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> { def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
let SchedRW = [WriteDouble]; let SchedRW = [WriteDouble];
} }
let SchedRW = [Write64Bit] in { let SchedRW = [Write64Bit] in {
let SubtargetPredicate = isGFX6GFX7GFX10 in { let SubtargetPredicate = isGFX6GFX7 in {
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Any tests for GFX10 on this?

rampitec: Any tests for GFX10 on this?
alex-tAuthorUnsubmitted
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Will be an assertion "Opcode does not exist on target"

alex-t: Will be an assertion "Opcode does not exist on target"
def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>; def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>;
def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>; def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>;
def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>; def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>;
} // End SubtargetPredicate = isGFX6GFX7
let SubtargetPredicate = isGFX6GFX7GFX10 in {
def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
} // End SubtargetPredicate = isGFX6GFX7GFX10 } // End SubtargetPredicate = isGFX6GFX7GFX10
let SubtargetPredicate = isGFX8Plus in { let SubtargetPredicate = isGFX8Plus in {
def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>; def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>;
def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>; def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>;
def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>; def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>;
} // End SubtargetPredicate = isGFX8Plus } // End SubtargetPredicate = isGFX8Plus
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llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

Show First 20 Lines • Show All 973 Lines • ▼ Show 20 Linesentry:
ret double %ext ret double %ext
} }
define amdgpu_ps double @dyn_extract_v8f64_s_s_offsetm1(<8 x double> inreg %vec, i32 inreg %sel) { define amdgpu_ps double @dyn_extract_v8f64_s_s_offsetm1(<8 x double> inreg %vec, i32 inreg %sel) {
; GPRIDX-LABEL: dyn_extract_v8f64_s_s_offsetm1: ; GPRIDX-LABEL: dyn_extract_v8f64_s_s_offsetm1:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_mov_b32 s0, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_mov_b32 s1, s3
; GPRIDX-NEXT: s_add_u32 m0, s18, -1 ; GPRIDX-NEXT: s_add_i32 m0, s18, -1
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It does not belong to this change. Please generate a proper diff.

rampitec: It does not belong to this change. Please generate a proper diff.
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_mov_b32 s2, s4
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_mov_b32 s4, s6
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_mov_b32 s6, s8
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10 ; GPRIDX-NEXT: s_mov_b32 s8, s10
; GPRIDX-NEXT: s_mov_b32 s9, s11 ; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: s_mov_b32 s10, s12 ; GPRIDX-NEXT: s_mov_b32 s10, s12
; GPRIDX-NEXT: s_mov_b32 s11, s13 ; GPRIDX-NEXT: s_mov_b32 s11, s13
; GPRIDX-NEXT: s_mov_b32 s12, s14 ; GPRIDX-NEXT: s_mov_b32 s12, s14
; GPRIDX-NEXT: s_mov_b32 s13, s15 ; GPRIDX-NEXT: s_mov_b32 s13, s15
; GPRIDX-NEXT: s_mov_b32 s14, s16 ; GPRIDX-NEXT: s_mov_b32 s14, s16
; GPRIDX-NEXT: s_mov_b32 s15, s17 ; GPRIDX-NEXT: s_mov_b32 s15, s17
; GPRIDX-NEXT: s_movrels_b64 s[0:1], s[0:1] ; GPRIDX-NEXT: s_movrels_b64 s[0:1], s[0:1]
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_extract_v8f64_s_s_offsetm1: ; MOVREL-LABEL: dyn_extract_v8f64_s_s_offsetm1:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_add_u32 m0, s18, -1 ; MOVREL-NEXT: s_add_i32 m0, s18, -1
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_mov_b32 s8, s10 ; MOVREL-NEXT: s_mov_b32 s8, s10
; MOVREL-NEXT: s_mov_b32 s9, s11 ; MOVREL-NEXT: s_mov_b32 s9, s11
Show All 13 Lines
define double @dyn_extract_v8f64_v_v_offset3(<8 x double> %vec, i32 %sel) { define double @dyn_extract_v8f64_v_v_offset3(<8 x double> %vec, i32 %sel) {
; GPRIDX-LABEL: dyn_extract_v8f64_v_v_offset3: ; GPRIDX-LABEL: dyn_extract_v8f64_v_v_offset3:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GPRIDX-NEXT: s_mov_b64 s[4:5], exec ; GPRIDX-NEXT: s_mov_b64 s[4:5], exec
; GPRIDX-NEXT: BB22_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: BB22_1: ; =>This Inner Loop Header: Depth=1
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v16 ; GPRIDX-NEXT: v_readfirstlane_b32 s6, v16
; GPRIDX-NEXT: s_add_u32 s7, s6, 3 ; GPRIDX-NEXT: s_add_i32 s7, s6, 3
; GPRIDX-NEXT: s_lshl_b32 s7, s7, 1 ; GPRIDX-NEXT: s_lshl_b32 s7, s7, 1
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s6, v16 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s6, v16
; GPRIDX-NEXT: s_set_gpr_idx_on s7, gpr_idx(SRC0) ; GPRIDX-NEXT: s_set_gpr_idx_on s7, gpr_idx(SRC0)
; GPRIDX-NEXT: v_mov_b32_e32 v17, v0 ; GPRIDX-NEXT: v_mov_b32_e32 v17, v0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_set_gpr_idx_on s7, gpr_idx(SRC0) ; GPRIDX-NEXT: s_set_gpr_idx_on s7, gpr_idx(SRC0)
; GPRIDX-NEXT: v_mov_b32_e32 v18, v1 ; GPRIDX-NEXT: v_mov_b32_e32 v18, v1
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc ; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc ; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB22_1 ; GPRIDX-NEXT: s_cbranch_execnz BB22_1
; GPRIDX-NEXT: ; %bb.2: ; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[4:5] ; GPRIDX-NEXT: s_mov_b64 exec, s[4:5]
; GPRIDX-NEXT: v_mov_b32_e32 v0, v17 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v17
; GPRIDX-NEXT: v_mov_b32_e32 v1, v18 ; GPRIDX-NEXT: v_mov_b32_e32 v1, v18
; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; GPRIDX-NEXT: s_setpc_b64 s[30:31]
; ;
; MOVREL-LABEL: dyn_extract_v8f64_v_v_offset3: ; MOVREL-LABEL: dyn_extract_v8f64_v_v_offset3:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MOVREL-NEXT: s_mov_b64 s[4:5], exec ; MOVREL-NEXT: s_mov_b64 s[4:5], exec
; MOVREL-NEXT: BB22_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB22_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s6, v16 ; MOVREL-NEXT: v_readfirstlane_b32 s6, v16
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, s6, v16 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, s6, v16
; MOVREL-NEXT: s_add_u32 s6, s6, 3 ; MOVREL-NEXT: s_add_i32 s6, s6, 3
; MOVREL-NEXT: s_lshl_b32 m0, s6, 1 ; MOVREL-NEXT: s_lshl_b32 m0, s6, 1
; MOVREL-NEXT: v_movrels_b32_e32 v17, v0 ; MOVREL-NEXT: v_movrels_b32_e32 v17, v0
; MOVREL-NEXT: v_movrels_b32_e32 v18, v1 ; MOVREL-NEXT: v_movrels_b32_e32 v18, v1
; MOVREL-NEXT: s_and_saveexec_b64 vcc, vcc ; MOVREL-NEXT: s_and_saveexec_b64 vcc, vcc
; MOVREL-NEXT: s_xor_b64 exec, exec, vcc ; MOVREL-NEXT: s_xor_b64 exec, exec, vcc
; MOVREL-NEXT: s_cbranch_execnz BB22_1 ; MOVREL-NEXT: s_cbranch_execnz BB22_1
; MOVREL-NEXT: ; %bb.2: ; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b64 exec, s[4:5] ; MOVREL-NEXT: s_mov_b64 exec, s[4:5]
▲ Show 20 Lines • Show All 190 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

Show First 20 Lines • Show All 2,087 Lines • ▼ Show 20 Lines
} }
define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, double %val, i32 %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_v_add_1: ; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: s_mov_b64 s[0:1], exec
; GPRIDX-NEXT: BB32_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: BB32_1: ; =>This Inner Loop Header: Depth=1
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v18 ; GPRIDX-NEXT: v_readfirstlane_b32 s2, v18
; GPRIDX-NEXT: s_add_u32 s3, s2, 1 ; GPRIDX-NEXT: s_add_i32 s3, s2, 1
; GPRIDX-NEXT: s_lshl_b32 s3, s3, 1 ; GPRIDX-NEXT: s_lshl_b32 s3, s3, 1
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v18 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v18
; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v34, v15 ; GPRIDX-NEXT: v_mov_b32_e32 v34, v15
; GPRIDX-NEXT: v_mov_b32_e32 v33, v14 ; GPRIDX-NEXT: v_mov_b32_e32 v33, v14
; GPRIDX-NEXT: v_mov_b32_e32 v32, v13 ; GPRIDX-NEXT: v_mov_b32_e32 v32, v13
; GPRIDX-NEXT: v_mov_b32_e32 v31, v12 ; GPRIDX-NEXT: v_mov_b32_e32 v31, v12
; GPRIDX-NEXT: v_mov_b32_e32 v30, v11 ; GPRIDX-NEXT: v_mov_b32_e32 v30, v11
Show All 29 Lines
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB32_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: BB32_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v18 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v18
; MOVREL-NEXT: v_mov_b32_e32 v34, v15 ; MOVREL-NEXT: v_mov_b32_e32 v34, v15
; MOVREL-NEXT: v_mov_b32_e32 v19, v0 ; MOVREL-NEXT: v_mov_b32_e32 v19, v0
; MOVREL-NEXT: v_mov_b32_e32 v33, v14 ; MOVREL-NEXT: v_mov_b32_e32 v33, v14
; MOVREL-NEXT: v_mov_b32_e32 v32, v13 ; MOVREL-NEXT: v_mov_b32_e32 v32, v13
; MOVREL-NEXT: s_add_u32 s2, s1, 1 ; MOVREL-NEXT: s_add_i32 s2, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18
; MOVREL-NEXT: v_mov_b32_e32 v31, v12 ; MOVREL-NEXT: v_mov_b32_e32 v31, v12
; MOVREL-NEXT: v_mov_b32_e32 v30, v11 ; MOVREL-NEXT: v_mov_b32_e32 v30, v11
; MOVREL-NEXT: v_mov_b32_e32 v29, v10 ; MOVREL-NEXT: v_mov_b32_e32 v29, v10
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v28, v9 ; MOVREL-NEXT: v_mov_b32_e32 v28, v9
; MOVREL-NEXT: v_mov_b32_e32 v27, v8 ; MOVREL-NEXT: v_mov_b32_e32 v27, v8
; MOVREL-NEXT: v_mov_b32_e32 v26, v7 ; MOVREL-NEXT: v_mov_b32_e32 v26, v7
Show All 31 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
rampitecUnsubmitted
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Ugh... Fiji is GFX8. Instead of dropping test for tahiti just fix the check-prefix for fiji.

rampitec: Ugh... Fiji is GFX8. Instead of dropping test for tahiti just fix the check-prefix for fiji.
rampitecUnsubmitted
Not Done
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Please return the dropped tahiti run line.

rampitec: Please return the dropped tahiti run line.
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
--- ---
name: add_s32 name: add_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX6-LABEL: name: add_s32 ; GFX6-LABEL: name: add_s32
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec ; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_U32_]], %7, 0, implicit $exec ; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_I32_]], %7, 0, implicit $exec
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec ; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit %7, implicit %8, implicit %9 ; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit %7, implicit %8, implicit %9
; GFX8-LABEL: name: add_s32
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX8: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
; GFX8: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_I32_]], %7, 0, implicit $exec
; GFX8: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit %7, implicit %8, implicit %9
; GFX9-LABEL: name: add_s32 ; GFX9-LABEL: name: add_s32
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_U32_]], [[V_ADD_U32_e64_]], 0, implicit $exec ; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec ; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]] ; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:vgpr(s32) = COPY $vgpr0 %2:vgpr(s32) = COPY $vgpr0
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%4:sgpr(s32) = G_CONSTANT i32 1 %4:sgpr(s32) = G_CONSTANT i32 1
%5:sgpr(s32) = G_CONSTANT i32 4096 %5:sgpr(s32) = G_CONSTANT i32 4096
; add ss ; add ss
Show All 22 Linesbody: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_s ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
; GFX6: liveins: $sgpr0 ; GFX6: liveins: $sgpr0
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc ; GFX6: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
; GFX6: S_ENDPGM 0, implicit [[S_SUB_I32_]] ; GFX6: S_ENDPGM 0, implicit [[S_SUB_I32_]]
; GFX8-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
; GFX8: liveins: $sgpr0
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX8: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
; GFX8: S_ENDPGM 0, implicit [[S_SUB_I32_]]
; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
; GFX9: liveins: $sgpr0 ; GFX9: liveins: $sgpr0
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc ; GFX9: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
; GFX9: S_ENDPGM 0, implicit [[S_SUB_I32_]] ; GFX9: S_ENDPGM 0, implicit [[S_SUB_I32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 -64 %1:sgpr(s32) = G_CONSTANT i32 -64
%2:sgpr(s32) = G_ADD %0, %1 %2:sgpr(s32) = G_ADD %0, %1
Show All 12 Lines bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_v ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
; GFX6: liveins: $vgpr0 ; GFX6: liveins: $vgpr0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967232, implicit $exec ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967232, implicit $exec
; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit %2 ; GFX6: S_ENDPGM 0, implicit %2
; GFX8-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967232, implicit $exec
; GFX8: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_v ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
; GFX9: liveins: $vgpr0 ; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY]], 64, 0, implicit $exec ; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY]], 64, 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_]] ; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 -64 %1:vgpr(s32) = G_CONSTANT i32 -64
%2:vgpr(s32) = G_ADD %0, %1 %2:vgpr(s32) = G_ADD %0, %1
Show All 12 Lines bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_s ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
; GFX6: liveins: $sgpr0 ; GFX6: liveins: $sgpr0
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]] ; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]]
; GFX8-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
; GFX8: liveins: $sgpr0
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GFX8: S_ENDPGM 0, implicit [[S_ADD_I32_]]
; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_s ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
; GFX9: liveins: $sgpr0 ; GFX9: liveins: $sgpr0
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]] ; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 16 %1:sgpr(s32) = G_CONSTANT i32 16
%2:sgpr(s32) = G_ADD %0, %1 %2:sgpr(s32) = G_ADD %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: add_neg_inline_const_16_to_sub_s32_v name: add_neg_inline_const_16_to_sub_s32_v
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_v ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
; GFX6: liveins: $vgpr0 ; GFX6: liveins: $vgpr0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit %2 ; GFX6: S_ENDPGM 0, implicit %2
; GFX8-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
; GFX8: liveins: $vgpr0
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
; GFX8: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_v ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
; GFX9: liveins: $vgpr0 ; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]] ; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 16 %1:vgpr(s32) = G_CONSTANT i32 16
%2:vgpr(s32) = G_ADD %0, %1 %2:vgpr(s32) = G_ADD %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Lines bb.0:
; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]] ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
; GFX10-LABEL: name: ashr_s64_sv ; GFX10-LABEL: name: ashr_s64_sv
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ASHR_I64_]] ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s64) = G_ASHR %0, %1 %2:vgpr(s64) = G_ASHR %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ashr_s64_vs name: ashr_s64_vs
Show All 22 Lines bb.0:
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]] ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
; GFX10-LABEL: name: ashr_s64_vs ; GFX10-LABEL: name: ashr_s64_vs
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX10: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ASHR_I64_]] ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s64) = G_ASHR %0, %1 %2:vgpr(s64) = G_ASHR %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ashr_s64_vv name: ashr_s64_vv
Show All 22 Lines bb.0:
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]] ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
; GFX10-LABEL: name: ashr_s64_vv ; GFX10-LABEL: name: ashr_s64_vv
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ASHR_I64_]] ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = COPY $vgpr2 %1:vgpr(s32) = COPY $vgpr2
%2:vgpr(s64) = G_ASHR %0, %1 %2:vgpr(s64) = G_ASHR %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: add_ctpop_s32_s_ss_commute0 ; CHECK-LABEL: name: add_ctpop_s32_s_ss_commute0
; CHECK: liveins: $sgpr0, $sgpr1 ; CHECK: liveins: $sgpr0, $sgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; CHECK: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def $scc ; CHECK: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def $scc
; CHECK: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[S_BCNT1_I32_B32_]], [[COPY1]], implicit-def $scc ; CHECK: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BCNT1_I32_B32_]], [[COPY1]], implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_ADD_U32_]] ; CHECK: S_ENDPGM 0, implicit [[S_ADD_I32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_CTPOP %0 %2:sgpr(s32) = G_CTPOP %0
%3:sgpr(s32) = G_ADD %2, %1 %3:sgpr(s32) = G_ADD %2, %1
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL_GFX6 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MOVREL_GFX8 %s
# RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-vgpr-index-mode -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX %s # RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-vgpr-index-mode -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX_GFX8 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GPRIDX_GFX9 %s
--- ---
name: extract_vector_elt_s_s32_v2s32 name: extract_vector_elt_s_s32_v2s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $sgpr2 liveins: $sgpr0_sgpr1, $sgpr2
; MOVREL-LABEL: name: extract_vector_elt_s_s32_v2s32 ; MOVREL-LABEL: name: extract_vector_elt_s_s32_v2s32
; MOVREL: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; MOVREL: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL: $m0 = COPY [[COPY1]] ; MOVREL: $m0 = COPY [[COPY1]]
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v2s32 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v2s32
; GPRIDX: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v2s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v2s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v2s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v2s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1 %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
%1:sgpr(s32) = COPY $sgpr2 %1:sgpr(s32) = COPY $sgpr2
%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s32_v3s32 name: extract_vector_elt_s_s32_v3s32
Show All 11 Lines bb.0:
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v3s32 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v3s32
; GPRIDX: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v3s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v3s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v3s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v3s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2 %0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2
%1:sgpr(s32) = COPY $sgpr2 %1:sgpr(s32) = COPY $sgpr2
%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s32_v4s32 name: extract_vector_elt_s_s32_v4s32
Show All 11 Lines bb.0:
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v4s32 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v4s32
; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v4s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v4s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v4s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v4s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 %0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:sgpr(s32) = COPY $sgpr4 %1:sgpr(s32) = COPY $sgpr4
%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s32_v8s32 name: extract_vector_elt_s_s32_v8s32
Show All 11 Lines bb.0:
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v8s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v8s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s32_v16s32 name: extract_vector_elt_s_s32_v16s32
Show All 11 Lines bb.0:
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v16s32 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v16s32
; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v16s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v16s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v16s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v16s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 %0:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s32_v32s32 name: extract_vector_elt_s_s32_v32s32
Show All 11 Lines bb.0:
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v32s32 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v32s32
; GPRIDX: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v32s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v32s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v32s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v32s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<32 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 %0:sgpr(<32 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
%1:sgpr(s32) = COPY $sgpr40 %1:sgpr(s32) = COPY $sgpr40
%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s64_v2s64 name: extract_vector_elt_s_s64_v2s64
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; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v2s64 ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v2s64
; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; GPRIDX: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s64_v2s64
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s64_v2s64
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s64_v2s64
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s64_v2s64
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
%0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 %0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:sgpr(s32) = COPY $sgpr4 %1:sgpr(s32) = COPY $sgpr4
%2:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s64_v4s64 name: extract_vector_elt_s_s64_v4s64
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; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v4s64 ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v4s64
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s64_v4s64
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s64_v4s64
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s64_v4s64
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s64_v4s64
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
%0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 %0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s64_v8s64 name: extract_vector_elt_s_s64_v8s64
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; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64 ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64
; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s64_v8s64
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s64_v8s64
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s64_v8s64
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s64_v8s64
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
%0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s64_v16s64 name: extract_vector_elt_s_s64_v16s64
Show All 11 Lines bb.0:
; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v16s64 ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v16s64
; GPRIDX: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s64_v16s64
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s64_v16s64
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s64_v16s64
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s64_v16s64
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_1024 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
%0:sgpr(<16 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 %0:sgpr(<16 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
%1:sgpr(s32) = COPY $sgpr40 %1:sgpr(s32) = COPY $sgpr40
%2:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %1 %2:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_s_s32_v8s32_idx_offset_1 name: extract_vector_elt_s_s32_v8s32_idx_offset_1
Show All 11 Lines bb.0:
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub1, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub1, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_1 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_1
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub1, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub1, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_1
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_1
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_1
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_1
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 1 %2:sgpr(s32) = G_CONSTANT i32 1
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3 %4:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: extract_vector_elt_s_s32_v8s32_idx_offset_m1 name: extract_vector_elt_s_s32_v8s32_idx_offset_m1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8
; MOVREL-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1 ; MOVREL-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1
; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL: $m0 = COPY [[S_ADD_U32_]] ; MOVREL: $m0 = COPY [[S_ADD_U32_]]
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX: $m0 = COPY [[S_ADD_U32_]] ; GPRIDX: $m0 = COPY [[S_ADD_U32_]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL_GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX6: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX8: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX8: $m0 = COPY [[S_ADD_I32_]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX_GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX9: $m0 = COPY [[S_ADD_I32_]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 -1 %2:sgpr(s32) = G_CONSTANT i32 -1
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3 %4:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 13 Lines bb.0:
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub7, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub7, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_7 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_7
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub7, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub7, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_7
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub7, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_7
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub7, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_7
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub7, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_7
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub7, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 7 %2:sgpr(s32) = G_CONSTANT i32 7
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3 %4:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: extract_vector_elt_s_s32_v8s32_idx_offset_8 name: extract_vector_elt_s_s32_v8s32_idx_offset_8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8
; MOVREL-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8 ; MOVREL-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8
; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL: $m0 = COPY [[S_ADD_U32_]] ; MOVREL: $m0 = COPY [[S_ADD_U32_]]
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8 ; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX: $m0 = COPY [[S_ADD_U32_]] ; GPRIDX: $m0 = COPY [[S_ADD_U32_]]
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; MOVREL_GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX6: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX6: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; MOVREL_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX8: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; GPRIDX_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX8: $m0 = COPY [[S_ADD_I32_]]
; GPRIDX_GFX8: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; GPRIDX_GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX9: $m0 = COPY [[S_ADD_I32_]]
; GPRIDX_GFX9: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 8 %2:sgpr(s32) = G_CONSTANT i32 8
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3 %4:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 13 Lines bb.0:
; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub2_sub3, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub2_sub3, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_1 ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_1
; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub2_sub3, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub2_sub3, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_1
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub2_sub3, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_1
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub2_sub3, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_1
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub2_sub3, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_1
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub2_sub3, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
%0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 1 %2:sgpr(s32) = G_CONSTANT i32 1
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %3 %4:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 13 Lines bb.0:
; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub4_sub5, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub4_sub5, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_2 ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_2
; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: $m0 = COPY [[COPY1]] ; GPRIDX: $m0 = COPY [[COPY1]]
; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub4_sub5, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub4_sub5, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_2
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub4_sub5, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_2
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub4_sub5, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_2
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: $m0 = COPY [[COPY1]]
; GPRIDX_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub4_sub5, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_2
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: $m0 = COPY [[COPY1]]
; GPRIDX_GFX9: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub4_sub5, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
%0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 2 %2:sgpr(s32) = G_CONSTANT i32 2
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %3 %4:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: extract_vector_elt_s_s64_v8s64_idx_offset_m1 name: extract_vector_elt_s_s64_v8s64_idx_offset_m1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1 ; MOVREL-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1
; MOVREL: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; MOVREL: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL: $m0 = COPY [[S_ADD_U32_]] ; MOVREL: $m0 = COPY [[S_ADD_U32_]]
; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1 ; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1
; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX: $m0 = COPY [[S_ADD_U32_]] ; GPRIDX: $m0 = COPY [[S_ADD_U32_]]
; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]] ; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1
; MOVREL_GFX6: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL_GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX6: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX6: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1
; MOVREL_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX8: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX8: $m0 = COPY [[S_ADD_I32_]]
; GPRIDX_GFX8: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX_GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX9: $m0 = COPY [[S_ADD_I32_]]
; GPRIDX_GFX9: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
%0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 %0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 -1 %2:sgpr(s32) = G_CONSTANT i32 -1
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %3 %4:sgpr(s64) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 14 Lines bb.0:
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v2s32 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v2s32
; GPRIDX: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v2s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v2s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v2s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v2s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1 %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr2 %1:sgpr(s32) = COPY $sgpr2
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_v_s32_v3s32 name: extract_vector_elt_v_s32_v3s32
Show All 12 Lines bb.0:
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v3s32 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v3s32
; GPRIDX: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v3s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v3s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v3s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v3s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:vgpr(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:sgpr(s32) = COPY $sgpr2 %1:sgpr(s32) = COPY $sgpr2
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_v_s32_v4s32 name: extract_vector_elt_v_s32_v4s32
Show All 12 Lines bb.0:
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v4s32 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v4s32
; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v4s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v4s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v4s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v4s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:sgpr(s32) = COPY $sgpr4 %1:sgpr(s32) = COPY $sgpr4
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_v_s32_v8s32 name: extract_vector_elt_v_s32_v8s32
Show All 12 Lines bb.0:
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v8s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v8s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_v_s32_v16s32 name: extract_vector_elt_v_s32_v16s32
Show All 12 Lines bb.0:
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v16s32 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v16s32
; GPRIDX: [[COPY:%[0-9]+]]:vreg_512 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_512 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v16s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_512 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v16s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_512 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v16s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_512 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v16s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_512 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 %0:vgpr(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_v_s32_v32s32 name: extract_vector_elt_v_s32_v32s32
Show All 12 Lines bb.0:
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v32s32 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v32s32
; GPRIDX: [[COPY:%[0-9]+]]:vreg_1024 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_1024 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v32s32
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_1024 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v32s32
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_1024 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v32s32
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_1024 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v32s32
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_1024 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr40
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<32 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 %0:vgpr(<32 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
%1:sgpr(s32) = COPY $sgpr40 %1:sgpr(s32) = COPY $sgpr40
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: extract_vector_elt_v_s32_v8s32_idx_offset_1 name: extract_vector_elt_v_s32_v8s32_idx_offset_1
Show All 12 Lines bb.0:
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_1 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_1
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub1, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub1, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_1
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub1, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_1
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub1, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_1
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub1, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_1
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub1, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 1 %2:sgpr(s32) = G_CONSTANT i32 1
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3 %4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: extract_vector_elt_v_s32_v8s32_idx_offset_m1 name: extract_vector_elt_v_s32_v8s32_idx_offset_m1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $sgpr8 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $sgpr8
; MOVREL-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1 ; MOVREL-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1
; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL: $m0 = COPY [[S_ADD_U32_]] ; MOVREL: $m0 = COPY [[S_ADD_U32_]]
; MOVREL: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]] ; MOVREL: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_U32_]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_U32_]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL_GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX6: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; MOVREL_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX8: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
; GPRIDX_GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 -1 %2:sgpr(s32) = G_CONSTANT i32 -1
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3 %4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 14 Lines bb.0:
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_7 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_7
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub7, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub7, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_7
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: $m0 = COPY [[COPY1]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub7, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_7
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: $m0 = COPY [[COPY1]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub7, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_7
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub7, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_7
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[COPY1]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub7, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 7 %2:sgpr(s32) = G_CONSTANT i32 7
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3 %4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: extract_vector_elt_v_s32_v8s32_idx_offset_8 name: extract_vector_elt_v_s32_v8s32_idx_offset_8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $sgpr8 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $sgpr8
; MOVREL-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8 ; MOVREL-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8
; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL: $m0 = COPY [[S_ADD_U32_]] ; MOVREL: $m0 = COPY [[S_ADD_U32_]]
; MOVREL: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]] ; MOVREL: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]] ; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8 ; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_U32_]], 1, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_U32_]], 1, implicit-def $m0, implicit $m0
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0 ; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MOVREL_GFX6-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8
; MOVREL_GFX6: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; MOVREL_GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX6: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX6: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX6: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; MOVREL_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8
; MOVREL_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; MOVREL_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL_GFX8: $m0 = COPY [[S_ADD_I32_]]
; MOVREL_GFX8: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
; MOVREL_GFX8: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
; GPRIDX_GFX8-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8
; GPRIDX_GFX8: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; GPRIDX_GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX8: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX8: S_SET_GPR_IDX_OFF
; GPRIDX_GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; GPRIDX_GFX9-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8
; GPRIDX_GFX9: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX_GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX_GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; GPRIDX_GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX_GFX9: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 1, implicit-def $m0, implicit $m0
; GPRIDX_GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
; GPRIDX_GFX9: S_SET_GPR_IDX_OFF
; GPRIDX_GFX9: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = G_CONSTANT i32 8 %2:sgpr(s32) = G_CONSTANT i32 8
%3:sgpr(s32) = G_ADD %1, %2 %3:sgpr(s32) = G_ADD %1, %2
%4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3 %4:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

Show First 20 Lines • Show All 528 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8, $sgpr9
; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8 ; MOVREL-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 ; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL: $m0 = COPY [[S_ADD_U32_]] ; MOVREL: $m0 = COPY [[S_ADD_I32_]]
; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec ; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]] ; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8 ; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_U32_]], 8, implicit-def $m0, implicit $m0 ; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 8, implicit-def $m0, implicit $m0
; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec ; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
; GPRIDX: S_SET_GPR_IDX_OFF ; GPRIDX: S_SET_GPR_IDX_OFF
; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]] ; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:vgpr(s32) = COPY $vgpr8 %1:vgpr(s32) = COPY $vgpr8
%2:sgpr(s32) = COPY $sgpr9 %2:sgpr(s32) = COPY $sgpr9
%3:sgpr(s32) = G_CONSTANT i32 8 %3:sgpr(s32) = G_CONSTANT i32 8
%4:sgpr(s32) = G_ADD %2, %3 %4:sgpr(s32) = G_ADD %2, %3
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9 liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8, $sgpr9
; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8 ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 ; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc ; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; MOVREL: $m0 = COPY [[S_ADD_U32_]] ; MOVREL: $m0 = COPY [[S_ADD_I32_]]
; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0 ; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0
; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]] ; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8 ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8 ; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc ; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GPRIDX: $m0 = COPY [[S_ADD_U32_]] ; GPRIDX: $m0 = COPY [[S_ADD_I32_]]
; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0 ; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0
; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]] ; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s32) = COPY $sgpr8 %1:sgpr(s32) = COPY $sgpr8
%2:sgpr(s32) = COPY $sgpr9 %2:sgpr(s32) = COPY $sgpr9
%3:sgpr(s32) = G_CONSTANT i32 8 %3:sgpr(s32) = G_CONSTANT i32 8
%4:sgpr(s32) = G_ADD %2, %3 %4:sgpr(s32) = G_ADD %2, %3
%5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 %5:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Lines bb.0:
; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]] ; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]
; GFX10-LABEL: name: lshr_s64_sv ; GFX10-LABEL: name: lshr_s64_sv
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_LSHR_B64_]] ; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s64) = G_LSHR %0, %1 %2:vgpr(s64) = G_LSHR %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: lshr_s64_vs name: lshr_s64_vs
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; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]] ; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]
; GFX10-LABEL: name: lshr_s64_vs ; GFX10-LABEL: name: lshr_s64_vs
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX10: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_LSHR_B64_]] ; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s64) = G_LSHR %0, %1 %2:vgpr(s64) = G_LSHR %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: lshr_s64_vv name: lshr_s64_vv
Show All 22 Lines bb.0:
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]] ; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]
; GFX10-LABEL: name: lshr_s64_vv ; GFX10-LABEL: name: lshr_s64_vv
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_LSHR_B64_]] ; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = COPY $vgpr2 %1:vgpr(s32) = COPY $vgpr2
%2:vgpr(s64) = G_LSHR %0, %1 %2:vgpr(s64) = G_LSHR %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir

Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2 liveins: $sgpr0, $sgpr1, $sgpr2
; GFX8-LABEL: name: add_s32_sgpr_sgpr_sgpr ; GFX8-LABEL: name: add_s32_sgpr_sgpr_sgpr
; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2 ; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX8: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 [[S_ADD_U32_]], [[COPY2]], implicit-def $scc ; GFX8: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[COPY2]], implicit-def $scc
; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_1]] ; GFX8: S_ENDPGM 0, implicit [[S_ADD_I32_1]]
; GFX9-LABEL: name: add_s32_sgpr_sgpr_sgpr ; GFX9-LABEL: name: add_s32_sgpr_sgpr_sgpr
; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2 ; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 [[S_ADD_U32_]], [[COPY2]], implicit-def $scc ; GFX9: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[COPY2]], implicit-def $scc
; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_1]] ; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_1]]
; GFX10-LABEL: name: add_s32_sgpr_sgpr_sgpr ; GFX10-LABEL: name: add_s32_sgpr_sgpr_sgpr
; GFX10: liveins: $sgpr0, $sgpr1, $sgpr2 ; GFX10: liveins: $sgpr0, $sgpr1, $sgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GFX10: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX10: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 [[S_ADD_U32_]], [[COPY2]], implicit-def $scc ; GFX10: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[COPY2]], implicit-def $scc
; GFX10: S_ENDPGM 0, implicit [[S_ADD_U32_1]] ; GFX10: S_ENDPGM 0, implicit [[S_ADD_I32_1]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2 %2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = G_ADD %0, %1 %3:sgpr(s32) = G_ADD %0, %1
%4:sgpr(s32) = G_ADD %3, %2 %4:sgpr(s32) = G_ADD %3, %2
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Lines bb.0:
; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]] ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
; GFX10-LABEL: name: shl_s64_sv ; GFX10-LABEL: name: shl_s64_sv
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_LSHL_B64_]] ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s64) = G_SHL %0, %1 %2:vgpr(s64) = G_SHL %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: shl_s64_vs name: shl_s64_vs
Show All 22 Lines bb.0:
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]] ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
; GFX10-LABEL: name: shl_s64_vs ; GFX10-LABEL: name: shl_s64_vs
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX10: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_LSHL_B64_]] ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s64) = G_SHL %0, %1 %2:vgpr(s64) = G_SHL %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: shl_s64_vv name: shl_s64_vv
Show All 22 Lines bb.0:
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec ; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]] ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
; GFX10-LABEL: name: shl_s64_vv ; GFX10-LABEL: name: shl_s64_vv
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_LSHL_B64_]] ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = COPY $vgpr2 %1:vgpr(s32) = COPY $vgpr2
%2:vgpr(s64) = G_SHL %0, %1 %2:vgpr(s64) = G_SHL %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
--- ---
name: sub_s32 name: sub_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX6-LABEL: name: sub_s32 ; GFX6-LABEL: name: sub_s32
; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 ; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GFX6: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_SUB_I32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec ; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_SUB_I32_e64 [[COPY2]], [[S_SUB_I32_]], 0, implicit $exec
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_SUB_I32_e64 [[S_SUB_U32_]], %7, 0, implicit $exec ; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_SUB_I32_e64 [[S_SUB_I32_]], %7, 0, implicit $exec
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_SUB_I32_e64 %8, [[COPY2]], 0, implicit $exec ; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_SUB_I32_e64 %8, [[COPY2]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit %9 ; GFX6: S_ENDPGM 0, implicit %9
; GFX9-LABEL: name: sub_s32 ; GFX9-LABEL: name: sub_s32
; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GFX9: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec ; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_I32_]], 0, implicit $exec
; GFX9: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec ; GFX9: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_I32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
; GFX9: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec ; GFX9: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]] ; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
; GFX10-LABEL: name: sub_s32 ; GFX10-LABEL: name: sub_s32
; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 ; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GFX10: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX10: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec ; GFX10: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_I32_]], 0, implicit $exec
; GFX10: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec ; GFX10: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_I32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
; GFX10: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec ; GFX10: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]] ; GFX10: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:vgpr(s32) = COPY $vgpr0 %2:vgpr(s32) = COPY $vgpr0
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%4:sgpr(s32) = G_CONSTANT i32 1 %4:sgpr(s32) = G_CONSTANT i32 1
%5:sgpr(s32) = G_CONSTANT i32 4096 %5:sgpr(s32) = G_CONSTANT i32 4096
Show All 16 Lines

llvm/test/CodeGen/AMDGPU/ashr.v2i16.ll

Show All 36 Lines
; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}} ; CI: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
; CI-DAG: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], [[RHS]] ; CI-DAG: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], [[RHS]]
; CI-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 ; CI-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, [[LHS]] ; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, [[LHS]]
; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} ; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; CI: v_ashr_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; CI: v_ashr_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} ; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} ; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_ashr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { define amdgpu_kernel void @v_ashr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/bfe-patterns.ll

Show All 18 Linesdefine amdgpu_kernel void @v_ubfe_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
ret void ret void
} }
; GCN-LABEL: {{^}}v_ubfe_sub_multi_use_shl_i32: ; GCN-LABEL: {{^}}v_ubfe_sub_multi_use_shl_i32:
; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]] ; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
; GCN-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]] ; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
; GCN-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]] ; SI-NEXT: v_lshr_b32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
; VI-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
; GCN: [[BFE]] ; GCN: [[BFE]]
; GCN: [[SHL]] ; GCN: [[SHL]]
define amdgpu_kernel void @v_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x %in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
%in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x %in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_sbfe_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
ret void ret void
} }
; GCN-LABEL: {{^}}v_sbfe_sub_multi_use_shl_i32: ; GCN-LABEL: {{^}}v_sbfe_sub_multi_use_shl_i32:
; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]] ; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
; GCN-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]] ; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
; GCN-NEXT: v_ashrrev_i32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]] ; SI-NEXT: v_ashr_i32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
; VI-NEXT: v_ashrrev_i32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
; GCN: [[BFE]] ; GCN: [[BFE]]
; GCN: [[SHL]] ; GCN: [[SHL]]
define amdgpu_kernel void @v_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
%id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
%in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x %in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
%in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x %in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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llvm/test/CodeGen/AMDGPU/commute-shifts.ll

Show All 11 Lines
; SI-NEXT: s_mov_b32 s3, s0 ; SI-NEXT: s_mov_b32 s3, s0
; SI-NEXT: s_mov_b32 s4, s0 ; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s0 ; SI-NEXT: s_mov_b32 s5, s0
; SI-NEXT: s_mov_b32 s6, s0 ; SI-NEXT: s_mov_b32 s6, s0
; SI-NEXT: s_mov_b32 s7, s0 ; SI-NEXT: s_mov_b32 s7, s0
; SI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm ; SI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm
; SI-NEXT: v_and_b32_e32 v0, 7, v0 ; SI-NEXT: v_and_b32_e32 v0, 7, v0
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, v0, v2 ; SI-NEXT: v_lshr_b32_e32 v0, v2, v0
; SI-NEXT: v_and_b32_e32 v0, 1, v0 ; SI-NEXT: v_and_b32_e32 v0, 1, v0
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, s0, v0 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, s0, v0
; SI-NEXT: ; return to shader part epilog ; SI-NEXT: ; return to shader part epilog
; ;
; VI-LABEL: main: ; VI-LABEL: main:
; VI: ; %bb.0: ; %bb ; VI: ; %bb.0: ; %bb
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llvm/test/CodeGen/AMDGPU/extract-lowbits.ll

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
} }
define i32 @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits) nounwind { define i32 @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits) nounwind {
; SI-LABEL: bzhi32_d1_indexzext: ; SI-LABEL: bzhi32_d1_indexzext:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v1 ; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 ; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, v1, v0 ; SI-NEXT: v_lshl_b32_e32 v0, v0, v1
; SI-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; SI-NEXT: v_lshr_b32_e32 v0, v0, v1
; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: s_setpc_b64 s[30:31]
; ;
; VI-LABEL: bzhi32_d1_indexzext: ; VI-LABEL: bzhi32_d1_indexzext:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_sub_u16_e32 v1, 32, v1 ; VI-NEXT: v_sub_u16_e32 v1, 32, v1
; VI-NEXT: v_and_b32_e32 v1, 0xff, v1 ; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
; VI-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; VI-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
%numhighbits = sub i8 32, %numlowbits %numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32 %sh_prom = zext i8 %numhighbits to i32
%highbitscleared = shl i32 %val, %sh_prom %highbitscleared = shl i32 %val, %sh_prom
%masked = lshr i32 %highbitscleared, %sh_prom %masked = lshr i32 %highbitscleared, %sh_prom
ret i32 %masked ret i32 %masked
} }

llvm/test/CodeGen/AMDGPU/inline-asm.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK --check-prefix=PRE-GFX8 %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK --check-prefix=GFX8 %s
; CHECK-LABEL: {{^}}inline_asm: ; CHECK-LABEL: {{^}}inline_asm:
; CHECK: s_endpgm ; CHECK: s_endpgm
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_kernel void @inline_asm(i32 addrspace(1)* %out) { define amdgpu_kernel void @inline_asm(i32 addrspace(1)* %out) {
entry: entry:
store i32 5, i32 addrspace(1)* %out store i32 5, i32 addrspace(1)* %out
call void asm sideeffect "s_endpgm", ""() call void asm sideeffect "s_endpgm", ""()
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Linesentry:
call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1) call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1)
ret void ret void
} }
; CHECK-LABEL: {{^}}muliple_def_phys_vgpr: ; CHECK-LABEL: {{^}}muliple_def_phys_vgpr:
; CHECK: ; def v0 ; CHECK: ; def v0
; CHECK: v_mov_b32_e32 v1, v0 ; CHECK: v_mov_b32_e32 v1, v0
; CHECK: ; def v0 ; CHECK: ; def v0
; CHECK: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1 ; PRE-GFX8: v_lshl_b32_e32 v{{[0-9]+}}, v1, v0
; GFX8: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1
define amdgpu_kernel void @muliple_def_phys_vgpr() { define amdgpu_kernel void @muliple_def_phys_vgpr() {
entry: entry:
%def0 = call i32 asm sideeffect "; def $0 ", "={v0}"() %def0 = call i32 asm sideeffect "; def $0 ", "={v0}"()
%def1 = call i32 asm sideeffect "; def $0 ", "={v0}"() %def1 = call i32 asm sideeffect "; def $0 ", "={v0}"()
%add = shl i32 %def0, %def1 %add = shl i32 %def0, %def1
store i32 %add, i32 addrspace(1)* undef store i32 %add, i32 addrspace(1)* undef
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 { define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
; GFX9-LABEL: s_lshr_v2i16: ; GFX9-LABEL: s_lshr_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c
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; CI-NEXT: s_mov_b32 s8, 0xffff ; CI-NEXT: s_mov_b32 s8, 0xffff
; CI-NEXT: s_mov_b64 s[2:3], s[6:7] ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s8, v2
; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v3, s8, v3
; CI-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; CI-NEXT: v_lshr_b32_e32 v2, v2, v3
; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v4 ; CI-NEXT: v_lshr_b32_e32 v3, v4, v5
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v4 ; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v5 ; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s8, v2
; CI-NEXT: v_and_b32_e32 v4, s8, v4 ; CI-NEXT: v_and_b32_e32 v4, s8, v4
; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v3, s8, v3
; CI-NEXT: v_and_b32_e32 v5, s8, v5 ; CI-NEXT: v_and_b32_e32 v5, s8, v5
; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v3 ; CI-NEXT: v_lshr_b32_e32 v3, v3, v5
; CI-NEXT: v_lshrrev_b32_e32 v5, v9, v7 ; CI-NEXT: v_lshr_b32_e32 v5, v7, v9
; CI-NEXT: v_lshrrev_b32_e32 v2, v4, v2 ; CI-NEXT: v_lshr_b32_e32 v2, v2, v4
; CI-NEXT: v_lshrrev_b32_e32 v4, v8, v6 ; CI-NEXT: v_lshr_b32_e32 v4, v6, v8
; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; CI-NEXT: v_or_b32_e32 v3, v3, v5 ; CI-NEXT: v_or_b32_e32 v3, v3, v5
; CI-NEXT: v_or_b32_e32 v2, v2, v4 ; CI-NEXT: v_or_b32_e32 v2, v2, v4
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
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llvm/test/CodeGen/AMDGPU/sext-in-reg.ll

Show First 20 Lines • Show All 571 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_sext_in_reg_i1_i16(i16 addrspace(3)* %out, i16 addrspace(1)* %ptr) #0 {
store i16 %sext, i16 addrspace(3)* %out.gep store i16 %sext, i16 addrspace(3)* %out.gep
ret void ret void
} }
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_i16_nonload: ; FUNC-LABEL: {{^}}v_sext_in_reg_i1_i16_nonload:
; GCN: {{buffer|flat|global}}_load_ushort [[VAL0:v[0-9]+]] ; GCN: {{buffer|flat|global}}_load_ushort [[VAL0:v[0-9]+]]
; GCN: {{buffer|flat|global}}_load_ushort [[VAL1:v[0-9]+]] ; GCN: {{buffer|flat|global}}_load_ushort [[VAL1:v[0-9]+]]
; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], [[VAL1]], [[VAL0]] ; SI: v_lshl_b32_e32 [[REG:v[0-9]+]], [[VAL0]], [[VAL1]]
; GFX89: v_lshlrev_b16_e32 [[REG:v[0-9]+]], [[VAL1]], [[VAL0]] ; GFX89: v_lshlrev_b16_e32 [[REG:v[0-9]+]], [[VAL1]], [[VAL0]]
; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[REG]], 0, 1{{$}} ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[REG]], 0, 1{{$}}
; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]] ; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]]
define amdgpu_kernel void @v_sext_in_reg_i1_i16_nonload(i16 addrspace(3)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr, i16 %s.val) nounwind { define amdgpu_kernel void @v_sext_in_reg_i1_i16_nonload(i16 addrspace(3)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr, i16 %s.val) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() %tid = call i32 @llvm.r600.read.tidig.x()
%a.gep = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid %a.gep = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
%b.gep = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid %b.gep = getelementptr i16, i16 addrspace(1)* %bptr, i32 %tid
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llvm/test/CodeGen/AMDGPU/shift-select.ll

  • This file was added.
; RUN: llc -march=amdgcn -mcpu=tahiti -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX6 %s
; RUN: llc -march=amdgcn -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s
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Please add another line for gfx1010.

rampitec: Please add another line for gfx1010.
; GCN-LABEL: name: s_shl_i32
; GCN: S_LSHL_B32
define amdgpu_kernel void @s_shl_i32(i32 addrspace(1)* %out, i32 %lhs, i32 %rhs) {
%result = shl i32 %lhs, %rhs
store i32 %result, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: name: v_shl_i32
; GFX6: V_LSHL_B32_e32
; GFX8: V_LSHLREV_B32_e32
define amdgpu_kernel void @v_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
%a = load i32, i32 addrspace(1)* %in
%b = load i32, i32 addrspace(1)* %b_ptr
%result = shl i32 %a, %b
store i32 %result, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: name: s_lshr_i32
; GCN: S_LSHR_B32
define amdgpu_kernel void @s_lshr_i32(i32 addrspace(1)* %out, i32 %lhs, i32 %rhs) {
%result = lshr i32 %lhs, %rhs
store i32 %result, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: name: v_lshr_i32
; GFX6: V_LSHR_B32_e32
; GFX8: V_LSHRREV_B32_e64
define amdgpu_kernel void @v_lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
%a = load i32, i32 addrspace(1)* %in
%b = load i32, i32 addrspace(1)* %b_ptr
%result = lshr i32 %a, %b
store i32 %result, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: name: s_ashr_i32
; GCN: S_ASHR_I32
define amdgpu_kernel void @s_ashr_i32(i32 addrspace(1)* %out, i32 %lhs, i32 %rhs) #0 {
%result = ashr i32 %lhs, %rhs
store i32 %result, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: name: v_ashr_i32
; GFX6: V_ASHR_I32_e32
; GFX8: V_ASHRREV_I32_e64
define amdgpu_kernel void @v_ashr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
rampitecUnsubmitted
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You also need tests for i64.

rampitec: You also need tests for i64.
rampitecUnsubmitted
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Would be LGTM if there were i64 tests.

rampitec: Would be LGTM if there were i64 tests.
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
%a = load i32, i32 addrspace(1)* %in
%b = load i32, i32 addrspace(1)* %b_ptr
%result = ashr i32 %a, %b
store i32 %result, i32 addrspace(1)* %out
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x()
No newline at end of file
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Newline.

rampitec: Newline.

llvm/test/CodeGen/AMDGPU/shl.ll

Show First 20 Lines • Show All 295 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_mov_b64 s[12:13], s[2:3] ; GCN-NEXT: s_mov_b64 s[12:13], s[2:3]
; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 ; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0
; GCN-NEXT: buffer_load_ushort v0, v[0:1], s[12:15], 0 addr64 offset:2 ; GCN-NEXT: buffer_load_ushort v0, v[0:1], s[12:15], 0 addr64 offset:2
; GCN-NEXT: s_mov_b32 s4, s0 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_lshlrev_b32_e32 v0, v0, v2 ; GCN-NEXT: v_lshl_b32_e32 v0, v2, v0
; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; EG-LABEL: shl_i16_computed_amount: ; EG-LABEL: shl_i16_computed_amount:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @8 ; EG-NEXT: TEX 0 @8
; EG-NEXT: ALU 1, @13, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 1, @13, KC0[CB0:0-32], KC1[]
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; GCN-NEXT: s_mov_b32 s4, s0 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s0, 0xffff ; GCN-NEXT: s_mov_b32 s0, 0xffff
; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GCN-NEXT: v_and_b32_e32 v0, s0, v0 ; GCN-NEXT: v_and_b32_e32 v0, s0, v0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GCN-NEXT: v_lshlrev_b32_e32 v0, v0, v1 ; GCN-NEXT: v_lshl_b32_e32 v0, v1, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, v3, v2 ; GCN-NEXT: v_lshl_b32_e32 v1, v2, v3
; GCN-NEXT: v_and_b32_e32 v0, s0, v0 ; GCN-NEXT: v_and_b32_e32 v0, s0, v0
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_or_b32_e32 v0, v0, v1 ; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; EG-LABEL: shl_v2i16: ; EG-LABEL: shl_v2i16:
; EG: ; %bb.0: ; EG: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_and_b32_e32 v8, s8, v4 ; GCN-NEXT: v_and_b32_e32 v8, s8, v4
; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_and_b32_e32 v9, s8, v5 ; GCN-NEXT: v_and_b32_e32 v9, s8, v5
; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_lshlrev_b32_e32 v5, v5, v7 ; GCN-NEXT: v_lshl_b32_e32 v5, v7, v5
; GCN-NEXT: v_lshlrev_b32_e32 v3, v9, v3 ; GCN-NEXT: v_lshl_b32_e32 v3, v3, v9
; GCN-NEXT: v_lshlrev_b32_e32 v4, v4, v6 ; GCN-NEXT: v_lshl_b32_e32 v4, v6, v4
; GCN-NEXT: v_lshlrev_b32_e32 v2, v8, v2 ; GCN-NEXT: v_lshl_b32_e32 v2, v2, v8
; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GCN-NEXT: v_and_b32_e32 v3, s8, v3 ; GCN-NEXT: v_and_b32_e32 v3, s8, v3
; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GCN-NEXT: v_and_b32_e32 v2, s8, v2 ; GCN-NEXT: v_and_b32_e32 v2, s8, v2
; GCN-NEXT: v_or_b32_e32 v3, v3, v5 ; GCN-NEXT: v_or_b32_e32 v3, v3, v5
; GCN-NEXT: v_or_b32_e32 v2, v2, v4 ; GCN-NEXT: v_or_b32_e32 v2, v2, v4
; GCN-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; GCN-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
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llvm/test/CodeGen/AMDGPU/shl.v2i16.ll

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; CI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4 ; CI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 offset:4
; CI-NEXT: s_mov_b32 s8, 0xffff ; CI-NEXT: s_mov_b32 s8, 0xffff
; CI-NEXT: s_mov_b64 s[2:3], s[6:7] ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_and_b32_e32 v5, s8, v3 ; CI-NEXT: v_and_b32_e32 v5, s8, v3
; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; CI-NEXT: v_lshlrev_b32_e32 v3, v3, v4 ; CI-NEXT: v_lshl_b32_e32 v3, v4, v3
; CI-NEXT: v_lshlrev_b32_e32 v2, v5, v2 ; CI-NEXT: v_lshl_b32_e32 v2, v2, v5
; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s8, v2
; CI-NEXT: v_or_b32_e32 v2, v2, v3 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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; CI-NEXT: s_waitcnt vmcnt(1) ; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2 ; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_and_b32_e32 v8, s8, v4 ; CI-NEXT: v_and_b32_e32 v8, s8, v4
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; CI-NEXT: v_and_b32_e32 v9, s8, v5 ; CI-NEXT: v_and_b32_e32 v9, s8, v5
; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3 ; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; CI-NEXT: v_lshlrev_b32_e32 v5, v5, v7 ; CI-NEXT: v_lshl_b32_e32 v5, v7, v5
; CI-NEXT: v_lshlrev_b32_e32 v3, v9, v3 ; CI-NEXT: v_lshl_b32_e32 v3, v3, v9
; CI-NEXT: v_lshlrev_b32_e32 v4, v4, v6 ; CI-NEXT: v_lshl_b32_e32 v4, v6, v4
; CI-NEXT: v_lshlrev_b32_e32 v2, v8, v2 ; CI-NEXT: v_lshl_b32_e32 v2, v2, v8
; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; CI-NEXT: v_and_b32_e32 v3, s8, v3 ; CI-NEXT: v_and_b32_e32 v3, s8, v3
; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; CI-NEXT: v_and_b32_e32 v2, s8, v2 ; CI-NEXT: v_and_b32_e32 v2, s8, v2
; CI-NEXT: v_or_b32_e32 v3, v3, v5 ; CI-NEXT: v_or_b32_e32 v3, v3, v5
; CI-NEXT: v_or_b32_e32 v2, v2, v4 ; CI-NEXT: v_or_b32_e32 v2, v2, v4
; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
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