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Differential D73445

AMDGPU/GlobalISel: Prefer merge/unmerge ops to legalize TFE
ClosedPublic

Authored by arsenm on Jan 26 2020, 7:52 PM.

Details

Reviewers
nhaehnle
kerbowa
Summary

These have a better chance of combining with other operations and are
currently much better supported than G_EXTRACT.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
87 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
112 lines
25 lines

Diff 240469

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 2,716 Lines • ▼ Show 20 Lines MIB.addUse(RSrc) // rsrc
.addImm(AuxiliaryData) // cachepolicy, swizzled buffer(imm) .addImm(AuxiliaryData) // cachepolicy, swizzled buffer(imm)
.addImm(HasVIndex ? -1 : 0) // idxen(imm) .addImm(HasVIndex ? -1 : 0) // idxen(imm)
.addMemOperand(MMO); .addMemOperand(MMO);
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
// Produce a vector of s16 elements from s32 pieces.
static void truncToS16Vector(MachineIRBuilder &B, Register DstReg,
ArrayRef<Register> UnmergeParts) {
const LLT S16 = LLT::scalar(16);
SmallVector<Register, 4> RemergeParts(UnmergeParts.size());
for (int I = 0, E = UnmergeParts.size(); I != E; ++I)
RemergeParts[I] = B.buildTrunc(S16, UnmergeParts[I]).getReg(0);
B.buildBuildVector(DstReg, RemergeParts);
}
/// Convert a set of s32 registers to a result vector with s16 elements.
static void bitcastToS16Vector(MachineIRBuilder &B, Register DstReg,
ArrayRef<Register> UnmergeParts) {
MachineRegisterInfo &MRI = *B.getMRI();
const LLT V2S16 = LLT::vector(2, 16);
LLT TargetTy = MRI.getType(DstReg);
int NumElts = UnmergeParts.size();
if (NumElts == 1) {
assert(TargetTy == V2S16);
B.buildBitcast(DstReg, UnmergeParts[0]);
return;
}
SmallVector<Register, 4> RemergeParts(NumElts);
for (int I = 0; I != NumElts; ++I)
RemergeParts[I] = B.buildBitcast(V2S16, UnmergeParts[I]).getReg(0);
if (TargetTy.getSizeInBits() == 32u * NumElts) {
B.buildConcatVectors(DstReg, RemergeParts);
return;
}
const LLT V3S16 = LLT::vector(3, 16);
const LLT V6S16 = LLT::vector(6, 16);
// Widen to v6s16 and unpack v3 parts.
assert(TargetTy == V3S16);
RemergeParts.push_back(B.buildUndef(V2S16).getReg(0));
auto Concat = B.buildConcatVectors(V6S16, RemergeParts);
B.buildUnmerge({DstReg, MRI.createGenericVirtualRegister(V3S16)}, Concat);
}
// FIXME: Just vector trunc should be sufficent, but legalization currently // FIXME: Just vector trunc should be sufficent, but legalization currently
// broken. // broken.
static void repackUnpackedD16Load(MachineIRBuilder &B, Register DstReg, static void repackUnpackedD16Load(MachineIRBuilder &B, Register DstReg,
Register WideDstReg) { Register WideDstReg) {
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
const LLT S16 = LLT::scalar(16); const LLT S16 = LLT::scalar(16);
auto Unmerge = B.buildUnmerge(S32, WideDstReg); auto Unmerge = B.buildUnmerge(S32, WideDstReg);
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines if (BaseOpcode->Store) { // No TFE for stores?
return true; return true;
} }
if (BaseOpcode->Atomic) // No d16 atomics, or TFE? if (BaseOpcode->Atomic) // No d16 atomics, or TFE?
return true; return true;
Register DstReg = MI.getOperand(0).getReg(); Register DstReg = MI.getOperand(0).getReg();
LLT Ty = MRI->getType(DstReg); LLT Ty = MRI->getType(DstReg);
const LLT EltTy = Ty.getScalarType();
const bool IsD16 = Ty.getScalarType() == S16; const bool IsD16 = Ty.getScalarType() == S16;
const unsigned NumElts = Ty.isVector() ? Ty.getNumElements() : 1; const unsigned NumElts = Ty.isVector() ? Ty.getNumElements() : 1;
if (IsTFE) { if (IsTFE) {
// In the IR, TFE is supposed to be used with a 2 element struct return // In the IR, TFE is supposed to be used with a 2 element struct return
// type. The intruction really returns these two values in one contiguous // type. The intruction really returns these two values in one contiguous
// register, with one additional dword beyond the loaded data. Rewrite the // register, with one additional dword beyond the loaded data. Rewrite the
// return type to use a single register result. // return type to use a single register result.
Show All 24 Lines if (IsTFE) {
// FIXME: Do we need to notify the observer of the instruction change? // FIXME: Do we need to notify the observer of the instruction change?
MI.getOperand(0).setReg(TFEReg); MI.getOperand(0).setReg(TFEReg);
MI.RemoveOperand(1); MI.RemoveOperand(1);
// Insert after the instruction. // Insert after the instruction.
B.setInsertPt(*MI.getParent(), ++MI.getIterator()); B.setInsertPt(*MI.getParent(), ++MI.getIterator());
// TODO: Should probably unmerge to s32 pieces and repack instead of using // Now figure out how to copy the new result register back into the old
// extracts. // result.
if (RoundedTy == Ty) {
B.buildExtract(DstReg, TFEReg, 0); SmallVector<Register, 5> UnmergeResults(TFETy.getNumElements(), Dst1Reg);
} else { int NumDataElts = TFETy.getNumElements() - 1;
// If we had to round the data type (i.e. this was a <3 x s16>), do the
// weird extract separately. if (!Ty.isVector()) {
auto DataPart = B.buildExtract(RoundedTy, TFEReg, 0); // Simplest case is a trivial unmerge (plus a truncate for d16).
B.buildExtract(DstReg, DataPart, 0); UnmergeResults[0] = Ty == S32 ?
DstReg : MRI->createGenericVirtualRegister(S32);
B.buildUnmerge(UnmergeResults, TFEReg);
if (Ty != S32)
B.buildTrunc(DstReg, UnmergeResults[0]);
return true;
} }
B.buildExtract(Dst1Reg, TFEReg, RoundedTy.getSizeInBits()); // We have to repack into a new vector of some kind.
for (int I = 0; I != NumDataElts; ++I)
UnmergeResults[I] = MRI->createGenericVirtualRegister(S32);
B.buildUnmerge(UnmergeResults, TFEReg);
// Drop the final TFE element.
ArrayRef<Register> DataPart(UnmergeResults.data(), NumDataElts);
if (EltTy == S32)
B.buildBuildVector(DstReg, DataPart);
else if (ST.hasUnpackedD16VMem())
truncToS16Vector(B, DstReg, DataPart);
else
bitcastToS16Vector(B, DstReg, DataPart);
return true; return true;
} }
// Must be an image load. // Must be an image load.
if (!Ty.isVector() || Ty.getElementType() != S16) if (!Ty.isVector() || Ty.getElementType() != S16)
return true; return true;
B.setInsertPt(*MI.getParent(), ++MI.getIterator()); B.setInsertPt(*MI.getParent(), ++MI.getIterator());
▲ Show 20 Lines • Show All 181 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll

Show First 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdefine amdgpu_ps half @image_load_tfe_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; UNPACKED: [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8") ; UNPACKED: [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<2 x s32>), 0 ; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<2 x s32>), 32 ; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: G_STORE [[EXTRACT1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; UNPACKED: $vgpr0 = COPY [[COPY10]](s32) ; UNPACKED: $vgpr0 = COPY [[COPY10]](s32)
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0 ; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
; PACKED-LABEL: name: image_load_tfe_f16 ; PACKED-LABEL: name: image_load_tfe_f16
; PACKED: bb.1 (%ir-block.0): ; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 ; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; PACKED: [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8") ; PACKED: [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INT]](<2 x s32>), 0 ; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
; PACKED: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[EXTRACT]](<2 x s16>) ; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; PACKED: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<2 x s32>), 32 ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; PACKED: G_STORE [[EXTRACT1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; PACKED: $vgpr0 = COPY [[COPY10]](s32) ; PACKED: $vgpr0 = COPY [[COPY10]](s32)
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0 ; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
%res = call { half, i32 } @llvm.amdgcn.image.load.2d.sl_f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %res = call { half, i32 } @llvm.amdgcn.image.load.2d.sl_f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { half, i32 } %res, 0 %tex = extractvalue { half, i32 } %res, 0
%tfe = extractvalue { half, i32 } %res, 1 %tfe = extractvalue { half, i32 } %res, 1
store i32 %tfe, i32 addrspace(1)* undef store i32 %tfe, i32 addrspace(1)* undef
ret half %tex ret half %tex
} }
Show All 10 Linesdefine amdgpu_ps <2 x half> @image_load_tfe_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; UNPACKED: [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8") ; UNPACKED: [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[INT]](<3 x s32>), 0 ; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[EXTRACT]](<2 x s32>), 0 ; UNPACKED: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<3 x s32>), 64 ; UNPACKED: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; UNPACKED: G_STORE [[EXTRACT2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>) ; UNPACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: $vgpr0 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0 ; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
; PACKED-LABEL: name: image_load_tfe_v2f16 ; PACKED-LABEL: name: image_load_tfe_v2f16
; PACKED: bb.1 (%ir-block.0): ; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 ; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; PACKED: [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8") ; PACKED: [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INT]](<2 x s32>), 0 ; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
; PACKED: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<2 x s32>), 32 ; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
; PACKED: G_STORE [[EXTRACT1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>) ; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0 ; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
%res = call { <2 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f16i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %res = call { <2 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f16i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { <2 x half>, i32 } %res, 0 %tex = extractvalue { <2 x half>, i32 } %res, 0
%tfe = extractvalue { <2 x half>, i32 } %res, 1 %tfe = extractvalue { <2 x half>, i32 } %res, 1
store i32 %tfe, i32 addrspace(1)* undef store i32 %tfe, i32 addrspace(1)* undef
ret <2 x half> %tex ret <2 x half> %tex
} }
Show All 9 Linesdefine amdgpu_ps <3 x half> @image_load_tfe_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; UNPACKED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8") ; UNPACKED: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[INT]](<4 x s32>), 0 ; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<4 x s32>)
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[EXTRACT]](<3 x s32>), 0 ; UNPACKED: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<4 x s32>), 96 ; UNPACKED: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; UNPACKED: G_STORE [[EXTRACT2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; UNPACKED: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; UNPACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; UNPACKED: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT1]](<3 x s16>), 0 ; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; UNPACKED: [[EXTRACT3:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0 ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF1]](s16)
; UNPACKED: [[EXTRACT4:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32 ; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; UNPACKED: $vgpr0 = COPY [[EXTRACT3]](<2 x s16>) ; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; UNPACKED: $vgpr1 = COPY [[EXTRACT4]](<2 x s16>) ; UNPACKED: G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
; UNPACKED: $vgpr0 = COPY [[EXTRACT1]](<2 x s16>)
; UNPACKED: $vgpr1 = COPY [[EXTRACT2]](<2 x s16>)
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
; PACKED-LABEL: name: image_load_tfe_v3f16 ; PACKED-LABEL: name: image_load_tfe_v3f16
; PACKED: bb.1 (%ir-block.0): ; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 ; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; PACKED: [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8") ; PACKED: [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; PACKED: [[EXTRACT:%[0-9]+]]:_(<4 x s16>) = G_EXTRACT [[INT]](<3 x s32>), 0 ; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[EXTRACT]](<4 x s16>), 0 ; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
; PACKED: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<3 x s32>), 64 ; PACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
; PACKED: G_STORE [[EXTRACT2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; PACKED: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; PACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[DEF1]](<2 x s16>)
; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT1]](<3 x s16>), 0 ; PACKED: [[UV3:%[0-9]+]]:_(<3 x s16>), [[UV4:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; PACKED: [[EXTRACT3:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0 ; PACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; PACKED: [[EXTRACT4:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32 ; PACKED: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; PACKED: $vgpr0 = COPY [[EXTRACT3]](<2 x s16>) ; PACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[UV3]](<3 x s16>), 0
; PACKED: $vgpr1 = COPY [[EXTRACT4]](<2 x s16>) ; PACKED: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 0
; PACKED: [[EXTRACT1:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[INSERT]](<4 x s16>), 32
; PACKED: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
; PACKED: $vgpr1 = COPY [[EXTRACT1]](<2 x s16>)
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
%res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %res = call { <3 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f16i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { <3 x half>, i32 } %res, 0 %tex = extractvalue { <3 x half>, i32 } %res, 0
%tfe = extractvalue { <3 x half>, i32 } %res, 1 %tfe = extractvalue { <3 x half>, i32 } %res, 1
store i32 %tfe, i32 addrspace(1)* undef store i32 %tfe, i32 addrspace(1)* undef
ret <3 x half> %tex ret <3 x half> %tex
} }
Show All 9 Linesdefine amdgpu_ps <4 x half> @image_load_tfe_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; UNPACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; UNPACKED: [[INT:%[0-9]+]]:_(<5 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8") ; UNPACKED: [[INT:%[0-9]+]]:_(<5 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<4 x s32>) = G_EXTRACT [[INT]](<5 x s32>), 0 ; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<5 x s32>)
; UNPACKED: [[EXTRACT1:%[0-9]+]]:_(<4 x s16>) = G_EXTRACT [[EXTRACT]](<4 x s32>), 0 ; UNPACKED: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; UNPACKED: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<5 x s32>), 128 ; UNPACKED: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; UNPACKED: G_STORE [[EXTRACT2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; UNPACKED: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; UNPACKED: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[EXTRACT1]](<4 x s16>) ; UNPACKED: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; UNPACKED: $vgpr0 = COPY [[UV]](<2 x s16>) ; UNPACKED: G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: $vgpr1 = COPY [[UV1]](<2 x s16>) ; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; UNPACKED: $vgpr0 = COPY [[BUILD_VECTOR1]](<2 x s16>)
; UNPACKED: $vgpr1 = COPY [[BUILD_VECTOR2]](<2 x s16>)
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
; PACKED-LABEL: name: image_load_tfe_v4f16 ; PACKED-LABEL: name: image_load_tfe_v4f16
; PACKED: bb.1 (%ir-block.0): ; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 ; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; PACKED: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; PACKED: [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8") ; PACKED: [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; PACKED: [[EXTRACT:%[0-9]+]]:_(<4 x s16>) = G_EXTRACT [[INT]](<3 x s32>), 0 ; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
; PACKED: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<3 x s32>), 64 ; PACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV]](s32)
; PACKED: G_STORE [[EXTRACT1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; PACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[UV1]](s32)
; PACKED: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[EXTRACT]](<4 x s16>) ; PACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; PACKED: $vgpr0 = COPY [[UV]](<2 x s16>) ; PACKED: $vgpr0 = COPY [[BITCAST]](<2 x s16>)
; PACKED: $vgpr1 = COPY [[UV1]](<2 x s16>) ; PACKED: $vgpr1 = COPY [[BITCAST1]](<2 x s16>)
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
%res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %res = call { <4 x half>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f16i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { <4 x half>, i32 } %res, 0 %tex = extractvalue { <4 x half>, i32 } %res, 0
%tfe = extractvalue { <4 x half>, i32 } %res, 1 %tfe = extractvalue { <4 x half>, i32 } %res, 1
store i32 %tfe, i32 addrspace(1)* undef store i32 %tfe, i32 addrspace(1)* undef
ret <4 x half> %tex ret <4 x half> %tex
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Linesdefine amdgpu_ps float @image_load_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8") ; GCN: [[INT:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 1, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
; GCN: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<2 x s32>), 0 ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<2 x s32>)
; GCN: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<2 x s32>), 32 ; GCN: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: G_STORE [[EXTRACT1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr0 = COPY [[EXTRACT]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0 ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
%res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { float, i32 } %res, 0 %tex = extractvalue { float, i32 } %res, 0
%tfe = extractvalue { float, i32 } %res, 1 %tfe = extractvalue { float, i32 } %res, 1
store i32 %tfe, i32 addrspace(1)* undef store i32 %tfe, i32 addrspace(1)* undef
ret float %tex ret float %tex
} }
Show All 9 Linesdefine amdgpu_ps <2 x float> @image_load_tfe_v2f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8") ; GCN: [[INT:%[0-9]+]]:_(<3 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 3, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[EXTRACT:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[INT]](<3 x s32>), 0 ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<3 x s32>)
; GCN: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<3 x s32>), 64 ; GCN: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: G_STORE [[EXTRACT1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
%res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { <2 x float>, i32 } %res, 0 %tex = extractvalue { <2 x float>, i32 } %res, 0
%tfe = extractvalue { <2 x float>, i32 } %res, 1 %tfe = extractvalue { <2 x float>, i32 } %res, 1
store i32 %tfe, i32 addrspace(1)* undef store i32 %tfe, i32 addrspace(1)* undef
ret <2 x float> %tex ret <2 x float> %tex
Show All 11 Linesdefine amdgpu_ps <3 x float> @image_load_tfe_v3f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8") ; GCN: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[INT]](<4 x s32>), 0 ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<4 x s32>)
; GCN: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<4 x s32>), 96 ; GCN: G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: G_STORE [[EXTRACT1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32) ; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
%res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { <3 x float>, i32 } %res, 0 %tex = extractvalue { <3 x float>, i32 } %res, 0
%tfe = extractvalue { <3 x float>, i32 } %res, 1 %tfe = extractvalue { <3 x float>, i32 } %res, 1
store i32 %tfe, i32 addrspace(1)* undef store i32 %tfe, i32 addrspace(1)* undef
Show All 12 Linesdefine amdgpu_ps <4 x float> @image_load_tfe_v4f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[INT:%[0-9]+]]:_(<5 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 32 from custom "TargetCustom8") ; GCN: [[INT:%[0-9]+]]:_(<5 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.load.2d), 15, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 32 from custom "TargetCustom8")
; GCN: [[EXTRACT:%[0-9]+]]:_(<4 x s32>) = G_EXTRACT [[INT]](<5 x s32>), 0 ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INT]](<5 x s32>)
; GCN: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[INT]](<5 x s32>), 128 ; GCN: G_STORE [[UV4]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: G_STORE [[EXTRACT1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32) ; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32) ; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
%res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { <4 x float>, i32 } %res, 0 %tex = extractvalue { <4 x float>, i32 } %res, 0
%tfe = extractvalue { <4 x float>, i32 } %res, 1 %tfe = extractvalue { <4 x float>, i32 } %res, 1
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