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Differential D73393

AMDGPU/GlobalISel: Legalize G_SEXT_INREG
ClosedPublic

Authored by arsenm on Jan 24 2020, 4:34 PM.

Details

Reviewers
nhaehnle
kerbowa
cdevadas
Summary

Split the VALU 64-bit case in RegBankSelect.

Diff Detail

Event Timeline

arsenm created this revision.Jan 24 2020, 4:34 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 24 2020, 4:34 PM
Herald added subscribers: Petar.Avramovic, hiraditya, t-tye and 7 others. · View Herald Transcript
arsenm added a comment.Feb 3 2020, 7:12 AM

ping

kerbowa accepted this revision.Feb 4 2020, 12:17 PM

LGTM

This revision is now accepted and ready to land.Feb 4 2020, 12:17 PM
arsenm closed this revision.Feb 4 2020, 1:26 PM

05f2a04ba7fd4bced5e9c8866888bb91e8cee256

Revision Contents

Diff 240328

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 237 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
const std::initializer_list<LLT> FPTypes16 = { const std::initializer_list<LLT> FPTypes16 = {
S32, S64, S16 S32, S64, S16
}; };
const std::initializer_list<LLT> FPTypesPK16 = { const std::initializer_list<LLT> FPTypesPK16 = {
S32, S64, S16, V2S16 S32, S64, S16, V2S16
}; };
const LLT MinLegalScalarShiftTy = ST.has16BitInsts() ? S16 : S32;
setAction({G_BRCOND, S1}, Legal); // VCC branches setAction({G_BRCOND, S1}, Legal); // VCC branches
setAction({G_BRCOND, S32}, Legal); // SCC branches setAction({G_BRCOND, S32}, Legal); // SCC branches
// TODO: All multiples of 32, vectors of pointers, all v2s16 pairs, more // TODO: All multiples of 32, vectors of pointers, all v2s16 pairs, more
// elements for v3s16 // elements for v3s16
getActionDefinitionsBuilder(G_PHI) getActionDefinitionsBuilder(G_PHI)
.legalFor({S32, S64, V2S16, V4S16, S1, S128, S256}) .legalFor({S32, S64, V2S16, V4S16, S1, S128, S256})
.legalFor(AllS32Vectors) .legalFor(AllS32Vectors)
▲ Show 20 Lines • Show All 902 Lines • ▼ Show 20 Lines Builder.widenScalarIf(
LitTy.getSizeInBits() % 16 == 0 && LitTy.getSizeInBits() % 16 == 0 &&
BigTy.getSizeInBits() <= 1024; BigTy.getSizeInBits() <= 1024;
}) })
// Any vectors left are the wrong size. Scalarize them. // Any vectors left are the wrong size. Scalarize them.
.scalarize(0) .scalarize(0)
.scalarize(1); .scalarize(1);
} }
// TODO: Make legal for s32, s64. s64 case needs break down in regbankselect. // S64 is only legal on SALU, and needs to be broken into 32-bit elements in
auto &SextInReg = getActionDefinitionsBuilder(G_SEXT_INREG); // RegBankSelect.
auto &SextInReg = getActionDefinitionsBuilder(G_SEXT_INREG)
.legalFor({{S32}, {S64}});
if (ST.hasVOP3PInsts()) { if (ST.hasVOP3PInsts()) {
SextInReg.lowerFor({{S32}, {S64}, {S16}, {V2S16}}) SextInReg.lowerFor({{V2S16}})
// Prefer to reduce vector widths for 16-bit vectors before lowering, to // Prefer to reduce vector widths for 16-bit vectors before lowering, to
// get more vector shift opportunities, since we'll get those when // get more vector shift opportunities, since we'll get those when
// expanded. // expanded.
.fewerElementsIf(elementTypeIs(0, S16), changeTo(0, V2S16)); .fewerElementsIf(elementTypeIs(0, S16), changeTo(0, V2S16));
} else if (ST.has16BitInsts()) { } else if (ST.has16BitInsts()) {
SextInReg.lowerFor({{S32}, {S64}, {S16}}); SextInReg.lowerFor({{S32}, {S64}, {S16}});
} else { } else {
// Prefer to promote to s32 before lowering if we don't have 16-bit // Prefer to promote to s32 before lowering if we don't have 16-bit
// shifts. This avoid a lot of intermediate truncate and extend operations. // shifts. This avoid a lot of intermediate truncate and extend operations.
SextInReg.lowerFor({{S32}, {S64}}); SextInReg.lowerFor({{S32}, {S64}});
} }
SextInReg SextInReg
.scalarize(0) .scalarize(0)
.clampScalar(0, MinLegalScalarShiftTy, S64) .clampScalar(0, S32, S64)
.lower(); .lower();
getActionDefinitionsBuilder(G_READCYCLECOUNTER) getActionDefinitionsBuilder(G_READCYCLECOUNTER)
.legalFor({S64}); .legalFor({S64});
getActionDefinitionsBuilder({ getActionDefinitionsBuilder({
// TODO: Verify V_BFI_B32 is generated from expanded bit ops // TODO: Verify V_BFI_B32 is generated from expanded bit ops
G_FCOPYSIGN, G_FCOPYSIGN,
▲ Show 20 Lines • Show All 1,398 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 1,828 Lines • ▼ Show 20 Lines if (Ty == S16) {
// FIXME: This is relying on widenScalar leaving MI in place. // FIXME: This is relying on widenScalar leaving MI in place.
lowerScalarMinMax(B, MI); lowerScalarMinMax(B, MI);
} else } else
lowerScalarMinMax(B, MI); lowerScalarMinMax(B, MI);
return; return;
} }
case AMDGPU::G_SEXT_INREG: {
const RegisterBank *SrcBank =
OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
// We can directly handle all 64-bit cases with s_bfe_i64.
if (SrcBank == &AMDGPU::SGPRRegBank)
break;
const LLT S32 = LLT::scalar(32);
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
LLT Ty = MRI.getType(DstReg);
if (Ty == S32)
break;
MachineIRBuilder B(MI);
ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank);
GISelObserverWrapper Observer(&O);
B.setChangeObserver(Observer);
int Amt = MI.getOperand(2).getImm();
if (Amt <= 32) {
// Don't use LegalizerHelper's narrowScalar. It produces unwanted G_SEXTs
// we would need to further expand, and doesn't let us directly set the
// result registers.
SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
if (SrcRegs.empty())
split64BitValueForMapping(B, SrcRegs, S32, SrcReg);
// Extend in the low bits and propagate the sign bit to the high half.
auto ShiftAmt = B.buildConstant(S32, 31);
if (Amt == 32) {
B.buildCopy(DstRegs[0], SrcRegs[0]);
B.buildAShr(DstRegs[1], DstRegs[0], ShiftAmt);
} else {
B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt);
B.buildAShr(DstRegs[1], DstRegs[0], ShiftAmt);
}
} else {
assert(empty(OpdMapper.getVRegs(0)) && empty(OpdMapper.getVRegs(1)));
const LLT S64 = LLT::scalar(64);
// This straddles two registers. Expand with 64-bit shifts.
auto ShiftAmt = B.buildConstant(S32, 64 - Amt);
auto Shl = B.buildShl(S64, SrcReg, ShiftAmt);
B.buildAShr(DstReg, Shl, ShiftAmt);
}
MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
MI.eraseFromParent();
return;
}
case AMDGPU::G_SEXT: case AMDGPU::G_SEXT:
case AMDGPU::G_ZEXT: { case AMDGPU::G_ZEXT: {
Register SrcReg = MI.getOperand(1).getReg(); Register SrcReg = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(SrcReg); LLT SrcTy = MRI.getType(SrcReg);
bool Signed = Opc == AMDGPU::G_SEXT; bool Signed = Opc == AMDGPU::G_SEXT;
MachineIRBuilder B(MI); MachineIRBuilder B(MI);
const RegisterBank *SrcBank = const RegisterBank *SrcBank =
▲ Show 20 Lines • Show All 1,083 Lines • ▼ Show 20 Lines if (MI.getOpcode() == AMDGPU::G_ANYEXT) {
// Scalar extend can use 64-bit BFE, but VGPRs require extending to // Scalar extend can use 64-bit BFE, but VGPRs require extending to
// 32-bits, and then to 64. // 32-bits, and then to 64.
OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize); OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);
OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(), OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(),
SrcSize); SrcSize);
} }
break; break;
} }
case AMDGPU::G_SEXT_INREG: {
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
Register Amt = MI.getOperand(2).getImm();
unsigned Size = getSizeInBits(Dst, MRI, *TRI);
unsigned BankID = getRegBank(Src, MRI, *TRI)->getID();
if (Amt <= 32) {
OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(BankID, Size);
} else {
// If we need to expand a 64 bit for the VALU, this will straddle two
// registers. Just expand this with 64-bit shifts.
OpdsMapping[0] = AMDGPU::getValueMapping(BankID, Size);
}
OpdsMapping[1] = OpdsMapping[0];
break;
}
case AMDGPU::G_FCMP: { case AMDGPU::G_FCMP: {
unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI); unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1);
OpdsMapping[1] = nullptr; // Predicate Operand. OpdsMapping[1] = nullptr; // Predicate Operand.
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size); OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
break; break;
▲ Show 20 Lines • Show All 559 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s # RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
# FIXME: Remove -global-isel-abort=0 when G_TRUNC legality handled # FIXME: Remove -global-isel-abort=0 when G_TRUNC legality handled
--- ---
name: test_sext_trunc_v2s32_to_v2s16_to_v2s32 name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s32 ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>) ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_TRUNC %0 %1:_(<2 x s16>) = G_TRUNC %0
%2:_(<2 x s32>) = G_SEXT %1 %2:_(<2 x s32>) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: test_sext_trunc_v2s32_to_v2s16_to_v2s64 name: test_sext_trunc_v2s32_to_v2s16_to_v2s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s64 ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 48 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT1]], 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT_INREG]](s64), [[SEXT_INREG1]](s64)
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT1]], [[COPY2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_TRUNC %0 %1:_(<2 x s16>) = G_TRUNC %0
%2:_(<2 x s64>) = G_SEXT %1 %2:_(<2 x s64>) = G_SEXT %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
... ...
--- ---
name: test_sext_trunc_v2s32_to_v2s8_to_v2s16 name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; The G_SEXT_INREG doesn't lower here because G_TRUNC is both illegal and ; The G_SEXT_INREG doesn't lower here because G_TRUNC is both illegal and
; unable to legalize. This prevents further legalization. ; unable to legalize. This prevents further legalization.
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16 ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>) ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC2]](s16) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC2]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_TRUNC %0 %1:_(<2 x s8>) = G_TRUNC %0
%2:_(<2 x s16>) = G_SEXT %1 %2:_(<2 x s16>) = G_SEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sext_trunc_v3s32_to_v3s16_to_v3s32 name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2 liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: test_sext_trunc_v3s32_to_v3s16_to_v3s32 ; CHECK-LABEL: name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>) ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>) = G_TRUNC %0 %1:_(<3 x s16>) = G_TRUNC %0
%2:_(<3 x s32>) = G_SEXT %1 %2:_(<3 x s32>) = G_SEXT %1
$vgpr0_vgpr1_vgpr2 = COPY %2 $vgpr0_vgpr1_vgpr2 = COPY %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir

Show All 9 Lines bb.0:
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = COPY $vgpr0_vgpr1
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(<2 x s32>) %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(<2 x s32>)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %1(<2 x s32>) %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %1(<2 x s32>)
%6:_(s1) = G_ICMP intpred(ne), %2(s32), %4 %6:_(s1) = G_ICMP intpred(ne), %2(s32), %4
%7:_(s1) = G_ICMP intpred(ne), %3(s32), %5 %7:_(s1) = G_ICMP intpred(ne), %3(s32), %5
%8:_(s32) = G_ANYEXT %6(s1) %8:_(s32) = G_ANYEXT %6(s1)
Show All 19 Lines bb.0:
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = COPY $vgpr0_vgpr1
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(<2 x s32>) %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(<2 x s32>)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %1(<2 x s32>) %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %1(<2 x s32>)
%6:_(s1) = G_ICMP intpred(ne), %2(s32), %4 %6:_(s1) = G_ICMP intpred(ne), %2(s32), %4
%7:_(s1) = G_ICMP intpred(ne), %3(s32), %5 %7:_(s1) = G_ICMP intpred(ne), %3(s32), %5
%8:_(s32) = G_ANYEXT %6(s1) %8:_(s32) = G_ANYEXT %6(s1)
▲ Show 20 Lines • Show All 458 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_sext_trunc_i64_i32_i64 name: test_sext_trunc_i64_i32_i64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_sext_trunc_i64_i32_i64 ; CHECK-LABEL: name: test_sext_trunc_i64_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY2]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0 %1:_(s32) = G_TRUNC %0
%2:_(s64) = G_SEXT %1 %2:_(s64) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: test_zext_trunc_i64_i32_i64 name: test_zext_trunc_i64_i32_i64
Show All 15 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_ashr_s16_s32 ; SI-LABEL: name: test_ashr_s16_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY3]](s32) ; SI: $vgpr0 = COPY [[COPY3]](s32)
; VI-LABEL: name: test_ashr_s16_s32 ; VI-LABEL: name: test_ashr_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
Show All 20 Lines bb.0:
; SI-LABEL: name: test_ashr_s16_s16 ; SI-LABEL: name: test_ashr_s16_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_ashr_s16_s16 ; VI-LABEL: name: test_ashr_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
Show All 23 Lines bb.0:
; SI-LABEL: name: test_ashr_s16_i8 ; SI-LABEL: name: test_ashr_s16_i8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_ashr_s16_i8 ; VI-LABEL: name: test_ashr_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
Show All 27 Lines bb.0:
; SI-LABEL: name: test_ashr_i8_i8 ; SI-LABEL: name: test_ashr_i8_i8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_ashr_i8_i8 ; VI-LABEL: name: test_ashr_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16) ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C1]](s16) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C1]](s16)
; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s32) ; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_ashr_i8_i8 ; GFX9-LABEL: name: test_ashr_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C1]](s16) ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s32) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_ASHR %2, %3 %4:_(s8) = G_ASHR %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
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; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR2]], [[AND1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR3]](s32)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; VI-LABEL: name: test_ashr_v2s16_v2s16 ; VI-LABEL: name: test_ashr_v2s16_v2s16
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; SI-LABEL: name: test_ashr_v2s16_v2s32 ; SI-LABEL: name: test_ashr_v2s16_v2s32
; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[UV]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[UV]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[UV1]](s32)
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR2]], [[UV1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR3]](s32)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; VI-LABEL: name: test_ashr_v2s16_v2s32 ; VI-LABEL: name: test_ashr_v2s16_v2s32
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines bb.0:
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) ; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR2]], [[AND1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR3]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]] ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32) ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; SI: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) ; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
; SI: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[ASHR4]], [[AND2]](s32) ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR2]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR5]](s32)
; SI: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF ; SI: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF2]](s16) ; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF2]](s16)
; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>) ; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; SI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0 ; SI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; SI: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; SI: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; SI: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT2]](<3 x s16>), 0 ; SI: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT2]](<3 x s16>), 0
; SI: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>) ; SI: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines bb.0:
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) ; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR2]], [[AND1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR3]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]] ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32) ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; SI: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) ; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
; SI: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[ASHR4]], [[AND2]](s32) ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR2]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR5]](s32)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32) ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]] ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32) ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
; SI: [[ASHR6:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[AND3]](s32)
; SI: [[ASHR7:%[0-9]+]]:_(s32) = G_ASHR [[ASHR6]], [[AND3]](s32) ; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR7]](s32)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16) ; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>) ; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; SI: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) ; SI: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; VI-LABEL: name: test_ashr_v4s16_v4s16 ; VI-LABEL: name: test_ashr_v4s16_v4s16
; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) ; VI: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir

Show First 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32 ; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>) ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0 ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(<2 x s8>) = G_IMPLICIT_DEF %0:_(<2 x s8>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0 %1:_(s32) = G_CONSTANT i32 0
%2:_(s8) = G_EXTRACT_VECTOR_ELT %0, %1 %2:_(s8) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
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body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32 ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>) ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0 ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF %0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0 %1:_(s32) = G_CONSTANT i32 0
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1 %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: extract_vector_elt_0_v2i1_i1 name: extract_vector_elt_0_v2i1_i1
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1 ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>) ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C1]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C1]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF %0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s1) = G_CONSTANT i1 false %1:_(s1) = G_CONSTANT i1 false
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1 %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: extract_vector_elt_v2s8_varidx_i32 name: extract_vector_elt_v2s8_varidx_i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2 liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: extract_vector_elt_v2s8_varidx_i32 ; CHECK-LABEL: name: extract_vector_elt_v2s8_varidx_i32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>) ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[COPY1]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32) ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2 %1:_(s32) = COPY $vgpr2
%2:_(<2 x s8>) = G_TRUNC %0 %2:_(<2 x s8>) = G_TRUNC %0
%3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1 %3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...
--- ---
name: extract_vector_elt_v3s8_varidx_i32 name: extract_vector_elt_v3s8_varidx_i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3 liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; CHECK-LABEL: name: extract_vector_elt_v3s8_varidx_i32 ; CHECK-LABEL: name: extract_vector_elt_v3s8_varidx_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>) ; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 8
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32) ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3 %1:_(s32) = COPY $vgpr3
%2:_(<3 x s8>) = G_TRUNC %0 %2:_(<3 x s8>) = G_TRUNC %0
%3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1 %3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...
--- ---
name: extract_vector_elt_v4s8_varidx_i32 name: extract_vector_elt_v4s8_varidx_i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; CHECK-LABEL: name: extract_vector_elt_v4s8_varidx_i32 ; CHECK-LABEL: name: extract_vector_elt_v4s8_varidx_i32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY [[COPY]](<4 x s32>) ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY [[COPY]](<4 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 8
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 8
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[UV3]], [[C]](s32)
; CHECK: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32), [[ASHR3]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32) ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4 %1:_(s32) = COPY $vgpr4
%2:_(<4 x s8>) = G_TRUNC %0 %2:_(<4 x s8>) = G_TRUNC %0
%3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1 %3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3 liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; CHECK-LABEL: name: extract_vector_elt_v3s16_varidx_i32 ; CHECK-LABEL: name: extract_vector_elt_v3s16_varidx_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>) ; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32) ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3 %1:_(s32) = COPY $vgpr3
%2:_(<3 x s16>) = G_TRUNC %0 %2:_(<3 x s16>) = G_TRUNC %0
%3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1 %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...
--- ---
name: extract_vector_elt_v3s16_idx0_i32 name: extract_vector_elt_v3s16_idx0_i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2 liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx0_i32 ; CHECK-LABEL: name: extract_vector_elt_v3s16_idx0_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>) ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 0 ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 0
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32) ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 0 %1:_(s32) = G_CONSTANT i32 0
%2:_(<3 x s16>) = G_TRUNC %0 %2:_(<3 x s16>) = G_TRUNC %0
%3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1 %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...
--- ---
name: extract_vector_elt_v3s16_idx1_i32 name: extract_vector_elt_v3s16_idx1_i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2 liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx1_i32 ; CHECK-LABEL: name: extract_vector_elt_v3s16_idx1_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>) ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 32 ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 32
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32) ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 1 %1:_(s32) = G_CONSTANT i32 1
%2:_(<3 x s16>) = G_TRUNC %0 %2:_(<3 x s16>) = G_TRUNC %0
%3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1 %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...
--- ---
name: extract_vector_elt_v3s16_idx2_i32 name: extract_vector_elt_v3s16_idx2_i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2 liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx2_i32 ; CHECK-LABEL: name: extract_vector_elt_v3s16_idx2_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>) ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64 ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32) ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 2 %1:_(s32) = G_CONSTANT i32 2
%2:_(<3 x s16>) = G_TRUNC %0 %2:_(<3 x s16>) = G_TRUNC %0
%3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1 %3:_(s16) = G_EXTRACT_VECTOR_ELT %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir

Show First 20 Lines • Show All 604 Lines • ▼ Show 20 Lines bb.0:
; GFX7: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 ; GFX7: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX7: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>) ; GFX7: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; GFX7: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>) ; GFX7: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]] ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]] ; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1) ; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1) ; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX7: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32) ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX7: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2p3 ; GFX8-LABEL: name: test_icmp_v2p3
; GFX8: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX8: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>) ; GFX8: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; GFX8: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>) ; GFX8: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]] ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]] ; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1) ; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2p3 ; GFX9-LABEL: name: test_icmp_v2p3
; GFX9: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1
; GFX9: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>) ; GFX9: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>)
; GFX9: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>) ; GFX9: [[UV2:%[0-9]+]]:_(p3), [[UV3:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]] ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[UV2]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]] ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1) ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x p3>) = COPY $vgpr0_vgpr1 %0:_(<2 x p3>) = COPY $vgpr0_vgpr1
%1:_(<2 x p3>) = COPY $vgpr0_vgpr1 %1:_(<2 x p3>) = COPY $vgpr0_vgpr1
%2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1 %2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%3:_(<2 x s32>) = G_SEXT %2 %3:_(<2 x s32>) = G_SEXT %2
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...
--- ---
name: test_icmp_v2p999 name: test_icmp_v2p999
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
; GFX7-LABEL: name: test_icmp_v2p999 ; GFX7-LABEL: name: test_icmp_v2p999
; GFX7: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX7: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX7: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 ; GFX7: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; GFX7: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>) ; GFX7: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>)
; GFX7: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>) ; GFX7: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>)
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]] ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]] ; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1) ; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1) ; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX7: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32) ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX7: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2p999 ; GFX8-LABEL: name: test_icmp_v2p999
; GFX8: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX8: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; GFX8: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>) ; GFX8: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>)
; GFX8: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>) ; GFX8: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]] ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]] ; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1) ; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2p999 ; GFX9-LABEL: name: test_icmp_v2p999
; GFX9: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
; GFX9: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>) ; GFX9: [[UV:%[0-9]+]]:_(p999), [[UV1:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY]](<2 x p999>)
; GFX9: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>) ; GFX9: [[UV2:%[0-9]+]]:_(p999), [[UV3:%[0-9]+]]:_(p999) = G_UNMERGE_VALUES [[COPY1]](<2 x p999>)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]] ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p999), [[UV2]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]] ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1) ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(<2 x p999>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 %1:_(<2 x p999>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
%2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1 %2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
%3:_(<2 x s32>) = G_SEXT %2 %3:_(<2 x s32>) = G_SEXT %2
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2 liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: insert_vector_elt_0_v2s32_s8 ; CHECK-LABEL: name: insert_vector_elt_0_v2s32_s8
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32) ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[SEXT_INREG]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[ASHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[IVEC]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[IVEC]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2 %1:_(s32) = COPY $vgpr2
%2:_(s8) = G_CONSTANT i8 0 %2:_(s8) = G_CONSTANT i8 0
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...
Show All 23 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir

Show All 9 Lines bb.0:
; CHECK-LABEL: name: test_saddo_s16 ; CHECK-LABEL: name: test_saddo_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C1]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C1]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C1]](s32)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ASHR2]](s32), [[SEXT]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]] ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK: $vgpr0 = COPY [[COPY7]](s32) ; CHECK: $vgpr0 = COPY [[COPY7]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir

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body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: test_sdiv_s16 ; GFX6-LABEL: name: test_sdiv_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32) ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: test_sdiv_s16 ; GFX8-LABEL: name: test_sdiv_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX8: $vgpr0 = COPY [[COPY4]](s32) ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
; GFX9-LABEL: name: test_sdiv_s16 ; GFX9-LABEL: name: test_sdiv_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32) ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_SDIV %2, %3 %4:_(s16) = G_SDIV %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
Show All 10 Lines bb.0:
; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV]](s32) ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; GFX6: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[ASHR2]], [[ASHR3]]
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV1]](s32) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV1]](s32)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX6: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; GFX6: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX8-LABEL: name: test_sdiv_v2s16 ; GFX8-LABEL: name: test_sdiv_v2s16
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV]](s32) ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV]](s32)
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX8: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX8: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX8: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; GFX8: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX8: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[ASHR2]], [[ASHR3]]
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV1]](s32) ; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV1]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX8: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; GFX8: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX9-LABEL: name: test_sdiv_v2s16 ; GFX9-LABEL: name: test_sdiv_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX9: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX9: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; GFX9: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX9: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[ASHR2]], [[ASHR3]]
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV1]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SDIV1]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1 %1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_SDIV %0, %1 %2:_(<2 x s16>) = G_SDIV %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sdiv_s7 name: test_sdiv_s7
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: test_sdiv_s7 ; GFX6-LABEL: name: test_sdiv_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32) ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: test_sdiv_s7 ; GFX8-LABEL: name: test_sdiv_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX8: $vgpr0 = COPY [[COPY4]](s32) ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
; GFX9-LABEL: name: test_sdiv_s7 ; GFX9-LABEL: name: test_sdiv_s7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32) ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
%4:_(s7) = G_SDIV %2, %3 %4:_(s7) = G_SDIV %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
... ...
--- ---
name: test_sdiv_s17 name: test_sdiv_s17
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: test_sdiv_s17 ; GFX6-LABEL: name: test_sdiv_s17
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32) ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: test_sdiv_s17 ; GFX8-LABEL: name: test_sdiv_s17
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX8: $vgpr0 = COPY [[COPY4]](s32) ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
; GFX9-LABEL: name: test_sdiv_s17 ; GFX9-LABEL: name: test_sdiv_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32) ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0 %2:_(s17) = G_TRUNC %0
%3:_(s17) = G_TRUNC %1 %3:_(s17) = G_TRUNC %1
%4:_(s17) = G_SDIV %2, %3 %4:_(s17) = G_SDIV %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
... ...
--- ---
name: test_sdiv_s33 name: test_sdiv_s33
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX6-LABEL: name: test_sdiv_s33 ; GFX6-LABEL: name: test_sdiv_s33
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[COPY3]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY4]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SDIV]](s64)
; GFX6: [[COPY5:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; GFX6: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; GFX6: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY5]], [[C]](s32)
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY6]](s32)
; GFX6: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX6: [[COPY7:%[0-9]+]]:_(s64) = COPY [[SDIV]](s64)
; GFX6: $vgpr0_vgpr1 = COPY [[COPY7]](s64)
; GFX8-LABEL: name: test_sdiv_s33 ; GFX8-LABEL: name: test_sdiv_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[COPY3]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY4]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SDIV]](s64)
; GFX8: [[COPY5:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; GFX8: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; GFX8: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY5]], [[C]](s32)
; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY6]](s32)
; GFX8: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX8: [[COPY7:%[0-9]+]]:_(s64) = COPY [[SDIV]](s64)
; GFX8: $vgpr0_vgpr1 = COPY [[COPY7]](s64)
; GFX9-LABEL: name: test_sdiv_s33 ; GFX9-LABEL: name: test_sdiv_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[COPY3]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY4]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SDIV]](s64)
; GFX9: [[COPY5:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; GFX9: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY5]], [[C]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY6]](s32)
; GFX9: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
; GFX9: [[COPY7:%[0-9]+]]:_(s64) = COPY [[SDIV]](s64)
; GFX9: $vgpr0_vgpr1 = COPY [[COPY7]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s33) = G_TRUNC %0 %2:_(s33) = G_TRUNC %0
%3:_(s33) = G_TRUNC %1 %3:_(s33) = G_TRUNC %1
%4:_(s33) = G_SDIV %2, %3 %4:_(s33) = G_SDIV %2, %3
%5:_(s64) = G_ANYEXT %4 %5:_(s64) = G_ANYEXT %4
$vgpr0_vgpr1 = COPY %5 $vgpr0_vgpr1 = COPY %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s # RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s
# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX8 %s # RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX8 %s
# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX6 %s # RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX6 %s
--- ---
name: test_sext_inreg_s32_1 name: test_sext_inreg_s32_1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX9-LABEL: name: test_sext_inreg_s32_1 ; GFX9-LABEL: name: test_sext_inreg_s32_1
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: test_sext_inreg_s32_1 ; GFX8-LABEL: name: test_sext_inreg_s32_1
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: $vgpr0 = COPY [[ASHR]](s32)
; GFX6-LABEL: name: test_sext_inreg_s32_1 ; GFX6-LABEL: name: test_sext_inreg_s32_1
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_SEXT_INREG %0, 1 %1:_(s32) = G_SEXT_INREG %0, 1
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_sext_inreg_s32_2 name: test_sext_inreg_s32_2
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX9-LABEL: name: test_sext_inreg_s32_2 ; GFX9-LABEL: name: test_sext_inreg_s32_2
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 30 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 2
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: test_sext_inreg_s32_2 ; GFX8-LABEL: name: test_sext_inreg_s32_2
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 30 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 2
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: $vgpr0 = COPY [[ASHR]](s32)
; GFX6-LABEL: name: test_sext_inreg_s32_2 ; GFX6-LABEL: name: test_sext_inreg_s32_2
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 30 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 2
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_SEXT_INREG %0, 2 %1:_(s32) = G_SEXT_INREG %0, 2
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_sext_inreg_s32_8 name: test_sext_inreg_s32_8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX9-LABEL: name: test_sext_inreg_s32_8 ; GFX9-LABEL: name: test_sext_inreg_s32_8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: test_sext_inreg_s32_8 ; GFX8-LABEL: name: test_sext_inreg_s32_8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: $vgpr0 = COPY [[ASHR]](s32)
; GFX6-LABEL: name: test_sext_inreg_s32_8 ; GFX6-LABEL: name: test_sext_inreg_s32_8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_SEXT_INREG %0, 8 %1:_(s32) = G_SEXT_INREG %0, 8
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_sext_inreg_s32_16 name: test_sext_inreg_s32_16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX9-LABEL: name: test_sext_inreg_s32_16 ; GFX9-LABEL: name: test_sext_inreg_s32_16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: test_sext_inreg_s32_16 ; GFX8-LABEL: name: test_sext_inreg_s32_16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: $vgpr0 = COPY [[ASHR]](s32)
; GFX6-LABEL: name: test_sext_inreg_s32_16 ; GFX6-LABEL: name: test_sext_inreg_s32_16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_SEXT_INREG %0, 8 %1:_(s32) = G_SEXT_INREG %0, 8
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_sext_inreg_s32_31 name: test_sext_inreg_s32_31
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX9-LABEL: name: test_sext_inreg_s32_31 ; GFX9-LABEL: name: test_sext_inreg_s32_31
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 31
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: test_sext_inreg_s32_31 ; GFX8-LABEL: name: test_sext_inreg_s32_31
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 31
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: $vgpr0 = COPY [[ASHR]](s32)
; GFX6-LABEL: name: test_sext_inreg_s32_31 ; GFX6-LABEL: name: test_sext_inreg_s32_31
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 31
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0 = COPY [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_SEXT_INREG %0, 31 %1:_(s32) = G_SEXT_INREG %0, 31
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_sext_inreg_s64_1 name: test_sext_inreg_s64_1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_s64_1 ; GFX9-LABEL: name: test_sext_inreg_s64_1
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 1
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX8-LABEL: name: test_sext_inreg_s64_1 ; GFX8-LABEL: name: test_sext_inreg_s64_1
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 1
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX6-LABEL: name: test_sext_inreg_s64_1 ; GFX6-LABEL: name: test_sext_inreg_s64_1
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 1 %1:_(s64) = G_SEXT_INREG %0, 1
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_s64_2 name: test_sext_inreg_s64_2
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_s64_2 ; GFX9-LABEL: name: test_sext_inreg_s64_2
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 62 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 2
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX8-LABEL: name: test_sext_inreg_s64_2 ; GFX8-LABEL: name: test_sext_inreg_s64_2
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 62 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 2
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX6-LABEL: name: test_sext_inreg_s64_2 ; GFX6-LABEL: name: test_sext_inreg_s64_2
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 62 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 2
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 2 %1:_(s64) = G_SEXT_INREG %0, 2
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_s64_8 name: test_sext_inreg_s64_8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_s64_8 ; GFX9-LABEL: name: test_sext_inreg_s64_8
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX8-LABEL: name: test_sext_inreg_s64_8 ; GFX8-LABEL: name: test_sext_inreg_s64_8
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX6-LABEL: name: test_sext_inreg_s64_8 ; GFX6-LABEL: name: test_sext_inreg_s64_8
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 8 %1:_(s64) = G_SEXT_INREG %0, 8
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_s64_16 name: test_sext_inreg_s64_16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_s64_16 ; GFX9-LABEL: name: test_sext_inreg_s64_16
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX8-LABEL: name: test_sext_inreg_s64_16 ; GFX8-LABEL: name: test_sext_inreg_s64_16
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX6-LABEL: name: test_sext_inreg_s64_16 ; GFX6-LABEL: name: test_sext_inreg_s64_16
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 8 %1:_(s64) = G_SEXT_INREG %0, 8
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_s64_31 name: test_sext_inreg_s64_31
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_s64_31 ; GFX9-LABEL: name: test_sext_inreg_s64_31
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 31
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX8-LABEL: name: test_sext_inreg_s64_31 ; GFX8-LABEL: name: test_sext_inreg_s64_31
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 31
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX6-LABEL: name: test_sext_inreg_s64_31 ; GFX6-LABEL: name: test_sext_inreg_s64_31
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 31
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 31 %1:_(s64) = G_SEXT_INREG %0, 31
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_s64_32 name: test_sext_inreg_s64_32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_s64_32 ; GFX9-LABEL: name: test_sext_inreg_s64_32
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX8-LABEL: name: test_sext_inreg_s64_32 ; GFX8-LABEL: name: test_sext_inreg_s64_32
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX6-LABEL: name: test_sext_inreg_s64_32 ; GFX6-LABEL: name: test_sext_inreg_s64_32
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 32 %1:_(s64) = G_SEXT_INREG %0, 32
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_s64_33 name: test_sext_inreg_s64_33
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_s64_33 ; GFX9-LABEL: name: test_sext_inreg_s64_33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX8-LABEL: name: test_sext_inreg_s64_33 ; GFX8-LABEL: name: test_sext_inreg_s64_33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX6-LABEL: name: test_sext_inreg_s64_33 ; GFX6-LABEL: name: test_sext_inreg_s64_33
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 33 %1:_(s64) = G_SEXT_INREG %0, 33
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_s64_63 name: test_sext_inreg_s64_63
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_s64_63 ; GFX9-LABEL: name: test_sext_inreg_s64_63
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 63
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX8-LABEL: name: test_sext_inreg_s64_63 ; GFX8-LABEL: name: test_sext_inreg_s64_63
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 63
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX6-LABEL: name: test_sext_inreg_s64_63 ; GFX6-LABEL: name: test_sext_inreg_s64_63
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 63
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32) ; GFX6: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 63 %1:_(s64) = G_SEXT_INREG %0, 63
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_s16_1 name: test_sext_inreg_s16_1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX9-LABEL: name: test_sext_inreg_s16_1 ; GFX9-LABEL: name: test_sext_inreg_s16_1
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16) ; GFX9: S_ENDPGM 0, implicit [[TRUNC]](s16)
; GFX9: S_ENDPGM 0, implicit [[ASHR]](s16)
; GFX8-LABEL: name: test_sext_inreg_s16_1 ; GFX8-LABEL: name: test_sext_inreg_s16_1
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15 ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16) ; GFX8: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16) ; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16)
; GFX6-LABEL: name: test_sext_inreg_s16_1 ; GFX6-LABEL: name: test_sext_inreg_s16_1
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16) ; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_SEXT_INREG %1, 1 %2:_(s16) = G_SEXT_INREG %1, 1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: test_sext_inreg_s16_15 name: test_sext_inreg_s16_15
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX9-LABEL: name: test_sext_inreg_s16_15 ; GFX9-LABEL: name: test_sext_inreg_s16_15
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 15
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16) ; GFX9: S_ENDPGM 0, implicit [[TRUNC]](s16)
; GFX9: S_ENDPGM 0, implicit [[ASHR]](s16)
; GFX8-LABEL: name: test_sext_inreg_s16_15 ; GFX8-LABEL: name: test_sext_inreg_s16_15
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16) ; GFX8: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16) ; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16)
; GFX6-LABEL: name: test_sext_inreg_s16_15 ; GFX6-LABEL: name: test_sext_inreg_s16_15
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 15
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16) ; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_SEXT_INREG %1, 15 %2:_(s16) = G_SEXT_INREG %1, 15
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: test_sext_inreg_s96_8 name: test_sext_inreg_s96_8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2 liveins: $vgpr0_vgpr1_vgpr2
; GFX9-LABEL: name: test_sext_inreg_s96_8 ; GFX9-LABEL: name: test_sext_inreg_s96_8
; GFX9: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 ; GFX9: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96) ; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32) ; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX9: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR1]](s32) ; GFX9: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
; GFX9: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64) ; GFX9: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s192) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s192)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96) ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
; GFX8-LABEL: name: test_sext_inreg_s96_8 ; GFX8-LABEL: name: test_sext_inreg_s96_8
; GFX8: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 ; GFX8: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96) ; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
; GFX8: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32) ; GFX8: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX8: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR1]](s32) ; GFX8: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
; GFX8: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64) ; GFX8: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s192) ; GFX8: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s192)
; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96) ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
; GFX6-LABEL: name: test_sext_inreg_s96_8 ; GFX6-LABEL: name: test_sext_inreg_s96_8
; GFX6: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2 ; GFX6: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96) ; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s96)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
; GFX6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32) ; GFX6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX6: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR1]](s32) ; GFX6: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
; GFX6: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64) ; GFX6: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s192) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s192)
; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96) ; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC1]](s96)
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2 %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s96) = G_SEXT_INREG %0, 8 %1:_(s96) = G_SEXT_INREG %0, 8
$vgpr0_vgpr1_vgpr2 = COPY %1 $vgpr0_vgpr1_vgpr2 = COPY %1
... ...
--- ---
name: test_sext_inreg_s128_8 name: test_sext_inreg_s128_8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3 liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-LABEL: name: test_sext_inreg_s128_8 ; GFX9-LABEL: name: test_sext_inreg_s128_8
; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) ; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX8-LABEL: name: test_sext_inreg_s128_8 ; GFX8-LABEL: name: test_sext_inreg_s128_8
; GFX8: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX8: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) ; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX8: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX8: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
; GFX6-LABEL: name: test_sext_inreg_s128_8 ; GFX6-LABEL: name: test_sext_inreg_s128_8
; GFX6: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX6: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) ; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX6: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX6: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128) ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s128) = G_SEXT_INREG %0, 8 %1:_(s128) = G_SEXT_INREG %0, 8
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
... ...
--- ---
name: test_sext_inreg_s160_8 name: test_sext_inreg_s160_8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
; GFX9-LABEL: name: test_sext_inreg_s160_8 ; GFX9-LABEL: name: test_sext_inreg_s160_8
; GFX9: [[COPY:%[0-9]+]]:_(s160) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; GFX9: [[COPY:%[0-9]+]]:_(s160) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s160) ; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s160)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT_INREG]](s64)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32) ; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX9: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR1]](s32) ; GFX9: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
; GFX9: [[MV2:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64) ; GFX9: [[MV2:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s160) = G_TRUNC [[MV2]](s320) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s160) = G_TRUNC [[MV2]](s320)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[TRUNC1]](s160) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[TRUNC1]](s160)
; GFX8-LABEL: name: test_sext_inreg_s160_8 ; GFX8-LABEL: name: test_sext_inreg_s160_8
; GFX8: [[COPY:%[0-9]+]]:_(s160) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; GFX8: [[COPY:%[0-9]+]]:_(s160) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s160) ; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s160)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT_INREG]](s64)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
; GFX8: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32) ; GFX8: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX8: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR1]](s32) ; GFX8: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
; GFX8: [[MV2:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64) ; GFX8: [[MV2:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s160) = G_TRUNC [[MV2]](s320) ; GFX8: [[TRUNC1:%[0-9]+]]:_(s160) = G_TRUNC [[MV2]](s320)
; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[TRUNC1]](s160) ; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[TRUNC1]](s160)
; GFX6-LABEL: name: test_sext_inreg_s160_8 ; GFX6-LABEL: name: test_sext_inreg_s160_8
; GFX6: [[COPY:%[0-9]+]]:_(s160) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; GFX6: [[COPY:%[0-9]+]]:_(s160) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s160) ; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s160)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT_INREG]](s64)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
; GFX6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32) ; GFX6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; GFX6: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR1]](s32) ; GFX6: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
; GFX6: [[MV2:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64) ; GFX6: [[MV2:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s160) = G_TRUNC [[MV2]](s320) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s160) = G_TRUNC [[MV2]](s320)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[TRUNC1]](s160) ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[TRUNC1]](s160)
%0:_(s160) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 %0:_(s160) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
%1:_(s160) = G_SEXT_INREG %0, 8 %1:_(s160) = G_SEXT_INREG %0, 8
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY %1
... ...
--- ---
name: test_sext_inreg_256_8 name: test_sext_inreg_256_8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-LABEL: name: test_sext_inreg_256_8 ; GFX9-LABEL: name: test_sext_inreg_256_8
; GFX9: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX9: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s256) ; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s256)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX9: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
; GFX8-LABEL: name: test_sext_inreg_256_8 ; GFX8-LABEL: name: test_sext_inreg_256_8
; GFX8: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s256) ; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s256)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX8: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX8: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256) ; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
; GFX6-LABEL: name: test_sext_inreg_256_8 ; GFX6-LABEL: name: test_sext_inreg_256_8
; GFX6: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX6: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s256) ; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s256)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX6: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX6: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256) ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[MV]](s256)
%0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(s256) = G_SEXT_INREG %0, 8 %1:_(s256) = G_SEXT_INREG %0, 8
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
... ...
--- ---
name: test_sext_inreg_512_8 name: test_sext_inreg_512_8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9-LABEL: name: test_sext_inreg_512_8 ; GFX9-LABEL: name: test_sext_inreg_512_8
; GFX9: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX9: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512) ; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX9: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512)
; GFX8-LABEL: name: test_sext_inreg_512_8 ; GFX8-LABEL: name: test_sext_inreg_512_8
; GFX8: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512) ; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX8: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX8: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512) ; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512)
; GFX6-LABEL: name: test_sext_inreg_512_8 ; GFX6-LABEL: name: test_sext_inreg_512_8
; GFX6: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX6: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512) ; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX6: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX6: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512) ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512)
%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%1:_(s512) = G_SEXT_INREG %0, 8 %1:_(s512) = G_SEXT_INREG %0, 8
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1
... ...
--- ---
name: test_sext_inreg_1024_8 name: test_sext_inreg_1024_8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-LABEL: name: test_sext_inreg_1024_8 ; GFX9-LABEL: name: test_sext_inreg_1024_8
; GFX9: [[COPY:%[0-9]+]]:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9: [[COPY:%[0-9]+]]:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s1024) ; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s1024)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX9: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024)
; GFX8-LABEL: name: test_sext_inreg_1024_8 ; GFX8-LABEL: name: test_sext_inreg_1024_8
; GFX8: [[COPY:%[0-9]+]]:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX8: [[COPY:%[0-9]+]]:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s1024) ; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s1024)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX8: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX8: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024) ; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024)
; GFX6-LABEL: name: test_sext_inreg_1024_8 ; GFX6-LABEL: name: test_sext_inreg_1024_8
; GFX6: [[COPY:%[0-9]+]]:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX6: [[COPY:%[0-9]+]]:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s1024) ; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s1024)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32) ; GFX6: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C1]](s32)
; GFX6: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64), [[ASHR1]](s64)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024) ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[MV]](s1024)
%0:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 %0:_(s1024) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
%1:_(s1024) = G_SEXT_INREG %0, 8 %1:_(s1024) = G_SEXT_INREG %0, 8
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY %1
... ...
--- ---
name: test_sext_inreg_v2s32_1 name: test_sext_inreg_v2s32_1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX9-LABEL: name: test_sext_inreg_v2s32_1 ; GFX9-LABEL: name: test_sext_inreg_v2s32_1
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_sext_inreg_v2s32_1 ; GFX8-LABEL: name: test_sext_inreg_v2s32_1
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX6-LABEL: name: test_sext_inreg_v2s32_1 ; GFX6-LABEL: name: test_sext_inreg_v2s32_1
; GFX6: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX6: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = G_SEXT_INREG %0, 1 %1:_(<2 x s32>) = G_SEXT_INREG %0, 1
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_inreg_v2s16_1 name: test_sext_inreg_v2s16_1
Show All 23 Lines bb.0:
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[ASHR]](s16), [[ASHR1]](s16) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[ASHR]](s16), [[ASHR1]](s16)
; GFX8: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; GFX8: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX6-LABEL: name: test_sext_inreg_v2s16_1 ; GFX6-LABEL: name: test_sext_inreg_v2s16_1
; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32) ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX6: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; GFX6: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = G_SEXT_INREG %0, 1 %1:_(<2 x s16>) = G_SEXT_INREG %0, 1
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
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; GFX6: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0 ; GFX6: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; GFX6: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>) ; GFX6: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) ; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) ; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32) ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s32) ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C1]](s32) ; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG2]](s32)
; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR2]](s32)
; GFX6: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF ; GFX6: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX6: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF1]](s16) ; GFX6: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF1]](s16)
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>) ; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX6: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0 ; GFX6: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[COPY]], [[EXTRACT1]](<3 x s16>), 0 ; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[COPY]], [[EXTRACT1]](<3 x s16>), 0
; GFX6: $vgpr0_vgpr1 = COPY [[INSERT1]](<4 x s16>) ; GFX6: $vgpr0_vgpr1 = COPY [[INSERT1]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<3 x s16>) = G_EXTRACT %0, 0 %1:_(<3 x s16>) = G_EXTRACT %0, 0
%2:_(<3 x s16>) = G_SEXT_INREG %1, 1 %2:_(<3 x s16>) = G_SEXT_INREG %1, 1
%3:_(<4 x s16>) = G_INSERT %0, %2, 0 %3:_(<4 x s16>) = G_INSERT %0, %2, 0
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...
--- ---
name: test_sext_inreg_v3s32_1 name: test_sext_inreg_v3s32_1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2 liveins: $vgpr0_vgpr1_vgpr2
; GFX9-LABEL: name: test_sext_inreg_v3s32_1 ; GFX9-LABEL: name: test_sext_inreg_v3s32_1
; GFX9: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; GFX9: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; GFX9: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
; GFX8-LABEL: name: test_sext_inreg_v3s32_1 ; GFX8-LABEL: name: test_sext_inreg_v3s32_1
; GFX8: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; GFX8: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; GFX8: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
; GFX6-LABEL: name: test_sext_inreg_v3s32_1 ; GFX6-LABEL: name: test_sext_inreg_v3s32_1
; GFX6: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 ; GFX6: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = G_SEXT_INREG %0, 1 %1:_(<3 x s32>) = G_SEXT_INREG %0, 1
$vgpr0_vgpr1_vgpr2 = COPY %1 $vgpr0_vgpr1_vgpr2 = COPY %1
... ...
--- ---
name: test_sext_inreg_v4s32_1 name: test_sext_inreg_v4s32_1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3 liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9-LABEL: name: test_sext_inreg_v4s32_1 ; GFX9-LABEL: name: test_sext_inreg_v4s32_1
; GFX9: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 1
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; GFX9: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[UV3]], [[C]](s32)
; GFX9: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32), [[ASHR3]](s32)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
; GFX8-LABEL: name: test_sext_inreg_v4s32_1 ; GFX8-LABEL: name: test_sext_inreg_v4s32_1
; GFX8: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX8: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 1
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; GFX8: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX8: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[UV3]], [[C]](s32)
; GFX8: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32), [[ASHR3]](s32)
; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>) ; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
; GFX6-LABEL: name: test_sext_inreg_v4s32_1 ; GFX6-LABEL: name: test_sext_inreg_v4s32_1
; GFX6: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX6: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[C]](s32) ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 1
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[C]](s32)
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[UV3]], [[C]](s32)
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32), [[ASHR3]](s32)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>) ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<4 x s32>) = G_SEXT_INREG %0, 1 %1:_(<4 x s32>) = G_SEXT_INREG %0, 1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
... ...
--- ---
name: test_sext_inreg_v4s16_1 name: test_sext_inreg_v4s16_1
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; GFX6: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; GFX6: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) ; GFX6: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) ; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) ; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32) ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s32) ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C1]](s32) ; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG2]](s32)
; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR2]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32) ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C1]](s32) ; GFX6: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG3]](s32)
; GFX6: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR3]](s32)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX6: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16) ; GFX6: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>) ; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) ; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = G_SEXT_INREG %0, 1 %1:_(<4 x s16>) = G_SEXT_INREG %0, 1
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
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; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) ; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) ; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32) ; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32) ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C1]](s32) ; GFX6: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG2]](s32)
; GFX6: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR2]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s32) ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C1]](s32) ; GFX6: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG3]](s32)
; GFX6: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR3]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32) ; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1
; GFX6: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL4]], [[C1]](s32) ; GFX6: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG4]](s32)
; GFX6: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR4]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C1]](s32) ; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 1
; GFX6: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[C1]](s32) ; GFX6: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG5]](s32)
; GFX6: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR5]](s32)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC2]](s16) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC2]](s16)
; GFX6: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](s16), [[TRUNC4]](s16) ; GFX6: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](s16), [[TRUNC4]](s16)
; GFX6: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](s16), [[TRUNC6]](s16) ; GFX6: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC5]](s16), [[TRUNC6]](s16)
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>) ; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>), [[BUILD_VECTOR2]](<2 x s16>)
; GFX6: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>) ; GFX6: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = G_IMPLICIT_DEF %0:_(<6 x s16>) = G_IMPLICIT_DEF
%1:_(<6 x s16>) = G_SEXT_INREG %0, 1 %1:_(<6 x s16>) = G_SEXT_INREG %0, 1
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
# FIXME: Should scalarize first # FIXME: Should scalarize first
--- ---
name: test_sext_inreg_v2s128_1 name: test_sext_inreg_v2s128_1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9-LABEL: name: test_sext_inreg_v2s128_1 ; GFX9-LABEL: name: test_sext_inreg_v2s128_1
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX9: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>) ; GFX9: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[UV]](s128) ; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[UV]](s128)
; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[COPY2]](s32)
; GFX9: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[UV1]](s128) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[UV1]](s128)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC1]], 1
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[TRUNC1]], [[COPY3]](s32) ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[COPY1]](s32)
; GFX9: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY4]](s32) ; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG1]](s64), [[ASHR1]](s64)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[ASHR2]], [[COPY5]](s32)
; GFX9: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR2]](s64), [[ASHR3]](s64)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
; GFX8-LABEL: name: test_sext_inreg_v2s128_1 ; GFX8-LABEL: name: test_sext_inreg_v2s128_1
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX8: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>) ; GFX8: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[UV]](s128) ; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[UV]](s128)
; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64)
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[COPY2]](s32)
; GFX8: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[UV1]](s128) ; GFX8: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[UV1]](s128)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC1]], 1
; GFX8: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[TRUNC1]], [[COPY3]](s32) ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[COPY1]](s32)
; GFX8: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY4]](s32) ; GFX8: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG1]](s64), [[ASHR1]](s64)
; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[ASHR2]], [[COPY5]](s32)
; GFX8: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR2]](s64), [[ASHR3]](s64)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; GFX8: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
; GFX6-LABEL: name: test_sext_inreg_v2s128_1 ; GFX6-LABEL: name: test_sext_inreg_v2s128_1
; GFX6: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX6: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>) ; GFX6: [[UV:%[0-9]+]]:_(s128), [[UV1:%[0-9]+]]:_(s128) = G_UNMERGE_VALUES [[COPY]](<2 x s128>)
; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[UV]](s128) ; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[UV]](s128)
; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC]], 1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63 ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C]](s32) ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64)
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[COPY2]](s32)
; GFX6: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR]](s64), [[ASHR1]](s64)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[UV1]](s128) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[UV1]](s128)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[TRUNC1]], 1
; GFX6: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[TRUNC1]], [[COPY3]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[COPY1]](s32)
; GFX6: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY4]](s32) ; GFX6: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[SEXT_INREG1]](s64), [[ASHR1]](s64)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[ASHR2]], [[COPY5]](s32)
; GFX6: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ASHR2]](s64), [[ASHR3]](s64)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s128>) = G_BUILD_VECTOR [[MV]](s128), [[MV1]](s128)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>) ; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<2 x s128>)
%0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:_(<2 x s128>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(<2 x s128>) = G_SEXT_INREG %0, 1 %1:_(<2 x s128>) = G_SEXT_INREG %0, 1
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir

Show All 19 Lines
name: test_sext_s16_to_s64 name: test_sext_s16_to_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s16_to_s64 ; CHECK-LABEL: name: test_sext_s16_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 48 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s32) ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s64) = G_SEXT %1 %2:_(s64) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: test_sext_s16_to_s32 name: test_sext_s16_to_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s16_to_s32 ; CHECK-LABEL: name: test_sext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sext_s24_to_s32 name: test_sext_s24_to_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s24_to_s32 ; CHECK-LABEL: name: test_sext_s24_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 24
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0 %1:_(s24) = G_TRUNC %0
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sext_i1_to_s32 name: test_sext_i1_to_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_i1_to_s32 ; CHECK-LABEL: name: test_sext_i1_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0 %1:_(s1) = G_TRUNC %0
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sext_v2s16_to_v2s32 name: test_sext_v2s16_to_v2s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_v2s16_to_v2s32 ; CHECK-LABEL: name: test_sext_v2s16_to_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s32>) = G_SEXT %0 %1:_(<2 x s32>) = G_SEXT %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_v3s16_to_v3s32 name: test_sext_v3s16_to_v3s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_sext_v3s16_to_v3s32 ; CHECK-LABEL: name: test_sext_v3s16_to_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0 ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0 ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>) ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<3 x s16>) = G_EXTRACT %0, 0 %1:_(<3 x s16>) = G_EXTRACT %0, 0
%2:_(<3 x s32>) = G_SEXT %1 %2:_(<3 x s32>) = G_SEXT %1
$vgpr0_vgpr1_vgpr2 = COPY %2 $vgpr0_vgpr1_vgpr2 = COPY %2
... ...
--- ---
name: test_sext_v4s16_to_v4s32 name: test_sext_v4s16_to_v4s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_sext_v4s16_to_v4s32 ; CHECK-LABEL: name: test_sext_v4s16_to_v4s32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; CHECK: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32), [[ASHR3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>) ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s32>) = G_SEXT %0 %1:_(<4 x s32>) = G_SEXT %0
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
... ...
--- ---
name: test_sext_v2s32_to_v2s64 name: test_sext_v2s32_to_v2s64
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
--- ---
name: test_sext_s8_to_s24 name: test_sext_s8_to_s24
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s8_to_s24 ; CHECK-LABEL: name: test_sext_s8_to_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[SEXT_INREG]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C2]](s32)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND1]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[ASHR1]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s24) ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s24)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0 %1:_(s8) = G_TRUNC %0
%2:_(s24) = G_SEXT %1 %2:_(s24) = G_SEXT %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: test_sext_s7_to_s32 name: test_sext_s7_to_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s7_to_s32 ; CHECK-LABEL: name: test_sext_s7_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: S_ENDPGM 0, implicit [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0 %1:_(s7) = G_TRUNC %0
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: test_sext_s8_to_s32 name: test_sext_s8_to_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_s8_to_s32 ; CHECK-LABEL: name: test_sext_s8_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: S_ENDPGM 0, implicit [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0 %1:_(s8) = G_TRUNC %0
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: test_sext_s32_to_s96 name: test_sext_s32_to_s96
▲ Show 20 Lines • Show All 419 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,SI # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefix=SI
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,VI # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefix=VI
--- ---
name: test_sextload_flat_i32_i8 name: test_sextload_flat_i32_i8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; SI-LABEL: name: test_sextload_flat_i32_i8 ; SI-LABEL: name: test_sextload_flat_i32_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1) ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; SI: $vgpr0 = COPY [[SEXTLOAD]](s32) ; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-LABEL: name: test_sextload_flat_i32_i8 ; VI-LABEL: name: test_sextload_flat_i32_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; VI: $vgpr0 = COPY [[SEXT_INREG]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; VI: $vgpr0 = COPY [[ASHR]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1 %0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 0) %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_sextload_flat_i32_i16 name: test_sextload_flat_i32_i16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; SI-LABEL: name: test_sextload_flat_i32_i16 ; SI-LABEL: name: test_sextload_flat_i32_i16
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2) ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
; SI: $vgpr0 = COPY [[SEXTLOAD]](s32) ; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-LABEL: name: test_sextload_flat_i32_i16 ; VI-LABEL: name: test_sextload_flat_i32_i16
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; VI: $vgpr0 = COPY [[SEXT_INREG]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; VI: $vgpr0 = COPY [[ASHR]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1 %0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 0) %1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 0)
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_sextload_flat_i31_i8 name: test_sextload_flat_i31_i8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; SI-LABEL: name: test_sextload_flat_i31_i8 ; SI-LABEL: name: test_sextload_flat_i31_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1) ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32) ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
; SI: $vgpr0 = COPY [[COPY1]](s32) ; SI: $vgpr0 = COPY [[COPY1]](s32)
; VI-LABEL: name: test_sextload_flat_i31_i8 ; VI-LABEL: name: test_sextload_flat_i31_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; VI: $vgpr0 = COPY [[COPY2]](s32) ; VI: $vgpr0 = COPY [[COPY2]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1 %0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s31) = G_SEXTLOAD %0 :: (load 1, addrspace 0) %1:_(s31) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sextload_flat_i64_i8 name: test_sextload_flat_i64_i8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; SI-LABEL: name: test_sextload_flat_i64_i8 ; SI-LABEL: name: test_sextload_flat_i64_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1) ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32) ; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64) ; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; VI-LABEL: name: test_sextload_flat_i64_i8 ; VI-LABEL: name: test_sextload_flat_i64_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)
; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64) ; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1 %0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXTLOAD %0 :: (load 1, addrspace 0) %1:_(s64) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sextload_flat_i64_i16 name: test_sextload_flat_i64_i16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; SI-LABEL: name: test_sextload_flat_i64_i16 ; SI-LABEL: name: test_sextload_flat_i64_i16
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2) ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32) ; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64) ; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; VI-LABEL: name: test_sextload_flat_i64_i16 ; VI-LABEL: name: test_sextload_flat_i64_i16
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXT_INREG]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)
; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64) ; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1 %0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXTLOAD %0 :: (load 2, addrspace 0) %1:_(s64) = G_SEXTLOAD %0 :: (load 2, addrspace 0)
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sextload_flat_i64_i32 name: test_sextload_flat_i64_i32
body: | body: |
Show All 17 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir

Show First 20 Lines • Show All 275 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT1]](<3 x s16>), 0 ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT1]](<3 x s16>), 0
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>) ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64 ; CHECK: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT2]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT2]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0 ; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>) ; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) ; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; CHECK: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32) ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; CHECK: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL4]], [[C]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32) ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; CHECK: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[C]](s32) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG3]](s32), [[SEXT_INREG4]](s32), [[SEXT_INREG5]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR3]](s32), [[ASHR4]](s32), [[ASHR5]](s32)
; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR1]](<3 x s32>), 32 ; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR1]](<3 x s32>), 32
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT3]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT3]](s32)
; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT1]](<3 x s16>), 0 ; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT1]](<3 x s16>), 0
; CHECK: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>) ; CHECK: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>)
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>) ; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32) ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>) ; CHECK: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32) ; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32) ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32) ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
; CHECK: [[ASHR6:%[0-9]+]]:_(s32) = G_ASHR [[SHL6]], [[C]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32) ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32) ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
; CHECK: [[ASHR7:%[0-9]+]]:_(s32) = G_ASHR [[SHL7]], [[C]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32) ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[C]](s32) ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 16
; CHECK: [[ASHR8:%[0-9]+]]:_(s32) = G_ASHR [[SHL8]], [[C]](s32) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG6]](s32), [[SEXT_INREG7]](s32), [[SEXT_INREG8]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR6]](s32), [[ASHR7]](s32), [[ASHR8]](s32)
; CHECK: [[EXTRACT4:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR2]](<3 x s32>), 0 ; CHECK: [[EXTRACT4:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR2]](<3 x s32>), 0
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT4]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT4]](s32)
; CHECK: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT]](<3 x s16>), 0 ; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT3]](<4 x s16>) ; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT3]](<4 x s16>)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>) ; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32) ; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>) ; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32) ; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32) ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C]](s32) ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 16
; CHECK: [[ASHR9:%[0-9]+]]:_(s32) = G_ASHR [[SHL9]], [[C]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32) ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C]](s32) ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 16
; CHECK: [[ASHR10:%[0-9]+]]:_(s32) = G_ASHR [[SHL10]], [[C]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32) ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C]](s32) ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 16
; CHECK: [[ASHR11:%[0-9]+]]:_(s32) = G_ASHR [[SHL11]], [[C]](s32) ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG9]](s32), [[SEXT_INREG10]](s32), [[SEXT_INREG11]](s32)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR9]](s32), [[ASHR10]](s32), [[ASHR11]](s32)
; CHECK: [[EXTRACT5:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR3]](<3 x s32>), 0 ; CHECK: [[EXTRACT5:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR3]](<3 x s32>), 0
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT5]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT5]](s32)
; CHECK: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; CHECK: [[BUILD_VECTOR4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; CHECK: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16) ; CHECK: [[BUILD_VECTOR5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>) ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR4]](<2 x s16>), [[BUILD_VECTOR5]](<2 x s16>)
; CHECK: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) ; CHECK: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3 %1:_(<4 x s16>) = COPY $vgpr2_vgpr3
%2:_(<3 x s16>) = G_EXTRACT %0, 0 %2:_(<3 x s16>) = G_EXTRACT %0, 0
%3:_(<3 x s16>) = G_EXTRACT %1, 0 %3:_(<3 x s16>) = G_EXTRACT %1, 0
%4:_(<4 x s16>) = G_SHUFFLE_VECTOR %2, %3, shufflemask(5, 1, 3, 0) %4:_(<4 x s16>) = G_SHUFFLE_VECTOR %2, %3, shufflemask(5, 1, 3, 0)
$vgpr0_vgpr1 = COPY %4 $vgpr0_vgpr1 = COPY %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
name: test_sitofp_s16_to_s16 name: test_sitofp_s16_to_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: test_sitofp_s16_to_s16 ; GFX6-LABEL: name: test_sitofp_s16_to_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX6: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16) ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: test_sitofp_s16_to_s16 ; GFX8-LABEL: name: test_sitofp_s16_to_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[TRUNC]](s16) ; GFX8: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[TRUNC]](s16)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_SITOFP %1 %2:_(s16) = G_SITOFP %1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: test_sitofp_s16_to_s32 name: test_sitofp_s16_to_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: test_sitofp_s16_to_s32 ; GFX6-LABEL: name: test_sitofp_s16_to_s32
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX6: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; GFX6: $vgpr0 = COPY [[SITOFP]](s32) ; GFX6: $vgpr0 = COPY [[SITOFP]](s32)
; GFX8-LABEL: name: test_sitofp_s16_to_s32 ; GFX8-LABEL: name: test_sitofp_s16_to_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX8: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; GFX8: $vgpr0 = COPY [[SITOFP]](s32) ; GFX8: $vgpr0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SITOFP %1 %2:_(s32) = G_SITOFP %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sitofp_s16_to_s64 name: test_sitofp_s16_to_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: test_sitofp_s16_to_s64 ; GFX6-LABEL: name: test_sitofp_s16_to_s64
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX6: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[SITOFP]](s64) ; GFX6: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
; GFX8-LABEL: name: test_sitofp_s16_to_s64 ; GFX8-LABEL: name: test_sitofp_s16_to_s64
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[SITOFP]](s64) ; GFX8: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s64) = G_SITOFP %1 %2:_(s64) = G_SITOFP %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: test_sitofp_s8_to_s16 name: test_sitofp_s8_to_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: test_sitofp_s8_to_s16 ; GFX6-LABEL: name: test_sitofp_s8_to_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX6: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16) ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: test_sitofp_s8_to_s16 ; GFX8-LABEL: name: test_sitofp_s8_to_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX8: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[ASHR]](s32)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0 %1:_(s8) = G_TRUNC %0
%2:_(s16) = G_SITOFP %1 %2:_(s16) = G_SITOFP %1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: test_sitofp_s8_to_s32 name: test_sitofp_s8_to_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: test_sitofp_s8_to_s32 ; GFX6-LABEL: name: test_sitofp_s8_to_s32
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX6: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; GFX6: $vgpr0 = COPY [[SITOFP]](s32) ; GFX6: $vgpr0 = COPY [[SITOFP]](s32)
; GFX8-LABEL: name: test_sitofp_s8_to_s32 ; GFX8-LABEL: name: test_sitofp_s8_to_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX8: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; GFX8: $vgpr0 = COPY [[SITOFP]](s32) ; GFX8: $vgpr0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0 %1:_(s8) = G_TRUNC %0
%2:_(s32) = G_SITOFP %1 %2:_(s32) = G_SITOFP %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sitofp_s8_to_s64 name: test_sitofp_s8_to_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: test_sitofp_s8_to_s64 ; GFX6-LABEL: name: test_sitofp_s8_to_s64
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX6: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[SITOFP]](s64) ; GFX6: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
; GFX8-LABEL: name: test_sitofp_s8_to_s64 ; GFX8-LABEL: name: test_sitofp_s8_to_s64
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[SITOFP]](s64) ; GFX8: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0 %1:_(s8) = G_TRUNC %0
%2:_(s64) = G_SITOFP %1 %2:_(s64) = G_SITOFP %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir

Show All 34 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_smax_s16 ; SI-LABEL: name: test_smax_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_smax_s16 ; VI-LABEL: name: test_smax_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[TRUNC]], [[TRUNC1]] ; VI: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[TRUNC]], [[TRUNC1]]
Show All 21 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_smax_s8 ; SI-LABEL: name: test_smax_s8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_smax_s8 ; VI-LABEL: name: test_smax_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) ; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16) ; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16)
; VI: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[ASHR]], [[ASHR1]] ; VI: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[ASHR]], [[ASHR1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_smax_s8 ; GFX9-LABEL: name: test_smax_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16) ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[TRUNC]], [[TRUNC1]]
; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[ASHR]], [[ASHR1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_SMAX %2, %3 %4:_(s8) = G_SMAX %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
... ...
--- ---
name: test_smax_s17 name: test_smax_s17
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_smax_s17 ; SI-LABEL: name: test_smax_s17
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_smax_s17 ; VI-LABEL: name: test_smax_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; VI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; VI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; VI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; VI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32) ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
; VI: $vgpr0 = COPY [[COPY4]](s32) ; VI: $vgpr0 = COPY [[COPY4]](s32)
; GFX9-LABEL: name: test_smax_s17 ; GFX9-LABEL: name: test_smax_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32) ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0 %2:_(s17) = G_TRUNC %0
%3:_(s17) = G_TRUNC %1 %3:_(s17) = G_TRUNC %1
%4:_(s17) = G_SMAX %2, %3 %4:_(s17) = G_SMAX %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
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; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG2]], [[SEXT_INREG3]]
; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[ASHR2]], [[ASHR3]]
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX1]](s32)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; VI-LABEL: name: test_smax_v2s16 ; VI-LABEL: name: test_smax_v2s16
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines bb.0:
; SI: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; SI: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; SI: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT1]](<3 x s16>), 0 ; SI: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT1]](<3 x s16>), 0
; SI: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>) ; SI: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) ; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG2]], [[SEXT_INREG3]]
; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[ASHR2]], [[ASHR3]]
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; SI: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL4]], [[C]](s32)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[C]](s32) ; SI: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG4]], [[SEXT_INREG5]]
; SI: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[ASHR4]], [[ASHR5]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX2]](s32) ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX2]](s32)
; SI: [[DEF4:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF ; SI: [[DEF4:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF4]](s16) ; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF4]](s16)
; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>) ; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; SI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0 ; SI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; SI: S_NOP 0, implicit [[EXTRACT2]](<3 x s16>) ; SI: S_NOP 0, implicit [[EXTRACT2]](<3 x s16>)
; VI-LABEL: name: test_smax_v3s16 ; VI-LABEL: name: test_smax_v3s16
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines bb.0:
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) ; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) ; SI: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) ; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG2]], [[SEXT_INREG3]]
; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[ASHR2]], [[ASHR3]]
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX1]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32) ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; SI: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL4]], [[C]](s32)
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32) ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; SI: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[C]](s32) ; SI: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG4]], [[SEXT_INREG5]]
; SI: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[ASHR4]], [[ASHR5]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX2]](s32) ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX2]](s32)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32) ; SI: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
; SI: [[ASHR6:%[0-9]+]]:_(s32) = G_ASHR [[SHL6]], [[C]](s32)
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32) ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32) ; SI: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
; SI: [[ASHR7:%[0-9]+]]:_(s32) = G_ASHR [[SHL7]], [[C]](s32) ; SI: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG6]], [[SEXT_INREG7]]
; SI: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[ASHR6]], [[ASHR7]]
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX3]](s32) ; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SMAX3]](s32)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16) ; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>) ; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; SI: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) ; SI: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; VI-LABEL: name: test_smax_v4s16 ; VI-LABEL: name: test_smax_v4s16
; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir

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body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_smin_s16 ; SI-LABEL: name: test_smin_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_smin_s16 ; VI-LABEL: name: test_smin_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[TRUNC1]] ; VI: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[TRUNC1]]
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body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_smin_s8 ; SI-LABEL: name: test_smin_s8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_smin_s8 ; VI-LABEL: name: test_smin_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) ; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16) ; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16)
; VI: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[ASHR]], [[ASHR1]] ; VI: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[ASHR]], [[ASHR1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_smin_s8 ; GFX9-LABEL: name: test_smin_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16) ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[TRUNC1]]
; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[ASHR]], [[ASHR1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_SMIN %2, %3 %4:_(s8) = G_SMIN %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
... ...
--- ---
name: test_smin_s17 name: test_smin_s17
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_smin_s17 ; SI-LABEL: name: test_smin_s17
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_smin_s17 ; VI-LABEL: name: test_smin_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; VI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; VI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; VI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; VI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32) ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; VI: $vgpr0 = COPY [[COPY4]](s32) ; VI: $vgpr0 = COPY [[COPY4]](s32)
; GFX9-LABEL: name: test_smin_s17 ; GFX9-LABEL: name: test_smin_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32) ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0 %2:_(s17) = G_TRUNC %0
%3:_(s17) = G_TRUNC %1 %3:_(s17) = G_TRUNC %1
%4:_(s17) = G_SMIN %2, %3 %4:_(s17) = G_SMIN %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
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; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG2]], [[SEXT_INREG3]]
; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[ASHR2]], [[ASHR3]]
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN1]](s32)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; VI-LABEL: name: test_smin_v2s16 ; VI-LABEL: name: test_smin_v2s16
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; SI: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; SI: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; SI: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT1]](<3 x s16>), 0 ; SI: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT1]](<3 x s16>), 0
; SI: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>) ; SI: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) ; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG2]], [[SEXT_INREG3]]
; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[ASHR2]], [[ASHR3]]
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; SI: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL4]], [[C]](s32)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[C]](s32) ; SI: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG4]], [[SEXT_INREG5]]
; SI: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[ASHR4]], [[ASHR5]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN2]](s32) ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN2]](s32)
; SI: [[DEF4:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF ; SI: [[DEF4:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF4]](s16) ; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[DEF4]](s16)
; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>) ; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; SI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0 ; SI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; SI: S_NOP 0, implicit [[EXTRACT2]](<3 x s16>) ; SI: S_NOP 0, implicit [[EXTRACT2]](<3 x s16>)
; VI-LABEL: name: test_smin_v3s16 ; VI-LABEL: name: test_smin_v3s16
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; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) ; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) ; SI: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) ; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG2]], [[SEXT_INREG3]]
; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[ASHR2]], [[ASHR3]]
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN1]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN1]](s32)
; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32) ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; SI: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL4]], [[C]](s32)
; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32) ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; SI: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[C]](s32) ; SI: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG4]], [[SEXT_INREG5]]
; SI: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[ASHR4]], [[ASHR5]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN2]](s32) ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN2]](s32)
; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32) ; SI: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
; SI: [[ASHR6:%[0-9]+]]:_(s32) = G_ASHR [[SHL6]], [[C]](s32)
; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32) ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32) ; SI: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
; SI: [[ASHR7:%[0-9]+]]:_(s32) = G_ASHR [[SHL7]], [[C]](s32) ; SI: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG6]], [[SEXT_INREG7]]
; SI: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[ASHR6]], [[ASHR7]]
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN3]](s32) ; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN3]](s32)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16) ; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>) ; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; SI: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) ; SI: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; VI-LABEL: name: test_smin_v4s16 ; VI-LABEL: name: test_smin_v4s16
; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir

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body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: test_srem_s16 ; GFX6-LABEL: name: test_srem_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX6: $vgpr0 = COPY [[AND]](s32) ; GFX6: $vgpr0 = COPY [[AND]](s32)
; GFX8-LABEL: name: test_srem_s16 ; GFX8-LABEL: name: test_srem_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX8: $vgpr0 = COPY [[AND]](s32) ; GFX8: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_srem_s16 ; GFX9-LABEL: name: test_srem_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32) ; GFX9: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_SREM %2, %3 %4:_(s16) = G_SREM %2, %3
%5:_(s32) = G_ZEXT %4 %5:_(s32) = G_ZEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
Show All 9 Lines bb.0:
; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SREM]](s32) ; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SREM]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; GFX6: [[SREM1:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SREM1:%[0-9]+]]:_(s32) = G_SREM [[ASHR2]], [[ASHR3]]
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SREM1]](s32) ; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SREM1]](s32)
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX6: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; GFX6: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX8-LABEL: name: test_srem_v2s16 ; GFX8-LABEL: name: test_srem_v2s16
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SREM]](s32) ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SREM]](s32)
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX8: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX8: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX8: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; GFX8: [[SREM1:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX8: [[SREM1:%[0-9]+]]:_(s32) = G_SREM [[ASHR2]], [[ASHR3]]
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SREM1]](s32) ; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SREM1]](s32)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX8: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; GFX8: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
; GFX9-LABEL: name: test_srem_v2s16 ; GFX9-LABEL: name: test_srem_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SREM]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SREM]](s32)
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX9: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32) ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX9: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32) ; GFX9: [[SREM1:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX9: [[SREM1:%[0-9]+]]:_(s32) = G_SREM [[ASHR2]], [[ASHR3]]
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SREM1]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SREM1]](s32)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1 %1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_SREM %0, %1 %2:_(<2 x s16>) = G_SREM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_srem_s7 name: test_srem_s7
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: test_srem_s7 ; GFX6-LABEL: name: test_srem_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32) ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: test_srem_s7 ; GFX8-LABEL: name: test_srem_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX8: $vgpr0 = COPY [[COPY4]](s32) ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
; GFX9-LABEL: name: test_srem_s7 ; GFX9-LABEL: name: test_srem_s7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32) ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
%4:_(s7) = G_SREM %2, %3 %4:_(s7) = G_SREM %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
... ...
--- ---
name: test_srem_s17 name: test_srem_s17
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: test_srem_s17 ; GFX6-LABEL: name: test_srem_s17
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX6: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32) ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: test_srem_s17 ; GFX8-LABEL: name: test_srem_s17
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX8: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX8: $vgpr0 = COPY [[COPY4]](s32) ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
; GFX9-LABEL: name: test_srem_s17 ; GFX9-LABEL: name: test_srem_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; GFX9: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
; GFX9: $vgpr0 = COPY [[COPY4]](s32) ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0 %2:_(s17) = G_TRUNC %0
%3:_(s17) = G_TRUNC %1 %3:_(s17) = G_TRUNC %1
%4:_(s17) = G_SREM %2, %3 %4:_(s17) = G_SREM %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
... ...
--- ---
name: test_srem_s33 name: test_srem_s33
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX6-LABEL: name: test_srem_s33 ; GFX6-LABEL: name: test_srem_s33
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[COPY3]](s32) ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX6: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY4]](s32) ; GFX6: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SREM]](s64)
; GFX6: [[COPY5:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; GFX6: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; GFX6: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY5]], [[C]](s32)
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY6]](s32)
; GFX6: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[ASHR]], [[ASHR1]]
; GFX6: [[COPY7:%[0-9]+]]:_(s64) = COPY [[SREM]](s64)
; GFX6: $vgpr0_vgpr1 = COPY [[COPY7]](s64)
; GFX8-LABEL: name: test_srem_s33 ; GFX8-LABEL: name: test_srem_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[COPY3]](s32) ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX8: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY4]](s32) ; GFX8: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SREM]](s64)
; GFX8: [[COPY5:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; GFX8: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; GFX8: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY5]], [[C]](s32)
; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY6]](s32)
; GFX8: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[ASHR]], [[ASHR1]]
; GFX8: [[COPY7:%[0-9]+]]:_(s64) = COPY [[SREM]](s64)
; GFX8: $vgpr0_vgpr1 = COPY [[COPY7]](s64)
; GFX9-LABEL: name: test_srem_s33 ; GFX9-LABEL: name: test_srem_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[COPY3]](s32) ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX9: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY4]](s32) ; GFX9: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SREM]](s64)
; GFX9: [[COPY5:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) ; GFX9: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY5]], [[C]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[COPY6]](s32)
; GFX9: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[ASHR]], [[ASHR1]]
; GFX9: [[COPY7:%[0-9]+]]:_(s64) = COPY [[SREM]](s64)
; GFX9: $vgpr0_vgpr1 = COPY [[COPY7]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s33) = G_TRUNC %0 %2:_(s33) = G_TRUNC %0
%3:_(s33) = G_TRUNC %1 %3:_(s33) = G_TRUNC %1
%4:_(s33) = G_SREM %2, %3 %4:_(s33) = G_SREM %2, %3
%5:_(s64) = G_ANYEXT %4 %5:_(s64) = G_ANYEXT %4
$vgpr0_vgpr1 = COPY %5 $vgpr0_vgpr1 = COPY %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir

Show All 9 Lines bb.0:
; CHECK-LABEL: name: test_ssubo_s16 ; CHECK-LABEL: name: test_ssubo_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C1]](s32) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C1]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C1]](s32)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ASHR2]](s32), [[SEXT]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[SEXT]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]] ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK: $vgpr0 = COPY [[COPY7]](s32) ; CHECK: $vgpr0 = COPY [[COPY7]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
--- ---
name: sext_inreg_s_s32_1 name: sext_inreg_s_s32_1
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: sext_inreg_s_s32_1
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(s32) = G_SEXT_INREG %0, 1 %1:_(s32) = G_SEXT_INREG %0, 1
S_ENDPGM 0, implicit %1
... ...
--- ---
name: sext_inreg_s_s64_1 name: sext_inreg_s_s64_1
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
%0:_(s64) = COPY $sgpr0 ; CHECK-LABEL: name: sext_inreg_s_s64_1
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 1
; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s64) = G_SEXT_INREG %0, 1 %1:_(s64) = G_SEXT_INREG %0, 1
S_ENDPGM 0, implicit %1
...
---
name: sext_inreg_s_s64_31
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: sext_inreg_s_s64_31
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 31
; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s64) = G_SEXT_INREG %0, 31
S_ENDPGM 0, implicit %1
...
---
name: sext_inreg_s_s64_32
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: sext_inreg_s_s64_32
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s64) = G_SEXT_INREG %0, 32
S_ENDPGM 0, implicit %1
...
---
name: sext_inreg_s_s64_33
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: sext_inreg_s_s64_33
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s64) = G_SEXT_INREG %0, 32
S_ENDPGM 0, implicit %1
... ...
--- ---
name: sext_inreg_v_s32_1 name: sext_inreg_v_s32_1
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: sext_inreg_v_s32_1
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_SEXT_INREG %0, 1 %1:_(s32) = G_SEXT_INREG %0, 1
S_ENDPGM 0, implicit %1
... ...
--- ---
name: sext_inreg_v_s64_1 name: sext_inreg_v_s64_1
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
%0:_(s64) = COPY $vgpr0 ; CHECK-LABEL: name: sext_inreg_v_s64_1
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 1 %1:_(s64) = G_SEXT_INREG %0, 1
S_ENDPGM 0, implicit %1
... ...
--- ---
name: sext_inreg_s_s16_1 name: sext_inreg_v_s64_31
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $vgpr0_vgpr1
%0:_(s32) = COPY $sgpr0 ; CHECK-LABEL: name: sext_inreg_v_s64_31
%1:_(s16) = G_TRUNC %0 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
%2:_(s16) = G_SEXT_INREG %1, 1 ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV]], 31
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 31
S_ENDPGM 0, implicit %1
... ...
--- ---
name: sext_inreg_v_s16_1 name: sext_inreg_v_s64_32
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0_vgpr1
%0:_(s32) = COPY $vgpr0 ; CHECK-LABEL: name: sext_inreg_v_s64_32
%1:_(s16) = G_TRUNC %0 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
%2:_(s16) = G_SEXT_INREG %1, 1 ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[UV]](s32)
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[COPY1]], [[C]](s32)
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY1]](s32), [[ASHR]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 32
S_ENDPGM 0, implicit %1
...
---
name: sext_inreg_v_s64_33
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: sext_inreg_v_s64_33
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
; CHECK: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: S_ENDPGM 0, implicit [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXT_INREG %0, 33
S_ENDPGM 0, implicit %1
... ...