[GlobalISel] Use pointer type size for offset constant when lowering load/stores

[gargaroff]

Summary

Lowering non-power-of-2 G_LOAD/G_STORE introduces a G_PTR_ADD. The offset constant used by this instruction uses 64-bit unconditionally. This causes legalization to fail for backends that don't use 64-bit pointers.

This patch uses the size of the pointer type for the type of the offset constant to fix this problem.

[gargaroff]

I didn't know if and where I can add a proper test for this. If that is required I'd appreciate it if you would point me in the right direction for it.

[arsenm]

While this is correct, this also shouldn't cause legalization to fail with non 64-bit pointers. Are you missing a legalize rule for the second type index for G_PTR_ADD?

[gargaroff]

In D73341#1838596, @arsenm wrote:

While this is correct, this also shouldn't cause legalization to fail with non 64-bit pointers. Are you missing a legalize rule for the second type index for G_PTR_ADD?

I don't think we do to be honest. This is our legalizer rule for G_PTR_ADD:

getActionDefinitionsBuilder(G_PTR_ADD)
    .legalFor({{p0, s32}})
    .clampScalar(1, s32, s32);

So we try to narrow the 64-bit constant to a 32-bit constant. In the LegalizerHelper::narrowScalar there is no rule for G_PTR_ADD, so it returns with UnableToLegalize.

[gargaroff]

Could someone with commit access land this for me?

[arsenm]

9965b12fd1bcb78396fbea2c28d80068e43b31a3

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
         LLT PtrTy = MRI.getType(PtrReg);
         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
         LLT AnyExtTy = LLT::scalar(AnyExtSize);
         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
         auto LargeLoad =
             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
 
-        auto OffsetCst =
-            MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
+        auto OffsetCst = MIRBuilder.buildConstant(
+            LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
         auto SmallPtr =
             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
                                               *SmallMMO);
 
         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);