[RISCV] Don't always execute SC for min/max masked AMOs

[jrtc27]

Summary

If we determine from the comparison that no change is needed, there is
no point in us executing the SC and conditionally retrying, since the
AMO can be viewed as having executed atomically at the time of the LR.

[jrtc27]

Never mind, I see why this is done, we need to respect the ordering, so skipping the SC misses the release.

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

bool RISCVExpandPseudo::expandAtomicMinMaxOp(
   assert(IsMasked == true &&
          "Should only need to expand masked atomic max/min");
   assert(Width == 32 && "Should never need to expand masked 64-bit operations");
 
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction *MF = MBB.getParent();
   auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
   auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
   auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
 
   // Insert new MBBs.
   MF->insert(++MBB.getIterator(), LoopHeadMBB);
-  MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB);
-  MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB);
+  MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB);
   MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
 
   // Set up successors and transfer remaining instructions to DoneMBB.
-  LoopHeadMBB->addSuccessor(LoopIfBodyMBB);
   LoopHeadMBB->addSuccessor(LoopTailMBB);
-  LoopIfBodyMBB->addSuccessor(LoopTailMBB);
-  LoopTailMBB->addSuccessor(LoopHeadMBB);
+  LoopHeadMBB->addSuccessor(DoneMBB);
   LoopTailMBB->addSuccessor(DoneMBB);
+  LoopTailMBB->addSuccessor(LoopHeadMBB);
   DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end());
   DoneMBB->transferSuccessors(&MBB);
   MBB.addSuccessor(LoopHeadMBB);
 
   Register DestReg = MI.getOperand(0).getReg();
   Register Scratch1Reg = MI.getOperand(1).getReg();
   Register Scratch2Reg = MI.getOperand(2).getReg();
   Register AddrReg = MI.getOperand(3).getReg();
   Register IncrReg = MI.getOperand(4).getReg();
   Register MaskReg = MI.getOperand(5).getReg();
   bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max;
   AtomicOrdering Ordering =
       static_cast<AtomicOrdering>(MI.getOperand(IsSigned ? 7 : 6).getImm());
 
   //
   // .loophead:
   //   lr.w destreg, (alignedaddr)
   //   and scratch2, destreg, mask
   //   mv scratch1, destreg
   //   [sext scratch2 if signed min/max]
-  //   ifnochangeneeded scratch2, incr, .looptail
+  //   ifnochangeneeded scratch2, incr, done
   BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
       .addReg(AddrReg);
   BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg)
       .addReg(DestReg)
       .addReg(MaskReg);
   BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg)
       .addReg(DestReg)
       .addImm(0);
 
   switch (BinOp) {
   default:
     llvm_unreachable("Unexpected AtomicRMW BinOp");
   case AtomicRMWInst::Max: {
     insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
         .addReg(Scratch2Reg)
         .addReg(IncrReg)
-        .addMBB(LoopTailMBB);
+        .addMBB(DoneMBB);
     break;
   }
   case AtomicRMWInst::Min: {
     insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
         .addReg(IncrReg)
         .addReg(Scratch2Reg)
-        .addMBB(LoopTailMBB);
+        .addMBB(DoneMBB);
     break;
   }
   case AtomicRMWInst::UMax:
     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
         .addReg(Scratch2Reg)
         .addReg(IncrReg)
-        .addMBB(LoopTailMBB);
+        .addMBB(DoneMBB);
     break;
   case AtomicRMWInst::UMin:
     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
         .addReg(IncrReg)
         .addReg(Scratch2Reg)
-        .addMBB(LoopTailMBB);
+        .addMBB(DoneMBB);
     break;
   }
 
-  // .loopifbody:
+  // .looptail:
   //   xor scratch1, destreg, incr
   //   and scratch1, scratch1, mask
   //   xor scratch1, destreg, scratch1
-  insertMaskedMerge(TII, DL, LoopIfBodyMBB, Scratch1Reg, DestReg, IncrReg,
-                    MaskReg, Scratch1Reg);
-
-  // .looptail:
   //   sc.w scratch1, scratch1, (addr)
   //   bnez scratch1, loop
+  insertMaskedMerge(TII, DL, LoopTailMBB, Scratch1Reg, DestReg, IncrReg,
+                    MaskReg, Scratch1Reg);
   BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg)
       .addReg(AddrReg)
       .addReg(Scratch1Reg);
   BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
       .addReg(Scratch1Reg)
       .addReg(RISCV::X0)
       .addMBB(LoopHeadMBB);
 
   NextMBBI = MBB.end();
   MI.eraseFromParent();
 
   LivePhysRegs LiveRegs;
   computeAndAddLiveIns(LiveRegs, *LoopHeadMBB);
-  computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB);
   computeAndAddLiveIns(LiveRegs, *LoopTailMBB);
   computeAndAddLiveIns(LiveRegs, *DoneMBB);
 
   return true;
 }
 
 bool RISCVExpandPseudo::expandAtomicCmpXchg(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked,

llvm/test/CodeGen/RISCV/atomic-rmw.ll

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB35_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB35_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB35_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB35_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB35_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB35_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB35_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB35_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b monotonic
   ret i8 %1
 }
 
 define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_acquire:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB36_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB36_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB36_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB36_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB36_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB36_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB36_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB36_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b acquire
   ret i8 %1
 }
 
 define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_release:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB37_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB37_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB37_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB37_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB37_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB37_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB37_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB37_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b release
   ret i8 %1
 }
 
 define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_acq_rel:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB38_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB38_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB38_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB38_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB38_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB38_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB38_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB38_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b acq_rel
   ret i8 %1
 }
 
 define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_seq_cst:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB39_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB39_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB39_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB39_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB39_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB39_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB39_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB39_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b seq_cst
   ret i8 %1
 }
 
 define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_monotonic:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB40_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB40_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB40_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB40_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB40_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB40_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b monotonic
   ret i8 %1
 }
 
 define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_acquire:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB41_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB41_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB41_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB41_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB41_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB41_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b acquire
   ret i8 %1
 }
 
 define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_release:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB42_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB42_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB42_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB42_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB42_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB42_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b release
   ret i8 %1
 }
 
 define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_acq_rel:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB43_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB43_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB43_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB43_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB43_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB43_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b acq_rel
   ret i8 %1
 }
 
 define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_seq_cst:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB44_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB44_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB44_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB44_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB44_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB44_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b seq_cst
   ret i8 %1
 }
 
 define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i8_monotonic:

 ; RV32IA-NEXT:    lr.w a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB45_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB45_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB45_3: # in Loop: Header=BB45_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB45_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB45_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB45_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB45_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB45_3: # in Loop: Header=BB45_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB45_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB45_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b monotonic
   ret i8 %1
 }
 
 define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i8_acquire:

 ; RV32IA-NEXT:    lr.w.aq a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB46_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB46_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB46_3: # in Loop: Header=BB46_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB46_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB46_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w.aq a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB46_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB46_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB46_3: # in Loop: Header=BB46_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB46_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB46_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b acquire
   ret i8 %1
 }
 
 define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i8_release:

 ; RV32IA-NEXT:    lr.w a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB47_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB47_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB47_3: # in Loop: Header=BB47_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB47_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB47_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB47_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB47_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB47_3: # in Loop: Header=BB47_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB47_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB47_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b release
   ret i8 %1
 }
 
 define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i8_acq_rel:

 ; RV32IA-NEXT:    lr.w.aq a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB48_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB48_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB48_3: # in Loop: Header=BB48_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB48_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB48_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w.aq a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB48_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB48_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB48_3: # in Loop: Header=BB48_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB48_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB48_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b acq_rel
   ret i8 %1
 }
 
 define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i8_seq_cst:

 ; RV32IA-NEXT:    lr.w.aqrl a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB49_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB49_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB49_3: # in Loop: Header=BB49_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB49_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB49_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w.aqrl a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB49_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB49_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB49_3: # in Loop: Header=BB49_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB49_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB49_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b seq_cst
   ret i8 %1
 }
 
 define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i8_monotonic:

 ; RV32IA-NEXT:    lr.w a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB50_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB50_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB50_3: # in Loop: Header=BB50_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB50_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB50_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB50_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB50_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB50_3: # in Loop: Header=BB50_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB50_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB50_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b monotonic
   ret i8 %1
 }
 
 define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i8_acquire:

 ; RV32IA-NEXT:    lr.w.aq a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB51_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB51_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB51_3: # in Loop: Header=BB51_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB51_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB51_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w.aq a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB51_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB51_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB51_3: # in Loop: Header=BB51_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB51_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB51_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b acquire
   ret i8 %1
 }
 
 define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i8_release:

 ; RV32IA-NEXT:    lr.w a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB52_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB52_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB52_3: # in Loop: Header=BB52_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB52_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB52_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB52_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB52_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB52_3: # in Loop: Header=BB52_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB52_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB52_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b release
   ret i8 %1
 }
 
 define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i8_acq_rel:

 ; RV32IA-NEXT:    lr.w.aq a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB53_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB53_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB53_3: # in Loop: Header=BB53_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB53_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB53_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w.aq a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB53_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB53_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB53_3: # in Loop: Header=BB53_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB53_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB53_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b acq_rel
   ret i8 %1
 }
 
 define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i8_seq_cst:

 ; RV32IA-NEXT:    lr.w.aqrl a4, (a6)
 ; RV32IA-NEXT:    and a2, a4, a3
 ; RV32IA-NEXT:    mv a5, a4
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB54_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB54_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB54_3: # in Loop: Header=BB54_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB54_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB54_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    lr.w.aqrl a4, (a6)
 ; RV64IA-NEXT:    and a2, a4, a3
 ; RV64IA-NEXT:    mv a5, a4
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB54_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB54_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB54_3: # in Loop: Header=BB54_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB54_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB54_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b seq_cst
   ret i8 %1
 }
 
 define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i16_monotonic:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB90_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB90_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB90_3: # in Loop: Header=BB90_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB90_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB90_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB90_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB90_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB90_3: # in Loop: Header=BB90_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB90_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB90_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b monotonic
   ret i16 %1
 }
 
 define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i16_acquire:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB91_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB91_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB91_3: # in Loop: Header=BB91_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB91_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB91_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB91_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB91_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB91_3: # in Loop: Header=BB91_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB91_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB91_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b acquire
   ret i16 %1
 }
 
 define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i16_release:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB92_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB92_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB92_3: # in Loop: Header=BB92_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB92_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB92_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB92_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB92_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB92_3: # in Loop: Header=BB92_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB92_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB92_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b release
   ret i16 %1
 }
 
 define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i16_acq_rel:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB93_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB93_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB93_3: # in Loop: Header=BB93_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB93_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB93_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB93_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB93_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB93_3: # in Loop: Header=BB93_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB93_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB93_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b acq_rel
   ret i16 %1
 }
 
 define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i16_seq_cst:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a3, a1, .LBB94_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB94_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB94_3: # in Loop: Header=BB94_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB94_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB94_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a3, a1, .LBB94_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB94_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB94_3: # in Loop: Header=BB94_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB94_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB94_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b seq_cst
   ret i16 %1
 }
 
 define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i16_monotonic:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB95_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB95_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB95_3: # in Loop: Header=BB95_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB95_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB95_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB95_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB95_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB95_3: # in Loop: Header=BB95_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB95_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB95_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b monotonic
   ret i16 %1
 }
 
 define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i16_acquire:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB96_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB96_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB96_3: # in Loop: Header=BB96_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB96_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB96_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB96_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB96_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB96_3: # in Loop: Header=BB96_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB96_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB96_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b acquire
   ret i16 %1
 }
 
 define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i16_release:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB97_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB97_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB97_3: # in Loop: Header=BB97_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB97_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB97_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB97_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB97_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB97_3: # in Loop: Header=BB97_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB97_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB97_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b release
   ret i16 %1
 }
 
 define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i16_acq_rel:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB98_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB98_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB98_3: # in Loop: Header=BB98_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB98_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB98_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB98_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB98_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB98_3: # in Loop: Header=BB98_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB98_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB98_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b acq_rel
   ret i16 %1
 }
 
 define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i16_seq_cst:

 ; RV32IA-NEXT:    mv a2, a5
 ; RV32IA-NEXT:    sll a3, a3, a4
 ; RV32IA-NEXT:    sra a3, a3, a4
 ; RV32IA-NEXT:    bge a1, a3, .LBB99_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB99_1 Depth=1
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB99_3: # in Loop: Header=BB99_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB99_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB99_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)

 ; RV64IA-NEXT:    mv a2, a5
 ; RV64IA-NEXT:    sll a3, a3, a4
 ; RV64IA-NEXT:    sra a3, a3, a4
 ; RV64IA-NEXT:    bge a1, a3, .LBB99_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB99_1 Depth=1
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB99_3: # in Loop: Header=BB99_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB99_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB99_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b seq_cst
   ret i16 %1
 }
 
 define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i16_monotonic:

 ; RV32IA-NEXT:    lr.w a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB100_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB100_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB100_3: # in Loop: Header=BB100_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB100_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB100_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB100_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB100_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB100_3: # in Loop: Header=BB100_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB100_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB100_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b monotonic
   ret i16 %1
 }
 
 define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i16_acquire:

 ; RV32IA-NEXT:    lr.w.aq a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB101_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB101_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB101_3: # in Loop: Header=BB101_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB101_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB101_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i16_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w.aq a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB101_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB101_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB101_3: # in Loop: Header=BB101_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB101_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB101_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b acquire
   ret i16 %1
 }
 
 define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i16_release:

 ; RV32IA-NEXT:    lr.w a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB102_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB102_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB102_3: # in Loop: Header=BB102_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB102_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB102_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i16_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB102_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB102_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB102_3: # in Loop: Header=BB102_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB102_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB102_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b release
   ret i16 %1
 }
 
 define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i16_acq_rel:

 ; RV32IA-NEXT:    lr.w.aq a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB103_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB103_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB103_3: # in Loop: Header=BB103_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB103_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB103_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i16_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w.aq a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB103_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB103_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB103_3: # in Loop: Header=BB103_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB103_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB103_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b acq_rel
   ret i16 %1
 }
 
 define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i16_seq_cst:

 ; RV32IA-NEXT:    lr.w.aqrl a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a2, a1, .LBB104_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB104_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB104_3: # in Loop: Header=BB104_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB104_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB104_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umax_i16_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w.aqrl a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a2, a1, .LBB104_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB104_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB104_3: # in Loop: Header=BB104_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB104_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB104_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b seq_cst
   ret i16 %1
 }
 
 define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i16_monotonic:

 ; RV32IA-NEXT:    lr.w a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB105_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB105_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB105_3: # in Loop: Header=BB105_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB105_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB105_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB105_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB105_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB105_3: # in Loop: Header=BB105_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB105_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB105_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b monotonic
   ret i16 %1
 }
 
 define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i16_acquire:

 ; RV32IA-NEXT:    lr.w.aq a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB106_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB106_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB106_3: # in Loop: Header=BB106_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB106_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB106_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i16_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w.aq a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB106_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB106_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB106_3: # in Loop: Header=BB106_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB106_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB106_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b acquire
   ret i16 %1
 }
 
 define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i16_release:

 ; RV32IA-NEXT:    lr.w a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB107_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB107_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB107_3: # in Loop: Header=BB107_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB107_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB107_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i16_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB107_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB107_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB107_3: # in Loop: Header=BB107_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB107_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB107_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b release
   ret i16 %1
 }
 
 define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i16_acq_rel:

 ; RV32IA-NEXT:    lr.w.aq a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB108_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB108_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB108_3: # in Loop: Header=BB108_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB108_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB108_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i16_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w.aq a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB108_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB108_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB108_3: # in Loop: Header=BB108_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB108_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB108_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b acq_rel
   ret i16 %1
 }
 
 define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i16_seq_cst:

 ; RV32IA-NEXT:    lr.w.aqrl a3, (a6)
 ; RV32IA-NEXT:    and a2, a3, a4
 ; RV32IA-NEXT:    mv a5, a3
 ; RV32IA-NEXT:    bgeu a1, a2, .LBB109_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB109_1 Depth=1
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB109_3: # in Loop: Header=BB109_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB109_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB109_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_umin_i16_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)

 ; RV64IA-NEXT:    lr.w.aqrl a3, (a6)
 ; RV64IA-NEXT:    and a2, a3, a4
 ; RV64IA-NEXT:    mv a5, a3
 ; RV64IA-NEXT:    bgeu a1, a2, .LBB109_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB109_1 Depth=1
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB109_3: # in Loop: Header=BB109_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB109_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB109_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b seq_cst
   ret i16 %1
 }
 
 define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i32_monotonic:

 ; RV32I-NEXT:    sw a3, 12(sp)
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
 ; RV32I-NEXT:    lw a3, 12(sp)
 ; RV32I-NEXT:    bnez a0, .LBB162_4
-; RV32I-NEXT:  LBB162_2: # %atomicrmw.start
+; RV32I-NEXT:  .LBB162_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    mv a2, a3
 ; RV32I-NEXT:    bgeu s1, a3, .LBB162_1
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB162_2 Depth=1
 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    j .LBB162_1
 ; RV32I-NEXT:  .LBB162_4: # %atomicrmw.end

 ; RV32I-NEXT:    bnez a0, .LBB200_7
 ; RV32I-NEXT:  .LBB200_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB200_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB200_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB200_5
-; RV32I-NEXT:  .LBB200_4:
+; RV32I-NEXT:  .LBB200_4: # in Loop: Header=BB200_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB200_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB200_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB200_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB200_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB200_7
 ; RV32IA-NEXT:  .LBB200_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB200_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB200_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB200_5
-; RV32IA-NEXT:  .LBB200_4:
+; RV32IA-NEXT:  .LBB200_4: # in Loop: Header=BB200_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB200_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB200_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB200_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB200_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB201_7
 ; RV32I-NEXT:  .LBB201_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB201_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB201_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB201_5
-; RV32I-NEXT:  .LBB201_4:
+; RV32I-NEXT:  .LBB201_4: # in Loop: Header=BB201_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB201_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB201_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB201_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB201_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB201_7
 ; RV32IA-NEXT:  .LBB201_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB201_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB201_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB201_5
-; RV32IA-NEXT:  .LBB201_4:
+; RV32IA-NEXT:  .LBB201_4: # in Loop: Header=BB201_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB201_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB201_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB201_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB201_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB202_7
 ; RV32I-NEXT:  .LBB202_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB202_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB202_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB202_5
-; RV32I-NEXT:  .LBB202_4:
+; RV32I-NEXT:  .LBB202_4: # in Loop: Header=BB202_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB202_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB202_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB202_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB202_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB202_7
 ; RV32IA-NEXT:  .LBB202_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB202_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB202_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB202_5
-; RV32IA-NEXT:  .LBB202_4:
+; RV32IA-NEXT:  .LBB202_4: # in Loop: Header=BB202_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB202_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB202_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB202_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB202_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB203_7
 ; RV32I-NEXT:  .LBB203_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB203_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB203_5
-; RV32I-NEXT:  .LBB203_4:
+; RV32I-NEXT:  .LBB203_4: # in Loop: Header=BB203_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB203_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB203_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB203_7
 ; RV32IA-NEXT:  .LBB203_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB203_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB203_5
-; RV32IA-NEXT:  .LBB203_4:
+; RV32IA-NEXT:  .LBB203_4: # in Loop: Header=BB203_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB203_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB203_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB204_7
 ; RV32I-NEXT:  .LBB204_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB204_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB204_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB204_5
-; RV32I-NEXT:  .LBB204_4:
+; RV32I-NEXT:  .LBB204_4: # in Loop: Header=BB204_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB204_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB204_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB204_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB204_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB204_7
 ; RV32IA-NEXT:  .LBB204_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB204_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB204_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB204_5
-; RV32IA-NEXT:  .LBB204_4:
+; RV32IA-NEXT:  .LBB204_4: # in Loop: Header=BB204_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB204_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB204_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB204_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB204_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB205_7
 ; RV32I-NEXT:  .LBB205_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB205_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB205_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB205_5
-; RV32I-NEXT:  .LBB205_4:
+; RV32I-NEXT:  .LBB205_4: # in Loop: Header=BB205_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB205_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB205_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB205_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB205_7
 ; RV32IA-NEXT:  .LBB205_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB205_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB205_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB205_5
-; RV32IA-NEXT:  .LBB205_4:
+; RV32IA-NEXT:  .LBB205_4: # in Loop: Header=BB205_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB205_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB205_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB205_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB206_7
 ; RV32I-NEXT:  .LBB206_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB206_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB206_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB206_5
-; RV32I-NEXT:  .LBB206_4:
+; RV32I-NEXT:  .LBB206_4: # in Loop: Header=BB206_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB206_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB206_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB206_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB206_7
 ; RV32IA-NEXT:  .LBB206_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB206_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB206_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB206_5
-; RV32IA-NEXT:  .LBB206_4:
+; RV32IA-NEXT:  .LBB206_4: # in Loop: Header=BB206_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB206_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB206_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB206_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB207_7
 ; RV32I-NEXT:  .LBB207_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB207_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB207_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB207_5
-; RV32I-NEXT:  .LBB207_4:
+; RV32I-NEXT:  .LBB207_4: # in Loop: Header=BB207_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB207_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB207_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB207_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB207_7
 ; RV32IA-NEXT:  .LBB207_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB207_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB207_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB207_5
-; RV32IA-NEXT:  .LBB207_4:
+; RV32IA-NEXT:  .LBB207_4: # in Loop: Header=BB207_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB207_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB207_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB207_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB208_7
 ; RV32I-NEXT:  .LBB208_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB208_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB208_5
-; RV32I-NEXT:  .LBB208_4:
+; RV32I-NEXT:  .LBB208_4: # in Loop: Header=BB208_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB208_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB208_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB208_7
 ; RV32IA-NEXT:  .LBB208_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB208_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB208_5
-; RV32IA-NEXT:  .LBB208_4:
+; RV32IA-NEXT:  .LBB208_4: # in Loop: Header=BB208_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB208_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB208_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB209_7
 ; RV32I-NEXT:  .LBB209_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB209_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB209_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB209_5
-; RV32I-NEXT:  .LBB209_4:
+; RV32I-NEXT:  .LBB209_4: # in Loop: Header=BB209_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB209_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB209_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB209_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB209_7
 ; RV32IA-NEXT:  .LBB209_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB209_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB209_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB209_5
-; RV32IA-NEXT:  .LBB209_4:
+; RV32IA-NEXT:  .LBB209_4: # in Loop: Header=BB209_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB209_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB209_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB209_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB210_7
 ; RV32I-NEXT:  .LBB210_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB210_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB210_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB210_5
-; RV32I-NEXT:  .LBB210_4:
+; RV32I-NEXT:  .LBB210_4: # in Loop: Header=BB210_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB210_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB210_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB210_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB210_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB210_7
 ; RV32IA-NEXT:  .LBB210_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB210_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB210_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB210_5
-; RV32IA-NEXT:  .LBB210_4:
+; RV32IA-NEXT:  .LBB210_4: # in Loop: Header=BB210_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB210_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB210_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB210_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB210_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB211_7
 ; RV32I-NEXT:  .LBB211_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB211_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB211_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB211_5
-; RV32I-NEXT:  .LBB211_4:
+; RV32I-NEXT:  .LBB211_4: # in Loop: Header=BB211_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB211_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB211_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB211_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB211_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB211_7
 ; RV32IA-NEXT:  .LBB211_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB211_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB211_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB211_5
-; RV32IA-NEXT:  .LBB211_4:
+; RV32IA-NEXT:  .LBB211_4: # in Loop: Header=BB211_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB211_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB211_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB211_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB211_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB212_7
 ; RV32I-NEXT:  .LBB212_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB212_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB212_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB212_5
-; RV32I-NEXT:  .LBB212_4:
+; RV32I-NEXT:  .LBB212_4: # in Loop: Header=BB212_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB212_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB212_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB212_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB212_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB212_7
 ; RV32IA-NEXT:  .LBB212_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB212_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB212_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB212_5
-; RV32IA-NEXT:  .LBB212_4:
+; RV32IA-NEXT:  .LBB212_4: # in Loop: Header=BB212_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB212_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB212_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB212_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB212_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB213_7
 ; RV32I-NEXT:  .LBB213_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB213_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB213_5
-; RV32I-NEXT:  .LBB213_4:
+; RV32I-NEXT:  .LBB213_4: # in Loop: Header=BB213_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB213_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB213_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB213_7
 ; RV32IA-NEXT:  .LBB213_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB213_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB213_5
-; RV32IA-NEXT:  .LBB213_4:
+; RV32IA-NEXT:  .LBB213_4: # in Loop: Header=BB213_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB213_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB213_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB214_7
 ; RV32I-NEXT:  .LBB214_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB214_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB214_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB214_5
-; RV32I-NEXT:  .LBB214_4:
+; RV32I-NEXT:  .LBB214_4: # in Loop: Header=BB214_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB214_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB214_2 Depth=1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB214_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB214_2 Depth=1

 ; RV32IA-NEXT:    bnez a0, .LBB214_7
 ; RV32IA-NEXT:  .LBB214_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB214_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB214_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB214_5
-; RV32IA-NEXT:  .LBB214_4:
+; RV32IA-NEXT:  .LBB214_4: # in Loop: Header=BB214_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB214_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB214_2 Depth=1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB214_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB214_2 Depth=1

 ; RV32I-NEXT:    bnez a0, .LBB215_7
 ; RV32I-NEXT:  .LBB215_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB215_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB215_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB215_5
-; RV32I-NEXT:  .LBB215_4:
+; RV32I-NEXT:  .LBB215_4: # in Loop: Header=BB215_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB215_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB215_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB215_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB215_7
 ; RV32IA-NEXT:  .LBB215_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB215_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB215_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB215_5
-; RV32IA-NEXT:  .LBB215_4:
+; RV32IA-NEXT:  .LBB215_4: # in Loop: Header=BB215_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB215_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB215_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB215_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB216_7
 ; RV32I-NEXT:  .LBB216_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB216_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB216_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB216_5
-; RV32I-NEXT:  .LBB216_4:
+; RV32I-NEXT:  .LBB216_4: # in Loop: Header=BB216_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB216_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB216_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB216_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB216_7
 ; RV32IA-NEXT:  .LBB216_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB216_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB216_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB216_5
-; RV32IA-NEXT:  .LBB216_4:
+; RV32IA-NEXT:  .LBB216_4: # in Loop: Header=BB216_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB216_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB216_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB216_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB217_7
 ; RV32I-NEXT:  .LBB217_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB217_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB217_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB217_5
-; RV32I-NEXT:  .LBB217_4:
+; RV32I-NEXT:  .LBB217_4: # in Loop: Header=BB217_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB217_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB217_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB217_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB217_7
 ; RV32IA-NEXT:  .LBB217_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB217_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB217_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB217_5
-; RV32IA-NEXT:  .LBB217_4:
+; RV32IA-NEXT:  .LBB217_4: # in Loop: Header=BB217_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB217_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB217_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB217_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB218_7
 ; RV32I-NEXT:  .LBB218_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB218_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB218_5
-; RV32I-NEXT:  .LBB218_4:
+; RV32I-NEXT:  .LBB218_4: # in Loop: Header=BB218_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB218_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB218_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB218_7
 ; RV32IA-NEXT:  .LBB218_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB218_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB218_5
-; RV32IA-NEXT:  .LBB218_4:
+; RV32IA-NEXT:  .LBB218_4: # in Loop: Header=BB218_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB218_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB218_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32I-NEXT:    bnez a0, .LBB219_7
 ; RV32I-NEXT:  .LBB219_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    beq a5, s1, .LBB219_4
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB219_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB219_5
-; RV32I-NEXT:  .LBB219_4:
+; RV32I-NEXT:  .LBB219_4: # in Loop: Header=BB219_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB219_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB219_2 Depth=1
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    mv a2, a4
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    bnez a0, .LBB219_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start

 ; RV32IA-NEXT:    bnez a0, .LBB219_7
 ; RV32IA-NEXT:  .LBB219_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    beq a5, s1, .LBB219_4
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB219_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB219_5
-; RV32IA-NEXT:  .LBB219_4:
+; RV32IA-NEXT:  .LBB219_4: # in Loop: Header=BB219_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB219_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB219_2 Depth=1
 ; RV32IA-NEXT:    xori a0, a0, 1
 ; RV32IA-NEXT:    mv a2, a4
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    bnez a0, .LBB219_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start