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AMDGPU: Move permlane discard vdst_in optimization
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Authored by arsenm on Jan 16 2020, 7:07 AM.

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Reviewers
rampitec
Summary

This case can be handled as a regular selection pattern, so move it
out of the weird post-isel folding code which doesn't have an exactly
equivalent place in GlobalISel.

I think it doesn't make much sense to do this optimization here
though, and it would be more useful in instcombine. There's not really
any new information that will be gained during lowering since these
inputs were known from the beginning.

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Event Timeline

arsenm created this revision.Jan 16 2020, 7:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 16 2020, 7:07 AM
rampitec added inline comments.Jan 16 2020, 12:13 PM
llvm/lib/Target/AMDGPU/VOP3Instructions.td
682

Don't you need added complexity here? The complexity of both patterns looks the same.

arsenm marked an inline comment as done.Jan 16 2020, 12:20 PM
arsenm added inline comments.
llvm/lib/Target/AMDGPU/VOP3Instructions.td
682

No, I think the custom predicate boosts the complexity score

rampitec accepted this revision.Jan 16 2020, 12:32 PM

LGTM

llvm/lib/Target/AMDGPU/VOP3Instructions.td
682
This revision is now accepted and ready to land.Jan 16 2020, 12:32 PM