[ARM,MVE] Use the new Tablegen `defvar` and `if` statements.

[simon_tatham]

Summary

This cleans up a lot of ugly foreach bodges that I've been using to
work around the lack of those two language features. Now they both
exist, I can make then all into something more legible!

In particular, in the common pattern in ARMInstrMVE.td where a
multiclass defines an Instruction instance plus one or more Pat that
select it, I've used a defvar to wrap !cast<Instruction>(NAME) so
that the patterns themselves become a little more legible.

Replacing a foreach with a defvar removes a level of block
structure, so several pieces of code have their indentation changed by
this patch. Best viewed with whitespace ignored.

NFC: the output of llvm-tblgen -print-records on the two affected
Tablegen sources is exactly identical before and after this change, so
there should be no effect at all on any of the other generated files.

[MarkMurrayARM]

llvm/lib/Target/ARM/ARMInstrMVE.td

2464

MUCH better!

clang/include/clang/Basic/arm_mve.td

 
 let params = T.Int in {
 def vminvq: Intrinsic<Scalar, (args Scalar:$prev, Vector:$vec),
     (Scalar (IRInt<"minv", [Vector], 1> $prev, $vec))>;
 def vmaxvq: Intrinsic<Scalar, (args Scalar:$prev, Vector:$vec),
     (Scalar (IRInt<"maxv", [Vector], 1> $prev, $vec))>;
 }
 
-foreach half = [ "b", "t" ] in
-foreach halfconst = [ !if(!eq(half, "b"), 0, 1) ] in {
+foreach half = [ "b", "t" ] in {
+  defvar halfconst = !if(!eq(half, "b"), 0, 1);
 
   let params = [f32], pnt = PNT_None in {
-
     def vcvt#half#q_f16: Intrinsic<
       VecOf<f16>, (args VecOf<f16>:$inactive, Vector:$a),
       (IRInt<"vcvt_narrow"> $inactive, $a, halfconst)>;
     def vcvt#half#q_m_f16: Intrinsic<
       VecOf<f16>, (args VecOf<f16>:$inactive, Vector:$a, PredOf<f32>:$pred),
       (IRInt<"vcvt_narrow_predicated"> $inactive, $a, halfconst, $pred)>;
-
   } // params = [f32], pnt = PNT_None
-
 } // loop over half = "b", "t"
 
 multiclass compare_with_pred<string condname, dag arguments,
                              dag cmp, string suffix> {
   // Make the predicated and unpredicated versions of a single comparison.
   def: Intrinsic<Predicate, arguments,
                  (u16 (IRInt<"pred_v2i", [Predicate]> cmp))>,
        NameOverride<"vcmp" # condname # "q" # suffix>;
defm "": IntrinsicMX<DblVector, (args Vector:$v, imm_1toN:$sh,
             $v, $sh, (unsignedflag Scalar), top, $pred, $inactive), 1, "_n">;
   }
 }
 defm vshllbq : vshll_imm<0>;
 defm vshlltq : vshll_imm<1>;
 
 multiclass DyadicImmShift<Type outtype, Immediate imm, string intname = NAME,
                           dag extraargs = (?)> {
-  foreach intparams = [!if(!eq(!cast<string>(outtype), !cast<string>(Vector)),
-                           [Vector], [outtype, Vector])] in {
-    def q_n: Intrinsic<
-        outtype, (args outtype:$a, Vector:$b, imm:$sh),
-        !con((IRInt<intname, intparams> $a, $b, $sh), extraargs)>;
+  defvar intparams = !if(!eq(!cast<string>(outtype), !cast<string>(Vector)),
+                         [Vector], [outtype, Vector]);
+
 
-    def q_m_n: Intrinsic<
-        outtype, (args outtype:$a, Vector:$b, imm:$sh, Predicate:$pred),
-        !con((IRInt<intname # "_predicated", intparams # [Predicate]>
-                 $a, $b, $sh), extraargs, (? $pred))>;
-  }
-}
 
 multiclass VSHRN<Type outtype, Immediate imm, dag extraargs> {
   defm b: DyadicImmShift<outtype, imm, "vshrn", !con(extraargs, (? 0))>;
   defm t: DyadicImmShift<outtype, imm, "vshrn", !con(extraargs, (? 1))>;
 }
 
 let params = [s16, s32, u16, u32], pnt = PNT_NType in {
-  foreach U = [(unsignedflag Scalar)] in {
-    defm vshrn   : VSHRN<HalfVector, imm_1toHalfN, (? 0,0,U,U)>;
-    defm vqshrn  : VSHRN<HalfVector, imm_1toHalfN, (? 1,0,U,U)>;
-    defm vrshrn  : VSHRN<HalfVector, imm_1toHalfN, (? 0,1,U,U)>;
-    defm vqrshrn : VSHRN<HalfVector, imm_1toHalfN, (? 1,1,U,U)>;
-  }
-}
+  defvar U = (unsignedflag Scalar);
 let params = [s16, s32], pnt = PNT_NType in {
   defm vqshrun  : VSHRN<UHalfVector, imm_1toHalfN, (? 1,0,1,0)>;
   defm vqrshrun : VSHRN<UHalfVector, imm_1toHalfN, (? 1,1,1,0)>;
 }
 let params = T.Int, pnt = PNT_NType in {
   defm vsli : DyadicImmShift<Vector, imm_0toNm1>;
   defm vsri : DyadicImmShift<Vector, imm_1toN>;
 }

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VABAV<string suffix, bit U, bits<2> size>
   let Inst{6} = 0b0;
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
 }
 
 multiclass MVE_VABAV_m<MVEVectorVTInfo VTI> {
   def "" : MVE_VABAV<VTI.Suffix, VTI.Unsigned, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     def : Pat<(i32 (int_arm_mve_vabav
-                            (i32 VTI.Unsigned),
-                            (i32 rGPR:$Rda_src),
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
-              (i32 (!cast<Instruction>(NAME)
-                            (i32 rGPR:$Rda_src),
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm)))>;
+              (i32 (Inst (i32 rGPR:$Rda_src),
 
     def : Pat<(i32 (int_arm_mve_vabav_predicated
-                            (i32 VTI.Unsigned),
-                            (i32 rGPR:$Rda_src),
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
-                            (VTI.Pred VCCR:$mask))),
-              (i32 (!cast<Instruction>(NAME)
-                            (i32 rGPR:$Rda_src),
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
-                            ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
+              (i32 (Inst (i32 rGPR:$Rda_src),
   }
 }
 
 defm MVE_VABAVs8  : MVE_VABAV_m<MVE_v16s8>;
 defm MVE_VABAVs16 : MVE_VABAV_m<MVE_v8s16>;
 defm MVE_VABAVs32 : MVE_VABAV_m<MVE_v4s32>;
 defm MVE_VABAVu8  : MVE_VABAV_m<MVE_v16u8>;
 defm MVE_VABAVu16 : MVE_VABAV_m<MVE_v8u16>;
class MVE_VMINMAXV<string iname, string suffix, bit U, bits<2> size,
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
 }
 
 multiclass MVE_VMINMAXV_p<string iname, bit bit_17, bit bit_7,
                           MVEVectorVTInfo VTI, Intrinsic intr> {
   def "": MVE_VMINMAXV<iname, VTI.Suffix, VTI.Unsigned, VTI.Size,
                        bit_17, bit_7>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in
   def _pat : Pat<(i32 (intr (i32 rGPR:$prev), (VTI.Vec MQPR:$vec))),
-                 (i32 (!cast<Instruction>(NAME)
-                           (i32 rGPR:$prev), (VTI.Vec MQPR:$vec)))>;
+                 (i32 (Inst (i32 rGPR:$prev), (VTI.Vec MQPR:$vec)))>;
 }
 
 multiclass MVE_VMINMAXV_ty<string iname, bit bit_7,
                            Intrinsic intr_s, Intrinsic intr_u> {
   defm s8 : MVE_VMINMAXV_p<iname, 1, bit_7, MVE_v16s8, intr_s>;
   defm s16: MVE_VMINMAXV_p<iname, 1, bit_7, MVE_v8s16, intr_s>;
   defm s32: MVE_VMINMAXV_p<iname, 1, bit_7, MVE_v4s32, intr_s>;
   defm u8 : MVE_VMINMAXV_p<iname, 1, bit_7, MVE_v16u8, intr_u>;
class MVE_VMINMAX<string iname, string suffix, bit U, bits<2> size,
   let Inst{6} = 0b1;
   let Inst{4} = bit_4;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VMINMAX_m<string iname, bit bit_4, MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VMINMAX<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, bit_4>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated min/max
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated min/max
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
                             (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VMAX<MVEVectorVTInfo VTI>
   : MVE_VMINMAX_m<"vmax", 0b0, VTI, !if(VTI.Unsigned, umax, smax), int_arm_mve_max_predicated>;
 multiclass MVE_VMIN<MVEVectorVTInfo VTI>
   : MVE_VMINMAX_m<"vmin", 0b1, VTI, !if(VTI.Unsigned, umin, smin), int_arm_mve_min_predicated>;
 
class MVE_VMULt1<string iname, string suffix, bits<2> size,
   let Inst{4} = 0b1;
   let Inst{0} = 0b0;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VMUL_m<string iname, MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VMULt1<iname, VTI.Suffix, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated multiply
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated multiply
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VMUL<MVEVectorVTInfo VTI>
   : MVE_VMUL_m<"vmul", VTI, mul, int_arm_mve_mul_predicated>;
 
 defm MVE_VMULi8  : MVE_VMUL<MVE_v16i8>;
 defm MVE_VMULi16 : MVE_VMUL<MVE_v8i16>;
class MVE_VQxDMULH_Base<string iname, string suffix, bits<2> size, bit rounding,
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
 }
 
 multiclass MVE_VQxDMULH_m<string iname, MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int,
                       bit rounding> {
   def "" : MVE_VQxDMULH_Base<iname, VTI.Suffix, VTI.Size, rounding>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated multiply
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated multiply
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VQxDMULH<string iname, MVEVectorVTInfo VTI, bit rounding>
   : MVE_VQxDMULH_m<iname, VTI, !if(rounding, int_arm_mve_vqrdmulh,
                                              int_arm_mve_vqdmulh),
                                !if(rounding, int_arm_mve_qrdmulh_predicated,
                                              int_arm_mve_qdmulh_predicated),
class MVE_VADDSUB<string iname, string suffix, bits<2> size, bit subtract,
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VADDSUB_m<string iname, MVEVectorVTInfo VTI, bit subtract,
                          SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VADDSUB<iname, VTI.Suffix, VTI.Size, subtract>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated add/subtract
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated add/subtract
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VADD<MVEVectorVTInfo VTI>
   : MVE_VADDSUB_m<"vadd", VTI, 0b0, add, int_arm_mve_add_predicated>;
 multiclass MVE_VSUB<MVEVectorVTInfo VTI>
   : MVE_VADDSUB_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>;
 

 class MVE_VQADD_<string suffix, bit U, bits<2> size>
   : MVE_VQADDSUB<"vqadd", suffix, U, 0b0, size>;
 class MVE_VQSUB_<string suffix, bit U, bits<2> size>
   : MVE_VQADDSUB<"vqsub", suffix, U, 0b1, size>;
 
 multiclass MVE_VQADD_m<MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VQADD_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated saturating add
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated saturating add
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
                             (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VQADD<MVEVectorVTInfo VTI, SDNode unpred_op>
   : MVE_VQADD_m<VTI, unpred_op, int_arm_mve_qadd_predicated>;
 
 defm MVE_VQADDs8  : MVE_VQADD<MVE_v16s8, saddsat>;
 defm MVE_VQADDs16 : MVE_VQADD<MVE_v8s16, saddsat>;
 defm MVE_VQADDs32 : MVE_VQADD<MVE_v4s32, saddsat>;
 defm MVE_VQADDu8  : MVE_VQADD<MVE_v16u8, uaddsat>;
 defm MVE_VQADDu16 : MVE_VQADD<MVE_v8u16, uaddsat>;
 defm MVE_VQADDu32 : MVE_VQADD<MVE_v4u32, uaddsat>;
 
 multiclass MVE_VQSUB_m<MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VQSUB_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated saturating subtract
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated saturating subtract
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
                             (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VQSUB<MVEVectorVTInfo VTI, SDNode unpred_op>
   : MVE_VQSUB_m<VTI, unpred_op, int_arm_mve_qsub_predicated>;
 
 defm MVE_VQSUBs8  : MVE_VQSUB<MVE_v16s8, ssubsat>;
 defm MVE_VQSUBs16 : MVE_VQSUB<MVE_v8s16, ssubsat>;
class MVE_VABD_int<string suffix, bit U, bits<2> size,
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VABD_m<MVEVectorVTInfo VTI,
                       Intrinsic unpred_int, Intrinsic pred_int> {
   def "" : MVE_VABD_int<VTI.Suffix, VTI.Unsigned, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated absolute difference
     def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated absolute difference
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
                             (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VABD<MVEVectorVTInfo VTI>
   : MVE_VABD_m<VTI, int_arm_mve_vabd, int_arm_mve_abd_predicated>;
 
 defm MVE_VABDs8  : MVE_VABD<MVE_v16s8>;
 defm MVE_VABDs16 : MVE_VABD<MVE_v8s16>;
class MVE_VRHADD_Base<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VRHADD_m<MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VRHADD_Base<VTI.Suffix, VTI.Unsigned, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated rounding add-with-divide-by-two
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated add-with-divide-by-two
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
                             (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VRHADD<MVEVectorVTInfo VTI>
   : MVE_VRHADD_m<VTI, int_arm_mve_vrhadd, int_arm_mve_rhadd_predicated>;
 
 defm MVE_VRHADDs8  : MVE_VRHADD<MVE_v16s8>;
 defm MVE_VRHADDs16 : MVE_VRHADD<MVE_v8s16>;
class MVE_VHADD_<string suffix, bit U, bits<2> size,
   : MVE_VHADDSUB<"vhadd", suffix, U, 0b0, size, pattern>;
 class MVE_VHSUB_<string suffix, bit U, bits<2> size,
               list<dag> pattern=[]>
   : MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
 
 multiclass MVE_VHADD_m<MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VHADD_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated add-and-divide-by-two
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (i32 VTI.Unsigned))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated add-and-divide-by-two
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (i32 VTI.Unsigned),
                             (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VHADD<MVEVectorVTInfo VTI>
   : MVE_VHADD_m<VTI, int_arm_mve_vhadd, int_arm_mve_hadd_predicated>;
 
 defm MVE_VHADDs8  : MVE_VHADD<MVE_v16s8>;
 defm MVE_VHADDs16 : MVE_VHADD<MVE_v8s16>;
 defm MVE_VHADDs32 : MVE_VHADD<MVE_v4s32>;
 defm MVE_VHADDu8  : MVE_VHADD<MVE_v16u8>;
 defm MVE_VHADDu16 : MVE_VHADD<MVE_v8u16>;
 defm MVE_VHADDu32 : MVE_VHADD<MVE_v4u32>;
 
 multiclass MVE_VHSUB_m<MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VHSUB_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated subtract-and-divide-by-two
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated subtract-and-divide-by-two
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
                             (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VHSUB<MVEVectorVTInfo VTI>
   : MVE_VHSUB_m<VTI, int_arm_mve_vhsub, int_arm_mve_hsub_predicated>;
 
 defm MVE_VHSUBs8  : MVE_VHSUB<MVE_v16s8>;
 defm MVE_VHSUBs16 : MVE_VHSUB<MVE_v8s16>;

 }
 
 defm MVE_VSHLL_lws8  : MVE_VSHLL_lw<"vshll", "s8",  0b00, 0b0, "$Qd, $Qm, #8">;
 defm MVE_VSHLL_lws16 : MVE_VSHLL_lw<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
 defm MVE_VSHLL_lwu8  : MVE_VSHLL_lw<"vshll", "u8",  0b00, 0b1, "$Qd, $Qm, #8">;
 defm MVE_VSHLL_lwu16 : MVE_VSHLL_lw<"vshll", "u16", 0b01, 0b1, "$Qd, $Qm, #16">;
 
 multiclass MVE_VSHLL_patterns<MVEVectorVTInfo VTI, int top> {
-  // A succession of local variable definitions, via singleton
-  // foreach, to make the actual patterns legible
-  foreach suffix = [!strconcat(VTI.Suffix, !if(top, "th", "bh"))] in
-  foreach inst_imm = [!cast<MVE_VSHLL_imm>("MVE_VSHLL_imm" # suffix)] in
-  foreach inst_lw = [!cast<MVE_VSHLL_by_lane_width>("MVE_VSHLL_lw" # suffix)] in
-  foreach unpred_int = [int_arm_mve_vshll_imm] in
-  foreach pred_int = [int_arm_mve_vshll_imm_predicated] in
-  foreach imm = [inst_imm.immediateType] in {
+  defvar suffix     = !strconcat(VTI.Suffix, !if(top, "th", "bh"));
+  defvar inst_imm   = !cast<MVE_VSHLL_imm>("MVE_VSHLL_imm" # suffix);
+  defvar inst_lw    = !cast<MVE_VSHLL_by_lane_width>("MVE_VSHLL_lw" # suffix);
+  defvar unpred_int = int_arm_mve_vshll_imm;
+  defvar pred_int   = int_arm_mve_vshll_imm_predicated;
+  defvar imm        = inst_imm.immediateType;
 
-    def : Pat<(VTI.DblVec (unpred_int (VTI.Vec MQPR:$src), imm:$imm,
-                                      (i32 VTI.Unsigned), (i32 top))),
-              (VTI.DblVec (inst_imm   (VTI.Vec MQPR:$src), imm:$imm))>;
-    def : Pat<(VTI.DblVec (unpred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits),
-                                      (i32 VTI.Unsigned), (i32 top))),
-              (VTI.DblVec (inst_lw    (VTI.Vec MQPR:$src)))>;
 
-    def : Pat<(VTI.DblVec (pred_int   (VTI.Vec MQPR:$src), imm:$imm,
-                                      (i32 VTI.Unsigned), (i32 top),
-                                      (VTI.Pred VCCR:$mask),
-                                      (VTI.DblVec MQPR:$inactive))),
-              (VTI.DblVec (inst_imm   (VTI.Vec MQPR:$src), imm:$imm,
-                                      ARMVCCThen, (VTI.Pred VCCR:$mask),
-                                      (VTI.DblVec MQPR:$inactive)))>;
-    def : Pat<(VTI.DblVec (pred_int   (VTI.Vec MQPR:$src), (i32 VTI.LaneBits),
-                                      (i32 VTI.Unsigned), (i32 top),
-                                      (VTI.Pred VCCR:$mask),
-                                      (VTI.DblVec MQPR:$inactive))),
-              (VTI.DblVec (inst_lw    (VTI.Vec MQPR:$src), ARMVCCThen,
-                                      (VTI.Pred VCCR:$mask),
-                                      (VTI.DblVec MQPR:$inactive)))>;
-
-  }
 }
 
 foreach VTI = [MVE_v16s8, MVE_v8s16, MVE_v16u8, MVE_v8u16] in
   foreach top = [0, 1] in
     defm : MVE_VSHLL_patterns<VTI, top>;
 
 class MVE_shift_imm_partial<Operand imm, string iname, string suffix>
   : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$QdSrc, MQPR:$Qm, imm:$imm),

 defm MVE_VQRSHRNbh : MVE_VxQRSHRN_types<"vqrshrnb", 0b1, 0b0>;
 defm MVE_VQRSHRNth : MVE_VxQRSHRN_types<"vqrshrnt", 0b1, 0b1>;
 defm MVE_VQSHRNbh  : MVE_VxQRSHRN_types<"vqshrnb", 0b0, 0b0>;
 defm MVE_VQSHRNth  : MVE_VxQRSHRN_types<"vqshrnt", 0b0, 0b1>;
 
 multiclass MVE_VSHRN_patterns<MVE_shift_imm_partial inst,
                               MVEVectorVTInfo OutVTI, MVEVectorVTInfo InVTI,
                               bit q, bit r, bit top> {
-  foreach inparams = [(? (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm),
-                         (inst.immediateType:$imm), (i32 q), (i32 r),
-                         (i32 OutVTI.Unsigned), (i32 InVTI.Unsigned),
-                         (i32 top))] in
-  foreach outparams = [(inst (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm),
-                             (imm:$imm))] in {
-    def : Pat<(OutVTI.Vec !setop(inparams, int_arm_mve_vshrn)),
-              (OutVTI.Vec outparams)>;
-    def : Pat<(OutVTI.Vec !con(inparams, (int_arm_mve_vshrn_predicated
-                                             (InVTI.Pred VCCR:$pred)))),
-              (OutVTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred)))>;
-  }
-}
+  defvar inparams = (? (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm),
+                       (i32 OutVTI.Unsigned), (i32 InVTI.Unsigned), (i32 top));
+  defvar outparams = (inst (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm),
+                           (imm:$imm));
+
 
 defm : MVE_VSHRN_patterns<MVE_VSHRNi16bh,    MVE_v16s8, MVE_v8s16, 0,0,0>;
 defm : MVE_VSHRN_patterns<MVE_VSHRNi16th,    MVE_v16s8, MVE_v8s16, 0,0,1>;
 defm : MVE_VSHRN_patterns<MVE_VSHRNi32bh,    MVE_v8s16, MVE_v4s32, 0,0,0>;
 defm : MVE_VSHRN_patterns<MVE_VSHRNi32th,    MVE_v8s16, MVE_v4s32, 0,0,1>;
 defm : MVE_VSHRN_patterns<MVE_VSHRNi16bh,    MVE_v16u8, MVE_v8u16, 0,0,0>;
 defm : MVE_VSHRN_patterns<MVE_VSHRNi16th,    MVE_v16u8, MVE_v8u16, 0,0,1>;
 defm : MVE_VSHRN_patterns<MVE_VSHRNi32bh,    MVE_v8u16, MVE_v4u32, 0,0,0>;
class MVE_shift_by_vec<string iname, string suffix, bit U,
   let Inst{4} = bit_4;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_shift_by_vec_p<string iname, MVEVectorVTInfo VTI, bit q, bit r> {
   def "" : MVE_shift_by_vec<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, q, r>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   def : Pat<(VTI.Vec (int_arm_mve_vshl_vector
                          (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
                          (i32 q), (i32 r), (i32 VTI.Unsigned))),
-            (VTI.Vec (!cast<Instruction>(NAME)
-                         (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh)))>;
+            (VTI.Vec (Inst (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh)))>;
 
   def : Pat<(VTI.Vec (int_arm_mve_vshl_vector_predicated
                          (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
                          (i32 q), (i32 r), (i32 VTI.Unsigned),
                          (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
-            (VTI.Vec (!cast<Instruction>(NAME)
-                         (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
+            (VTI.Vec (Inst (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
                            ARMVCCThen, (VTI.Pred VCCR:$mask),
                            (VTI.Vec MQPR:$inactive)))>;
 }
 
 multiclass mve_shift_by_vec_multi<string iname, bit bit_4, bit bit_8> {
   defm s8  : MVE_shift_by_vec_p<iname, MVE_v16s8, bit_4, bit_8>;
   defm s16 : MVE_shift_by_vec_p<iname, MVE_v8s16, bit_4, bit_8>;
   defm s32 : MVE_shift_by_vec_p<iname, MVE_v4s32, bit_4, bit_8>;
   defm u8  : MVE_shift_by_vec_p<iname, MVE_v16u8, bit_4, bit_8>;
   defm u16 : MVE_shift_by_vec_p<iname, MVE_v8u16, bit_4, bit_8>;

 }
 
 def MVE_VSLIimm32 : MVE_VSxI_imm<"vsli", "32", 0b1,imm0_31> {
   let Inst{21} = 0b1;
 }
 
 multiclass MVE_VSxI_patterns<MVE_VSxI_imm inst, string name,
                               MVEVectorVTInfo VTI> {
-  foreach inparams = [(? (VTI.Vec MQPR:$QdSrc), (VTI.Vec MQPR:$Qm),
-                         (inst.immediateType:$imm))] in
-  foreach outparams = [(inst (VTI.Vec MQPR:$QdSrc), (VTI.Vec MQPR:$Qm),
-                             (inst.immediateType:$imm))] in
-  foreach unpred_int = [!cast<Intrinsic>("int_arm_mve_" # name)] in
-  foreach pred_int = [!cast<Intrinsic>("int_arm_mve_" # name # "_predicated")] in {
-    def : Pat<(VTI.Vec !setop(inparams, unpred_int)),
-              (VTI.Vec outparams)>;
-    def : Pat<(VTI.Vec !con(inparams, (pred_int (VTI.Pred VCCR:$pred)))),
-              (VTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred)))>;
-  }
-}
+  defvar inparams = (? (VTI.Vec MQPR:$QdSrc), (VTI.Vec MQPR:$Qm),
+                       (inst.immediateType:$imm));
+  defvar outparams = (inst (VTI.Vec MQPR:$QdSrc), (VTI.Vec MQPR:$Qm),
+                           (inst.immediateType:$imm));
+  defvar unpred_int = !cast<Intrinsic>("int_arm_mve_" # name);
+  defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # name # "_predicated");
+
 
 defm : MVE_VSxI_patterns<MVE_VSLIimm8,  "vsli", MVE_v16i8>;
 defm : MVE_VSxI_patterns<MVE_VSLIimm16, "vsli", MVE_v8i16>;
 defm : MVE_VSxI_patterns<MVE_VSLIimm32, "vsli", MVE_v4i32>;
 defm : MVE_VSxI_patterns<MVE_VSRIimm8,  "vsri", MVE_v16i8>;
 defm : MVE_VSxI_patterns<MVE_VSRIimm16, "vsri", MVE_v8i16>;
 defm : MVE_VSxI_patterns<MVE_VSRIimm32, "vsri", MVE_v4i32>;
 
class MVE_VMUL_fp<string iname, string suffix, bit size, list<dag> pattern=[]>
   let Inst{7} = Qn{3};
   let Inst{4} = 0b1;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VMULT_fp_m<string iname, bit bit_21, MVEVectorVTInfo VTI,
                             SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VMUL_fp<iname, VTI.Suffix, VTI.Size{0}>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEFloat] in {
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VMUL_fp_m<MVEVectorVTInfo VTI>
   : MVE_VMULT_fp_m<"vmul", 0, VTI, fmul, int_arm_mve_mul_predicated>;
 
 defm MVE_VMULf32 : MVE_VMUL_fp_m<MVE_v4f32>;
 defm MVE_VMULf16 : MVE_VMUL_fp_m<MVE_v8f16>;
class MVE_VCMLA<string suffix, bit size>
   let Inst{15-13} = Qd{2-0};
   let Inst{12-8} = 0b01000;
   let Inst{7} = Qn{3};
   let Inst{4} = 0b0;
 }
 
 multiclass MVE_VCMLA_m<MVEVectorVTInfo VTI, bit size> {
   def "" : MVE_VCMLA<VTI.Suffix, size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEFloat] in {
     def : Pat<(VTI.Vec (int_arm_mve_vcmlaq
                             imm:$rot, (VTI.Vec MQPR:$Qd_src),
                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qd_src),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
                              (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                              imm:$rot))>;
 
     def : Pat<(VTI.Vec (int_arm_mve_vcmlaq_predicated
                             imm:$rot, (VTI.Vec MQPR:$Qd_src),
                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                             (VTI.Pred VCCR:$mask))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qn),
                              (VTI.Vec MQPR:$Qm), imm:$rot,
                              ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
 
   }
 }
 
 defm MVE_VCMLAf16 : MVE_VCMLA_m<MVE_v8f16, 0b0>;
 defm MVE_VCMLAf32 : MVE_VCMLA_m<MVE_v4f32, 0b1>;
 
 class MVE_VADDSUBFMA_fp<string iname, string suffix, bit size, bit bit_4,
def : Pat<(v4f32 (fma (fneg (v4f32 MQPR:$src1)), (v4f32 MQPR:$src2), (v4f32 MQPR:$src3))),
             (v4f32 (MVE_VFMSf32 $src3, $src1, $src2))>;
 }
 
 multiclass MVE_VADDSUB_fp_m<string iname, bit bit_21, MVEVectorVTInfo VTI,
                             SDNode unpred_op, Intrinsic pred_int> {
   def "" : MVE_VADDSUBFMA_fp<iname, VTI.Suffix, VTI.Size{0}, 0, 1, bit_21> {
     let validForTailPredication = 1;
   }
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEFloat] in {
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VADD_fp_m<MVEVectorVTInfo VTI>
   : MVE_VADDSUB_fp_m<"vadd", 0, VTI, fadd, int_arm_mve_add_predicated>;
 multiclass MVE_VSUB_fp_m<MVEVectorVTInfo VTI>
   : MVE_VADDSUB_fp_m<"vsub", 1, VTI, fsub, int_arm_mve_sub_predicated>;
 
class MVE_VCADD<string suffix, bit size, string cstr="">
   let Inst{15-13} = Qd{2-0};
   let Inst{12-8} = 0b01000;
   let Inst{7} = Qn{3};
   let Inst{4} = 0b0;
 }
 
 multiclass MVE_VCADD_m<MVEVectorVTInfo VTI, bit size, string cstr=""> {
   def "" : MVE_VCADD<VTI.Suffix, size, cstr>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEFloat] in {
     def : Pat<(VTI.Vec (int_arm_mve_vcaddq (i32 1),
                             imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                              imm:$rot))>;
 
     def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated (i32 1),
                             imm:$rot, (VTI.Vec MQPR:$inactive),
                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                             (VTI.Pred VCCR:$mask))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
-                            imm:$rot,
-                            ARMVCCThen, (VTI.Pred VCCR:$mask),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
+                             imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
 
   }
 }
 
 defm MVE_VCADDf16 : MVE_VCADD_m<MVE_v8f16, 0b0>;
 defm MVE_VCADDf32 : MVE_VCADD_m<MVE_v4f32, 0b1, "@earlyclobber $Qd">;
 
 class MVE_VABD_fp<string suffix, bit size>
class MVE_VABD_fp<string suffix, bit size>
   let Inst{7} = Qn{3};
   let Inst{4} = 0b0;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VABDT_fp_m<MVEVectorVTInfo VTI,
                             Intrinsic unpred_int, Intrinsic pred_int> {
   def "" : MVE_VABD_fp<VTI.Suffix, VTI.Size{0}>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEFloat] in {
     def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 0))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 0), (VTI.Pred VCCR:$mask),
                             (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VABD_fp_m<MVEVectorVTInfo VTI>
   : MVE_VABDT_fp_m<VTI, int_arm_mve_vabd, int_arm_mve_abd_predicated>;
 
 defm MVE_VABDf32 : MVE_VABD_fp_m<MVE_v4f32>;
 defm MVE_VABDf16 : MVE_VABD_fp_m<MVE_v8f16>;
class MVE_VCMUL<string iname, string suffix, bit size, string cstr="">
   let Inst{0} = rot{0};
 
   let Predicates = [HasMVEFloat];
 }
 
 multiclass MVE_VCMUL_m<string iname, MVEVectorVTInfo VTI,
                        bit size, string cstr=""> {
   def "" : MVE_VCMUL<iname, VTI.Suffix, size, cstr>;
-
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEFloat] in {
     def : Pat<(VTI.Vec (int_arm_mve_vcmulq
                             imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                              imm:$rot))>;
 
     def : Pat<(VTI.Vec (int_arm_mve_vcmulq_predicated
                             imm:$rot, (VTI.Vec MQPR:$inactive),
                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                             (VTI.Pred VCCR:$mask))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
-                            imm:$rot,
-                            ARMVCCThen, (VTI.Pred VCCR:$mask),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
+                             imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
 
   }
 }
 
 defm MVE_VCMULf16 : MVE_VCMUL_m<"vcmul", MVE_v8f16, 0b0>;
 defm MVE_VCMULf32 : MVE_VCMUL_m<"vcmul", MVE_v4f32, 0b1, "@earlyclobber $Qd">;
 
 class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VMULL_m<MVEVectorVTInfo VTI,
                        SDNode unpred_op, Intrinsic pred_int,
                        bit Top, string cstr=""> {
   def "" : MVE_VMULL<"vmull" # !if(Top, "t", "b"), VTI.Suffix, VTI.Unsigned,
                      VTI.Size, Top, cstr>;
+  defvar Inst = !cast<Instruction>(NAME);
 
-  foreach uflag = [!if(!eq(VTI.SuffixLetter, "p"),
-                       (?), (? (i32 VTI.Unsigned)))] in
   let Predicates = [HasMVEInt] in {
+    defvar uflag = !if(!eq(VTI.SuffixLetter, "p"), (?), (? (i32 VTI.Unsigned)));
 
     // Unpredicated multiply
     def : Pat<(VTI.DblVec !con((unpred_op (VTI.Vec MQPR:$Qm),
                                           (VTI.Vec MQPR:$Qn)),
                                uflag, (? (i32 Top)))),
-              (VTI.DblVec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated multiply
     def : Pat<(VTI.DblVec !con((pred_int (VTI.Vec MQPR:$Qm),
                                          (VTI.Vec MQPR:$Qn)),
                                uflag, (? (i32 Top), (VTI.Pred VCCR:$mask),
                                          (VTI.DblVec MQPR:$inactive)))),
-              (VTI.DblVec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                                 ARMVCCThen, (VTI.Pred VCCR:$mask),
                                 (VTI.DblVec MQPR:$inactive)))>;
   }
 }
 
 // For polynomial multiplies, the size bits take the unused value 0b11, and
 // the unsigned bit switches to encoding the size.
 
 defm MVE_VMULLBs8  : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull,
                                  int_arm_mve_mull_int_predicated, 0b0>;
class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size, bit round,
   let Inst{8} = 0b0;
   let Inst{7} = Qn{3};
   let Inst{0} = 0b1;
 }
 
 multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, SDNode unpred_op,
                         Intrinsic pred_int, bit round> {
   def "" : MVE_VxMULH<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, round>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // Unpredicated multiply returning high bits
     def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
 
     // Predicated multiply returning high bits
     def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                             (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
                             (VTI.Vec MQPR:$inactive))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
   }
 }
 
 multiclass MVE_VMULT<string iname, MVEVectorVTInfo VTI, bit round>
   : MVE_VxMULH_m<iname, VTI, !if(round, int_arm_mve_vrmulh, int_arm_mve_vmulh),
                  !if(round, int_arm_mve_rmulh_predicated,
                             int_arm_mve_mulh_predicated),
                  round>;
class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
   let Inst{8-7} = 0b00;
   let Inst{0} = 0b1;
 
   let Predicates = [HasMVEFloat];
 }
 
 multiclass MVE_VCVT_f2h_m<string iname, int half> {
   def "": MVE_VCVT_ff<iname, "f16.f32", 0b0, half>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEFloat] in {
     def : Pat<(v8f16 (int_arm_mve_vcvt_narrow
                          (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half))),
-              (v8f16 (!cast<Instruction>(NAME)
-                         (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>;
+              (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>;
     def : Pat<(v8f16 (int_arm_mve_vcvt_narrow_predicated
                          (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half),
                          (v4i1 VCCR:$mask))),
-              (v8f16 (!cast<Instruction>(NAME)
-                         (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm),
+              (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm),
                            ARMVCCThen, (v4i1 VCCR:$mask)))>;
   }
 }
 
 multiclass MVE_VCVT_h2f_m<string iname, int half> {
   def "": MVE_VCVT_ff<iname, "f32.f16", 0b1, half>;
 }
 
 defm MVE_VCVTf16f32bh : MVE_VCVT_f2h_m<"vcvtb", 0b0>;
class MVE_VxCADD<string iname, string suffix, bits<2> size, bit halve,
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{0} = 0b0;
 }
 
 multiclass MVE_VxCADD_m<string iname, MVEVectorVTInfo VTI,
                         bit halve, string cstr=""> {
   def "" : MVE_VxCADD<iname, VTI.Suffix, VTI.Size, halve, cstr>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     def : Pat<(VTI.Vec (int_arm_mve_vcaddq halve,
                             imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                              imm:$rot))>;
 
     def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated halve,
                             imm:$rot, (VTI.Vec MQPR:$inactive),
                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
                             (VTI.Pred VCCR:$mask))),
-              (VTI.Vec (!cast<Instruction>(NAME)
-                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
-                            imm:$rot,
-                            ARMVCCThen, (VTI.Pred VCCR:$mask),
+              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
+                             imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
 
   }
 }
 
 defm MVE_VCADDi8   : MVE_VxCADD_m<"vcadd", MVE_v16i8, 0b1>;
 defm MVE_VCADDi16  : MVE_VxCADD_m<"vcadd", MVE_v8i16, 0b1>;
 defm MVE_VCADDi32  : MVE_VxCADD_m<"vcadd", MVE_v4i32, 0b1, "@earlyclobber $Qd">;
 
class MVE_VxSHL_qr<string iname, string suffix, bit U, bits<2> size,
   let Inst{12-8} = 0b11110;
   let Inst{7} = bit_7;
   let Inst{6-4} = 0b110;
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VxSHL_qr_p<string iname, MVEVectorVTInfo VTI, bit q, bit r> {
   def "" : MVE_VxSHL_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, q, r>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar
                          (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
                          (i32 q), (i32 r), (i32 VTI.Unsigned))),
-            (VTI.Vec (!cast<Instruction>(NAME)
-                         (VTI.Vec MQPR:$in), (i32 rGPR:$sh)))>;
+            (VTI.Vec (Inst (VTI.Vec MQPR:$in), (i32 rGPR:$sh)))>;
 
   def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar_predicated
                          (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
                          (i32 q), (i32 r), (i32 VTI.Unsigned),
                          (VTI.Pred VCCR:$mask))),
-            (VTI.Vec (!cast<Instruction>(NAME)
-                         (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
+            (VTI.Vec (Inst (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
                            ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
 }
 
 multiclass MVE_VxSHL_qr_types<string iname, bit bit_7, bit bit_17> {
   defm s8  : MVE_VxSHL_qr_p<iname, MVE_v16s8, bit_7, bit_17>;
   defm s16 : MVE_VxSHL_qr_p<iname, MVE_v8s16, bit_7, bit_17>;
   defm s32 : MVE_VxSHL_qr_p<iname, MVE_v4s32, bit_7, bit_17>;
   defm u8  : MVE_VxSHL_qr_p<iname, MVE_v16u8, bit_7, bit_17>;
   defm u16 : MVE_VxSHL_qr_p<iname, MVE_v8u16, bit_7, bit_17>;
class MVE_VCTPInst<string suffix, bits<2> size, list<dag> pattern=[]>
 
   let Constraints = "";
   let DecoderMethod = "DecodeMveVCTP";
   let validForTailPredication = 1;
 }
 
 multiclass MVE_VCTP<MVEVectorVTInfo VTI, Intrinsic intr> {
   def "": MVE_VCTPInst<VTI.BitsSuffix, VTI.Size>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
-    def : Pat<(intr rGPR:$Rn),
-              (VTI.Pred (!cast<Instruction>(NAME) rGPR:$Rn))>;
+    def : Pat<(intr rGPR:$Rn), (VTI.Pred (Inst rGPR:$Rn))>;
     def : Pat<(and (intr rGPR:$Rn), (VTI.Pred VCCR:$mask)),
-              (VTI.Pred (!cast<Instruction>(NAME) rGPR:$Rn, ARMVCCThen, VCCR:$mask))>;
+              (VTI.Pred (Inst rGPR:$Rn, ARMVCCThen, VCCR:$mask))>;
   }
 }
 
 defm MVE_VCTP8  : MVE_VCTP<MVE_v16i8, int_arm_mve_vctp8>;
 defm MVE_VCTP16 : MVE_VCTP<MVE_v8i16, int_arm_mve_vctp16>;
 defm MVE_VCTP32 : MVE_VCTP<MVE_v4i32, int_arm_mve_vctp32>;
 defm MVE_VCTP64 : MVE_VCTP<MVE_v2i64, int_arm_mve_vctp64>;
 

 class MVE_VLDRSTR_rq_b<MVE_ldst_direction dir, MVE_memsz memsz,
                        string asm, string suffix, bit U, bits<2> size>
   : MVE_VLDRSTR_rq<dir, memsz, U, size, 0, asm, suffix, 0>;
 
 // Multiclasses wrapping that to add ISel patterns for intrinsics.
 multiclass MVE_VLDR_rq_w<MVE_memsz memsz, list<MVEVectorVTInfo> VTIs> {
   defm "": MVE_VLDRSTR_rq_w<MVE_ld, memsz, "vldr" # memsz.MnemonicLetter,
                             VTIs[0].Suffix, VTIs[0].Unsigned, VTIs[0].Size>;
+  defvar Inst = !cast<Instruction>(NAME);
+  defvar InstU = !cast<Instruction>(NAME # "_u");
+
   foreach VTI = VTIs in
   foreach UnsignedFlag = !if(!eq(VTI.Size, memsz.encoding),
                              [0,1], [VTI.Unsigned]) in {
     def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag)),
-              (VTI.Vec (!cast<Instruction>(NAME#"_u") GPR:$base, MQPR:$offsets))>;
+              (VTI.Vec (InstU GPR:$base, MQPR:$offsets))>;
     def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag)),
-              (VTI.Vec (!cast<Instruction>(NAME) GPR:$base, MQPR:$offsets))>;
+              (VTI.Vec (Inst GPR:$base, MQPR:$offsets))>;
     def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag, (VTI.Pred VCCR:$pred))),
-              (VTI.Vec (!cast<Instruction>(NAME#"_u") GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
+              (VTI.Vec (InstU GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
     def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag, (VTI.Pred VCCR:$pred))),
-              (VTI.Vec (!cast<Instruction>(NAME) GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
+              (VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
   }
 }
 multiclass MVE_VLDR_rq_b<list<MVEVectorVTInfo> VTIs> {
   def "": MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb",
                            VTIs[0].Suffix, VTIs[0].Unsigned, VTIs[0].Size>;
+  defvar Inst = !cast<Instruction>(NAME);
+
   foreach VTI = VTIs in {
     def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned)),
-              (VTI.Vec (!cast<Instruction>(NAME) GPR:$base, MQPR:$offsets))>;
+              (VTI.Vec (Inst GPR:$base, MQPR:$offsets))>;
     def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned, (VTI.Pred VCCR:$pred))),
-              (VTI.Vec (!cast<Instruction>(NAME) GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
+              (VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
   }
 }
 multiclass MVE_VSTR_rq_w<MVE_memsz memsz, list<MVEVectorVTInfo> VTIs> {
   defm "": MVE_VLDRSTR_rq_w<MVE_st, memsz, "vstr" # memsz.MnemonicLetter,
                             VTIs[0].BitsSuffix, 0, VTIs[0].Size>;
+  defvar Inst = !cast<Instruction>(NAME);
+  defvar InstU = !cast<Instruction>(NAME # "_u");
+
   foreach VTI = VTIs in {
     def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0),
-              (!cast<Instruction>(NAME#"_u") MQPR:$data, GPR:$base, MQPR:$offsets)>;
+              (InstU MQPR:$data, GPR:$base, MQPR:$offsets)>;
     def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift),
-              (!cast<Instruction>(NAME) MQPR:$data, GPR:$base, MQPR:$offsets)>;
+              (Inst MQPR:$data, GPR:$base, MQPR:$offsets)>;
     def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0, (VTI.Pred VCCR:$pred)),
-              (!cast<Instruction>(NAME#"_u") MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
+              (InstU MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
     def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift, (VTI.Pred VCCR:$pred)),
-              (!cast<Instruction>(NAME) MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
+              (Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
   }
 }
 multiclass MVE_VSTR_rq_b<list<MVEVectorVTInfo> VTIs> {
   def "": MVE_VLDRSTR_rq_b<MVE_st, MVE_memB, "vstrb",
                            VTIs[0].BitsSuffix, 0, VTIs[0].Size>;
+  defvar Inst = !cast<Instruction>(NAME);
+
   foreach VTI = VTIs in {
     def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0),
-              (!cast<Instruction>(NAME) MQPR:$data, GPR:$base, MQPR:$offsets)>;
+              (Inst MQPR:$data, GPR:$base, MQPR:$offsets)>;
     def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0, (VTI.Pred VCCR:$pred)),
-              (!cast<Instruction>(NAME) MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
+              (Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
   }
 }
 
 // Actually define all the loads and stores in this family.
 
 defm MVE_VLDRBU8_rq : MVE_VLDR_rq_b<[MVE_v16u8,MVE_v16s8]>;
 defm MVE_VLDRBU16_rq: MVE_VLDR_rq_b<[MVE_v8u16]>;
 defm MVE_VLDRBS16_rq: MVE_VLDR_rq_b<[MVE_v8s16]>;

 // Multiclasses wrapping that one, adding selection patterns for the
 // non-writeback loads and all the stores. (The writeback loads must
 // deliver multiple output values, so they have to be selected by C++
 // code.)
 multiclass MVE_VLDR_qi<MVE_memsz memsz, MVEVectorVTInfo AVTI,
                        list<MVEVectorVTInfo> DVTIs> {
   defm "" : MVE_VLDRSTR_qi_m<MVE_ld, memsz, "vldr" # memsz.MnemonicLetter,
                              "u" # memsz.TypeBits>;
+  defvar Inst = !cast<Instruction>(NAME);
 
   foreach DVTI = DVTIs in {
     def : Pat<(DVTI.Vec (int_arm_mve_vldr_gather_base
                  (AVTI.Vec MQPR:$addr), (i32 imm:$offset))),
-              (DVTI.Vec (!cast<Instruction>(NAME)
-                 (AVTI.Vec MQPR:$addr), (i32 imm:$offset)))>;
+              (DVTI.Vec (Inst (AVTI.Vec MQPR:$addr), (i32 imm:$offset)))>;
     def : Pat<(DVTI.Vec (int_arm_mve_vldr_gather_base_predicated
                  (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (AVTI.Pred VCCR:$pred))),
-              (DVTI.Vec (!cast<Instruction>(NAME)
-                 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), ARMVCCThen, VCCR:$pred))>;
+              (DVTI.Vec (Inst (AVTI.Vec MQPR:$addr), (i32 imm:$offset),
+                        ARMVCCThen, VCCR:$pred))>;
   }
 }
 multiclass MVE_VSTR_qi<MVE_memsz memsz, MVEVectorVTInfo AVTI,
                        list<MVEVectorVTInfo> DVTIs> {
   defm "" : MVE_VLDRSTR_qi_m<MVE_st, memsz, "vstr" # memsz.MnemonicLetter,
                              !cast<string>(memsz.TypeBits)>;
+  defvar Inst = !cast<Instruction>(NAME);
+  defvar InstPre = !cast<Instruction>(NAME # "_pre");
 
   foreach DVTI = DVTIs in {
     def : Pat<(int_arm_mve_vstr_scatter_base
                 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data)),
-              (!cast<Instruction>(NAME)
-               (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr), (i32 imm:$offset))>;
+              (Inst (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
+                    (i32 imm:$offset))>;
     def : Pat<(int_arm_mve_vstr_scatter_base_predicated
                 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred)),
-              (!cast<Instruction>(NAME)
-                (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr), (i32 imm:$offset), ARMVCCThen, VCCR:$pred)>;
+              (Inst (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
+                    (i32 imm:$offset), ARMVCCThen, VCCR:$pred)>;
     def : Pat<(AVTI.Vec (int_arm_mve_vstr_scatter_base_wb
                 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data))),
-              (AVTI.Vec (!cast<Instruction>(NAME # "_pre")
-                 (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr), (i32 imm:$offset)))>;
+              (AVTI.Vec (InstPre (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
+                                 (i32 imm:$offset)))>;
     def : Pat<(AVTI.Vec (int_arm_mve_vstr_scatter_base_wb_predicated
                 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred))),
-              (AVTI.Vec (!cast<Instruction>(NAME # "_pre")
-                 (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr), (i32 imm:$offset), ARMVCCThen, VCCR:$pred))>;
+              (AVTI.Vec (InstPre (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
+                                 (i32 imm:$offset), ARMVCCThen, VCCR:$pred))>;
   }
 }
 
 // Actual instruction definitions.
 defm MVE_VLDRWU32_qi: MVE_VLDR_qi<MVE_memW, MVE_v4i32, [MVE_v4i32,MVE_v4f32]>;
 defm MVE_VLDRDU64_qi: MVE_VLDR_qi<MVE_memD, MVE_v2i64, [MVE_v2i64,MVE_v2f64]>;
 defm MVE_VSTRW32_qi:  MVE_VSTR_qi<MVE_memW, MVE_v4i32, [MVE_v4i32,MVE_v4f32]>;
 defm MVE_VSTRD64_qi:  MVE_VSTR_qi<MVE_memD, MVE_v2i64, [MVE_v2i64,MVE_v2f64]>;

 // difference. So we permit all of vldrh.16, vldrh.u16, vldrh.s16,
 // vldrh.f16 and treat them all as equivalent to the canonical
 // spelling (which happens to be .u16 for loads, and just .16 for
 // stores).
 
 foreach vpt_cond = ["", "t", "e"] in
 foreach memsz = [MVE_memB, MVE_memH, MVE_memW, MVE_memD] in
 foreach suffix = memsz.suffixes in {
+  // Define an alias with every suffix in the list, except for the one
+  // used by the real Instruction record (i.e. the one that all the
+  // rest are aliases *for*).
 
-  // These foreaches are conceptually ifs, implemented by iterating a
-  // dummy variable over a list with 0 or 1 elements depending on the
-  // condition. The idea is to iterate over _nearly_ all the suffixes
-  // in memsz.suffixes, but omit the one we want all the others to alias.
-
-  foreach _ = !if(!ne(suffix, memsz.CanonLoadSuffix), [1], []<int>) in
+  if !ne(suffix, memsz.CanonLoadSuffix) then {
     def : MnemonicAlias<
       "vldr" # memsz.MnemonicLetter # vpt_cond # suffix,
       "vldr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonLoadSuffix>;
+  }
 
-  foreach _ = !if(!ne(suffix, memsz.CanonStoreSuffix), [1], []<int>) in
+  if !ne(suffix, memsz.CanonStoreSuffix) then {
     def : MnemonicAlias<
       "vstr" # memsz.MnemonicLetter # vpt_cond # suffix,
       "vstr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonStoreSuffix>;
   }
+}
 
 // end of MVE predicable load/store
 
 class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
   : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
   bits<3> fc;
   bits<4> Mk;
   bits<3> Qn;