[llvm-exegesis][NFC] internal changes

[gchatelet]

Summary

BitVectors are now cached to lower memory utilization.
Instructions have reference semantics.

[courbet]

llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp

17–18

Let's take Instr by pointer to avoid potentially binding to temporaries.

llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp

86

push_back(make_unique) ? I don't think there's a good reason to new here.

llvm/tools/llvm-exegesis/lib/MCInstrDescView.h

97

The name is a bit misleading. To me, an XXXBitVector is a BitVector. BitVectorCache would be better I think.

98

Doc ? This is not obvious.

101

SmallVector<T, 0> ? Why not std::vector ?

109–118

can this be private ?

122

Move this to the top ?

[gchatelet]

• Address comments

llvm/tools/llvm-exegesis/lib/CodeTemplate.h

 #include "MCInstrDescView.h"
 #include "llvm/ADT/BitmaskEnum.h"
 
 namespace llvm {
 namespace exegesis {
 
 // A template for an Instruction holding values for each of its Variables.
 struct InstructionTemplate {
-  InstructionTemplate(const Instruction &Instr);
+  InstructionTemplate(const Instruction *Instr);
 
   InstructionTemplate(const InstructionTemplate &);            // default
   InstructionTemplate &operator=(const InstructionTemplate &); // default
   InstructionTemplate(InstructionTemplate &&);                 // default
   InstructionTemplate &operator=(InstructionTemplate &&);      // default
 
   unsigned getOpcode() const;
   MCOperand &getValueFor(const Variable &Var);
   const MCOperand &getValueFor(const Variable &Var) const;
   MCOperand &getValueFor(const Operand &Op);
   const MCOperand &getValueFor(const Operand &Op) const;
   bool hasImmediateVariables() const;
+  const Instruction &getInstr() const { return *Instr; }
+  ArrayRef<MCOperand> getVariableValues() const { return VariableValues; }
 
   // Builds an MCInst from this InstructionTemplate setting its operands
   // to the corresponding variable values. Precondition: All VariableValues must
   // be set.
   MCInst build() const;
 
-  Instruction Instr;
+private:
+  const Instruction *Instr;
   SmallVector<MCOperand, 4> VariableValues;
 };
 
 enum class ExecutionMode : uint8_t {
   UNKNOWN = 0U,
   // The instruction is always serial because implicit Use and Def alias.
   // e.g. AAA (alias via EFLAGS)
   ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS = 1u << 0,

llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp

 //===-- CodeTemplate.cpp ----------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeTemplate.h"
 
 namespace llvm {
 namespace exegesis {
 
 CodeTemplate::CodeTemplate(CodeTemplate &&) = default;
 
 CodeTemplate &CodeTemplate::operator=(CodeTemplate &&) = default;
 
-InstructionTemplate::InstructionTemplate(const Instruction &Instr)
-    : Instr(Instr), VariableValues(Instr.Variables.size()) {}
+InstructionTemplate::InstructionTemplate(const Instruction *Instr)
+    : Instr(Instr), VariableValues(Instr->Variables.size()) {}
 
 InstructionTemplate::InstructionTemplate(InstructionTemplate &&) = default;
 
 InstructionTemplate &InstructionTemplate::
 operator=(InstructionTemplate &&) = default;
 
 InstructionTemplate::InstructionTemplate(const InstructionTemplate &) = default;
 
 InstructionTemplate &InstructionTemplate::
 operator=(const InstructionTemplate &) = default;
 
 unsigned InstructionTemplate::getOpcode() const {
-  return Instr.Description->getOpcode();
+  return Instr->Description.getOpcode();
 }
 
 MCOperand &InstructionTemplate::getValueFor(const Variable &Var) {
   return VariableValues[Var.getIndex()];
 }
 
 const MCOperand &InstructionTemplate::getValueFor(const Variable &Var) const {
   return VariableValues[Var.getIndex()];
 }
 
 MCOperand &InstructionTemplate::getValueFor(const Operand &Op) {
-  return getValueFor(Instr.Variables[Op.getVariableIndex()]);
+  return getValueFor(Instr->Variables[Op.getVariableIndex()]);
 }
 
 const MCOperand &InstructionTemplate::getValueFor(const Operand &Op) const {
-  return getValueFor(Instr.Variables[Op.getVariableIndex()]);
+  return getValueFor(Instr->Variables[Op.getVariableIndex()]);
 }
 
 bool InstructionTemplate::hasImmediateVariables() const {
-  return any_of(Instr.Variables, [this](const Variable &Var) {
-    return Instr.getPrimaryOperand(Var).isImmediate();
+  return any_of(Instr->Variables, [this](const Variable &Var) {
+    return Instr->getPrimaryOperand(Var).isImmediate();
   });
 }
 
 MCInst InstructionTemplate::build() const {
   MCInst Result;
-  Result.setOpcode(Instr.Description->Opcode);
-  for (const auto &Op : Instr.Operands)
+  Result.setOpcode(Instr->Description.Opcode);
+  for (const auto &Op : Instr->Operands)
     if (Op.isExplicit())
       Result.addOperand(getValueFor(Op));
   return Result;
 }
 
 bool isEnumValue(ExecutionMode Execution) {
   return isPowerOf2_32(static_cast<uint32_t>(Execution));
 }

llvm/tools/llvm-exegesis/lib/Latency.cpp

const char *Description;
      "Repeating a single explicitly serial instruction"},
     {ExecutionMode::SERIAL_VIA_MEMORY_INSTR |
          ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR,
      "Repeating two instructions"},
 };
 
 static constexpr size_t kMaxAliasingInstructions = 10;
 
-static std::vector<Instruction>
-computeAliasingInstructions(const LLVMState &State, const Instruction &Instr,
+static std::vector<const Instruction *>
+computeAliasingInstructions(const LLVMState &State, const Instruction *Instr,
                             size_t MaxAliasingInstructions,
                             const BitVector &ForbiddenRegisters) {
   // Randomly iterate the set of instructions.
   std::vector<unsigned> Opcodes;
   Opcodes.resize(State.getInstrInfo().getNumOpcodes());
   std::iota(Opcodes.begin(), Opcodes.end(), 0U);
   std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
 
-  std::vector<Instruction> AliasingInstructions;
+  std::vector<const Instruction *> AliasingInstructions;
   for (const unsigned OtherOpcode : Opcodes) {
-    if (OtherOpcode == Instr.Description->getOpcode())
+    if (OtherOpcode == Instr->Description.getOpcode())
       continue;
     const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode);
     if (OtherInstr.hasMemoryOperands())
       continue;
-    if (Instr.hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
-      AliasingInstructions.push_back(OtherInstr);
+    if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
+      AliasingInstructions.push_back(&OtherInstr);
     if (AliasingInstructions.size() >= MaxAliasingInstructions)
       break;
   }
   return AliasingInstructions;
 }
 
 static ExecutionMode getExecutionModes(const Instruction &Instr,
                                        const BitVector &ForbiddenRegisters) {
if (Instr.hasAliasingRegisters(ForbiddenRegisters))
       EM |= ExecutionMode::SERIAL_VIA_EXPLICIT_REGS;
     if (Instr.hasOneUseOrOneDef())
       EM |= ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR;
   }
   return EM;
 }
 
 static void appendCodeTemplates(const LLVMState &State,
-                                const Instruction &Instr,
+                                const Instruction *Instr,
                                 const BitVector &ForbiddenRegisters,
                                 ExecutionMode ExecutionModeBit,
                                 StringRef ExecutionClassDescription,
                                 std::vector<CodeTemplate> &CodeTemplates) {
   assert(isEnumValue(ExecutionModeBit) && "Bit must be a power of two");
   switch (ExecutionModeBit) {
   case ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS:
     // Nothing to do, the instruction is always serial.
static void appendCodeTemplates(const LLVMState &State,
   case ExecutionMode::SERIAL_VIA_MEMORY_INSTR: {
     // Select back-to-back memory instruction.
     // TODO: Implement me.
     return;
   }
   case ExecutionMode::SERIAL_VIA_EXPLICIT_REGS: {
     // Making the execution of this instruction serial by selecting one def
     // register to alias with one use register.
-    const AliasingConfigurations SelfAliasing(Instr, Instr);
+    const AliasingConfigurations SelfAliasing(*Instr, *Instr);
     assert(!SelfAliasing.empty() && !SelfAliasing.hasImplicitAliasing() &&
            "Instr must alias itself explicitly");
     InstructionTemplate IT(Instr);
     // This is a self aliasing instruction so defs and uses are from the same
     // instance, hence twice IT in the following call.
     setRandomAliasing(SelfAliasing, IT, IT);
     CodeTemplate CT;
     CT.Execution = ExecutionModeBit;
     CT.Info = ExecutionClassDescription;
     CT.Instructions.push_back(std::move(IT));
     CodeTemplates.push_back(std::move(CT));
     return;
   }
   case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR: {
     // Select back-to-back non-memory instruction.
-    for (const auto OtherInstr : computeAliasingInstructions(
+    for (const auto *OtherInstr : computeAliasingInstructions(
              State, Instr, kMaxAliasingInstructions, ForbiddenRegisters)) {
-      const AliasingConfigurations Forward(Instr, OtherInstr);
-      const AliasingConfigurations Back(OtherInstr, Instr);
+      const AliasingConfigurations Forward(*Instr, *OtherInstr);
+      const AliasingConfigurations Back(*OtherInstr, *Instr);
       InstructionTemplate ThisIT(Instr);
       InstructionTemplate OtherIT(OtherInstr);
       if (!Forward.hasImplicitAliasing())
         setRandomAliasing(Forward, ThisIT, OtherIT);
       if (!Back.hasImplicitAliasing())
         setRandomAliasing(Back, OtherIT, ThisIT);
       CodeTemplate CT;
       CT.Execution = ExecutionModeBit;

 
 Expected<std::vector<CodeTemplate>>
 LatencySnippetGenerator::generateCodeTemplates(
     const Instruction &Instr, const BitVector &ForbiddenRegisters) const {
   std::vector<CodeTemplate> Results;
   const ExecutionMode EM = getExecutionModes(Instr, ForbiddenRegisters);
   for (const auto EC : kExecutionClasses) {
     for (const auto ExecutionModeBit : getExecutionModeBits(EM & EC.Mask))
-      appendCodeTemplates(State, Instr, ForbiddenRegisters, ExecutionModeBit,
+      appendCodeTemplates(State, &Instr, ForbiddenRegisters, ExecutionModeBit,
                           EC.Description, Results);
     if (!Results.empty())
       break;
   }
   if (Results.empty())
     return make_error<Failure>(
         "No strategy found to make the execution serial");
   return std::move(Results);

llvm/tools/llvm-exegesis/lib/MCInstrDescView.h

 /// associated to them so the instruction can be fully defined by reading its
 /// Variables.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
 #define LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
 
+#include <memory>
 #include <random>
 #include <unordered_map>
 
 #include "RegisterAliasing.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
struct Variable {
   // Returns whether this Variable has more than one Operand linked to it.
   bool hasTiedOperands() const;
 
   // The indices of the operands tied to this Variable.
   SmallVector<unsigned, 2> TiedOperands;
 
   // The index of this Variable in Instruction.Variables and its associated
   // Value in InstructionBuilder.VariableValues.
-  int Index = -1;
+  Optional<uint8_t> Index;
 };
 
 // MCOperandInfo can only represents Explicit operands. This object gives a
 // uniform view of Implicit and Explicit Operands.
 // - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.
 // - Tracker: is set for Register Operands and is used to keep track of possible
 // registers and the registers reachable from them (aliasing registers).
 // - Info: a shortcut for MCInstrDesc::operands()[Index].
struct Operand {
   unsigned getIndex() const;
   unsigned getTiedToIndex() const;
   unsigned getVariableIndex() const;
   unsigned getImplicitReg() const;
   const RegisterAliasingTracker &getRegisterAliasing() const;
   const MCOperandInfo &getExplicitOperandInfo() const;
 
   // Please use the accessors above and not the following fields.
-  int Index = -1;
+  Optional<uint8_t> Index;
   bool IsDef = false;
   const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
   const MCOperandInfo *Info = nullptr;              // Set for Explicit Op.
-  int TiedToIndex = -1;                             // Set for Reg&Explicit Op.
+  Optional<uint8_t> TiedToIndex;                    // Set for Reg&Explicit Op.
   const MCPhysReg *ImplicitReg = nullptr;           // Set for Implicit Op.
-  int VariableIndex = -1;                           // Set for Explicit Op.
+  Optional<uint8_t> VariableIndex;                  // Set for Explicit Op.
+};
+
+/// A cache of BitVector to reuse between Instructions.
+/// The cache will only be exercised during Instruction initialization.
+/// For X86, this is ~160 unique vectors for all of the ~15K Instructions.
+struct BitVectorCache {
+  // Finds or allocates the provided BitVector in the cache and retrieves it's
+  // unique instance.
+  const BitVector *getUnique(BitVector &&BV) const;
+
+private:
+  mutable std::vector<std::unique_ptr<BitVector>> Cache;
 };
 
 // A view over an MCInstrDesc offering a convenient interface to compute
 // Register aliasing.
 struct Instruction {
-  Instruction(const MCInstrInfo &InstrInfo,
-              const RegisterAliasingTrackerCache &RATC, unsigned Opcode);
+  // Create an instruction for a particular Opcode.
+  static std::unique_ptr<Instruction>
+  create(const MCInstrInfo &InstrInfo, const RegisterAliasingTrackerCache &RATC,
+         const BitVectorCache &BVC, unsigned Opcode);
+
+  // Prevent copy or move, instructions are allocated once and cached.
+  Instruction(const Instruction &) = delete;
+  Instruction(Instruction &&) = delete;
+  Instruction &operator=(const Instruction &) = delete;
+  Instruction &operator=(Instruction &&) = delete;
 
   // Returns the Operand linked to this Variable.
   // In case the Variable is tied, the primary (i.e. Def) Operand is returned.
   const Operand &getPrimaryOperand(const Variable &Var) const;
 
   // Whether this instruction is self aliasing through its tied registers.
   // Repeating this instruction is guaranteed to executes sequentially.
   bool hasTiedRegisters() const;
 
   // Whether this instruction is self aliasing through its implicit registers.
   // Repeating this instruction is guaranteed to executes sequentially.
   bool hasAliasingImplicitRegisters() const;
struct Instruction {
   // instruction that aliases one of these.
   bool hasOneUseOrOneDef() const;
 
   // Convenient function to help with debugging.
   void dump(const MCRegisterInfo &RegInfo,
             const RegisterAliasingTrackerCache &RATC,
             raw_ostream &Stream) const;
 
-  const MCInstrDesc *Description; // Never nullptr.
-  StringRef Name;                 // The name of this instruction.
-  SmallVector<Operand, 8> Operands;
-  SmallVector<Variable, 4> Variables;
-  BitVector ImplDefRegs; // The set of aliased implicit def registers.
-  BitVector ImplUseRegs; // The set of aliased implicit use registers.
-  BitVector AllDefRegs;  // The set of all aliased def registers.
-  BitVector AllUseRegs;  // The set of all aliased use registers.
+  const MCInstrDesc &Description;
+  const StringRef Name; // The name of this instruction.
+  const SmallVector<Operand, 8> Operands;
+  const SmallVector<Variable, 4> Variables;
+  const BitVector &ImplDefRegs; // The set of aliased implicit def registers.
+  const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
+  const BitVector &AllDefRegs;  // The set of all aliased def registers.
+  const BitVector &AllUseRegs;  // The set of all aliased use registers.
+private:
+  Instruction(const MCInstrDesc *Description, StringRef Name,
+              SmallVector<Operand, 8> Operands,
+              SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
+              const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
+              const BitVector *AllUseRegs);
 };
 
 // Instructions are expensive to instantiate. This class provides a cache of
 // Instructions with lazy construction.
 struct InstructionsCache {
   InstructionsCache(const MCInstrInfo &InstrInfo,
                     const RegisterAliasingTrackerCache &RATC);
 
   // Returns the Instruction object corresponding to this Opcode.
   const Instruction &getInstr(unsigned Opcode) const;
 
 private:
   const MCInstrInfo &InstrInfo;
   const RegisterAliasingTrackerCache &RATC;
   mutable std::unordered_map<unsigned, std::unique_ptr<Instruction>>
       Instructions;
+  const BitVectorCache BVC;
 };
 
 // Represents the assignment of a Register to an Operand.
 struct RegisterOperandAssignment {
   RegisterOperandAssignment(const Operand *Operand, MCPhysReg Reg)
       : Op(Operand), Reg(Reg) {}
 
   const Operand *Op; // Pointer to an Explicit Register Operand.

llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp

 #include <map>
 #include <tuple>
 
 #include "llvm/ADT/STLExtras.h"
 
 namespace llvm {
 namespace exegesis {
 
-unsigned Variable::getIndex() const {
-  assert(Index >= 0 && "Index must be set");
-  return Index;
-}
+unsigned Variable::getIndex() const { return *Index; }
 
 unsigned Variable::getPrimaryOperandIndex() const {
   assert(!TiedOperands.empty());
   return TiedOperands[0];
 }
 
 bool Variable::hasTiedOperands() const {
   assert(TiedOperands.size() <= 2 &&
          "No more than two operands can be tied together");
   // By definition only Use and Def operands can be tied together.
   // TiedOperands[0] is the Def operand (LLVM stores defs first).
   // TiedOperands[1] is the Use operand.
   return TiedOperands.size() > 1;
 }
 
-unsigned Operand::getIndex() const {
-  assert(Index >= 0 && "Index must be set");
-  return Index;
-}
+unsigned Operand::getIndex() const { return *Index; }
 
 bool Operand::isExplicit() const { return Info; }
 
 bool Operand::isImplicit() const { return !Info; }
 
 bool Operand::isImplicitReg() const { return ImplicitReg; }
 
 bool Operand::isDef() const { return IsDef; }
 
 bool Operand::isUse() const { return !IsDef; }
 
 bool Operand::isReg() const { return Tracker; }
 
-bool Operand::isTied() const { return TiedToIndex >= 0; }
+bool Operand::isTied() const { return TiedToIndex.hasValue(); }
 
-bool Operand::isVariable() const { return VariableIndex >= 0; }
+bool Operand::isVariable() const { return VariableIndex.hasValue(); }
 
 bool Operand::isMemory() const {
   return isExplicit() &&
          getExplicitOperandInfo().OperandType == MCOI::OPERAND_MEMORY;
 }
 
 bool Operand::isImmediate() const {
   return isExplicit() &&
          getExplicitOperandInfo().OperandType == MCOI::OPERAND_IMMEDIATE;
 }
 
-unsigned Operand::getTiedToIndex() const {
-  assert(isTied() && "Operand must be tied to get the tied index");
-  assert(TiedToIndex >= 0 && "TiedToIndex must be set");
-  return TiedToIndex;
-}
+unsigned Operand::getTiedToIndex() const { return *TiedToIndex; }
 
-unsigned Operand::getVariableIndex() const {
-  assert(isVariable() && "Operand must be variable to get the Variable index");
-  assert(VariableIndex >= 0 && "VariableIndex must be set");
-  return VariableIndex;
-}
+unsigned Operand::getVariableIndex() const { return *VariableIndex; }
 
 unsigned Operand::getImplicitReg() const {
   assert(ImplicitReg);
   return *ImplicitReg;
 }
 
 const RegisterAliasingTracker &Operand::getRegisterAliasing() const {
   assert(Tracker);
   return *Tracker;
 }
 
 const MCOperandInfo &Operand::getExplicitOperandInfo() const {
   assert(Info);
   return *Info;
 }
 
-Instruction::Instruction(const MCInstrInfo &InstrInfo,
-                         const RegisterAliasingTrackerCache &RATC,
-                         unsigned Opcode)
-    : Description(&InstrInfo.get(Opcode)), Name(InstrInfo.getName(Opcode)) {
+const BitVector *BitVectorCache::getUnique(BitVector &&BV) const {
+  for (const auto &Entry : Cache)
+    if (*Entry == BV)
+      return Entry.get();
+  Cache.push_back(std::make_unique<BitVector>());
+  auto &Entry = Cache.back();
+  Entry->swap(BV);
+  return Entry.get();
+}
+
+Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
+                         SmallVector<Operand, 8> Operands,
+                         SmallVector<Variable, 4> Variables,
+                         const BitVector *ImplDefRegs,
+                         const BitVector *ImplUseRegs,
+                         const BitVector *AllDefRegs,
+                         const BitVector *AllUseRegs)
+    : Description(*Description), Name(Name), Operands(std::move(Operands)),
+      Variables(std::move(Variables)), ImplDefRegs(*ImplDefRegs),
+      ImplUseRegs(*ImplUseRegs), AllDefRegs(*AllDefRegs),
+      AllUseRegs(*AllUseRegs) {}
+
+std::unique_ptr<Instruction>
+Instruction::create(const MCInstrInfo &InstrInfo,
+                    const BitVectorCache &BVC, unsigned Opcode) {
+  const llvm::MCInstrDesc *const Description = &InstrInfo.get(Opcode);
   unsigned OpIndex = 0;
+  SmallVector<Operand, 8> Operands;
+  SmallVector<Variable, 4> Variables;
   for (; OpIndex < Description->getNumOperands(); ++OpIndex) {
     const auto &OpInfo = Description->opInfo_begin()[OpIndex];
     Operand Operand;
     Operand.Index = OpIndex;
     Operand.IsDef = (OpIndex < Description->getNumDefs());
     // TODO(gchatelet): Handle isLookupPtrRegClass.
     if (OpInfo.RegClass >= 0)
       Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);
-    Operand.TiedToIndex =
-        Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
+    int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
+    assert(TiedToIndex == -1 ||
+           TiedToIndex < std::numeric_limits<uint8_t>::max());
+    if (TiedToIndex >= 0)
+      Operand.TiedToIndex = TiedToIndex;
     Operand.Info = &OpInfo;
     Operands.push_back(Operand);
   }
   for (const MCPhysReg *MCPhysReg = Description->getImplicitDefs();
        MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) {
     Operand Operand;
     Operand.Index = OpIndex;
     Operand.IsDef = true;
     Operand.Tracker = &RATC.getRegister(*MCPhysReg);
     Operand.ImplicitReg = MCPhysReg;
     Operands.push_back(Operand);
   }
   for (const MCPhysReg *MCPhysReg = Description->getImplicitUses();
        MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) {
     Operand Operand;
     Operand.Index = OpIndex;
     Operand.IsDef = false;
     Operand.Tracker = &RATC.getRegister(*MCPhysReg);
     Operand.ImplicitReg = MCPhysReg;
     Operands.push_back(Operand);
   }
-  // Assigning Variables to non tied explicit operands.
   Variables.reserve(Operands.size()); // Variables.size() <= Operands.size()
+  // Assigning Variables to non tied explicit operands.
   for (auto &Op : Operands)
     if (Op.isExplicit() && !Op.isTied()) {
       const size_t VariableIndex = Variables.size();
+      assert(VariableIndex < std::numeric_limits<uint8_t>::max());
       Op.VariableIndex = VariableIndex;
       Variables.emplace_back();
       Variables.back().Index = VariableIndex;
     }
   // Assigning Variables to tied operands.
   for (auto &Op : Operands)
-    if (Op.isTied())
+    if (Op.isExplicit() && Op.isTied())
       Op.VariableIndex = Operands[Op.getTiedToIndex()].getVariableIndex();
   // Assigning Operands to Variables.
   for (auto &Op : Operands)
     if (Op.isVariable())
       Variables[Op.getVariableIndex()].TiedOperands.push_back(Op.getIndex());
   // Processing Aliasing.
-  ImplDefRegs = RATC.emptyRegisters();
-  ImplUseRegs = RATC.emptyRegisters();
-  AllDefRegs = RATC.emptyRegisters();
-  AllUseRegs = RATC.emptyRegisters();
+  BitVector ImplDefRegs = RATC.emptyRegisters();
+  BitVector ImplUseRegs = RATC.emptyRegisters();
+  BitVector AllDefRegs = RATC.emptyRegisters();
+  BitVector AllUseRegs = RATC.emptyRegisters();
   for (const auto &Op : Operands) {
     if (Op.isReg()) {
       const auto &AliasingBits = Op.getRegisterAliasing().aliasedBits();
       if (Op.isDef())
         AllDefRegs |= AliasingBits;
       if (Op.isUse())
         AllUseRegs |= AliasingBits;
       if (Op.isDef() && Op.isImplicit())
         ImplDefRegs |= AliasingBits;
       if (Op.isUse() && Op.isImplicit())
         ImplUseRegs |= AliasingBits;
     }
   }
+  // Can't use make_unique because constructor is private.
+  return std::unique_ptr<Instruction>(new Instruction(
+      Description, InstrInfo.getName(Opcode), std::move(Operands),
+      std::move(Variables), BVC.getUnique(std::move(ImplDefRegs)),
+      BVC.getUnique(std::move(ImplUseRegs)),
+      BVC.getUnique(std::move(AllDefRegs)),
+      BVC.getUnique(std::move(AllUseRegs))));
 }
 
 const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
   const auto PrimaryOperandIndex = Var.getPrimaryOperandIndex();
   assert(PrimaryOperandIndex < Operands.size());
   return Operands[PrimaryOperandIndex];
 }
 

 
 InstructionsCache::InstructionsCache(const MCInstrInfo &InstrInfo,
                                      const RegisterAliasingTrackerCache &RATC)
     : InstrInfo(InstrInfo), RATC(RATC) {}
 
 const Instruction &InstructionsCache::getInstr(unsigned Opcode) const {
   auto &Found = Instructions[Opcode];
   if (!Found)
-    Found.reset(new Instruction(InstrInfo, RATC, Opcode));
+    Found = Instruction::create(InstrInfo, RATC, BVC, Opcode);
   return *Found;
 }
 
 bool RegisterOperandAssignment::
 operator==(const RegisterOperandAssignment &Other) const {
   return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);
 }
 

llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp

const auto GetOpReg = [&IT](const Operand &Op) -> unsigned {
         return 0;
       if (Op.isImplicitReg())
         return Op.getImplicitReg();
       if (Op.isExplicit() && IT.getValueFor(Op).isReg())
         return IT.getValueFor(Op).getReg();
       return 0;
     };
     // Collect used registers that have never been def'ed.
-    for (const Operand &Op : IT.Instr.Operands) {
+    for (const Operand &Op : IT.getInstr().Operands) {
       if (Op.isUse()) {
         const unsigned Reg = GetOpReg(Op);
         if (Reg > 0 && !DefinedRegs.test(Reg)) {
           RIV.push_back(RegisterValue::zero(Reg));
           DefinedRegs.set(Reg);
         }
       }
     }
     // Mark defs as having been def'ed.
-    for (const Operand &Op : IT.Instr.Operands) {
+    for (const Operand &Op : IT.getInstr().Operands) {
       if (Op.isDef()) {
         const unsigned Reg = GetOpReg(Op);
         if (Reg > 0)
           DefinedRegs.set(Reg);
       }
     }
   }
   return RIV;
 }
 
 Expected<std::vector<CodeTemplate>>
 generateSelfAliasingCodeTemplates(const Instruction &Instr) {
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   if (SelfAliasing.empty())
     return make_error<SnippetGeneratorFailure>("empty self aliasing");
   std::vector<CodeTemplate> Result;
   Result.emplace_back();
   CodeTemplate &CT = Result.back();
-  InstructionTemplate IT(Instr);
+  InstructionTemplate IT(&Instr);
   if (SelfAliasing.hasImplicitAliasing()) {
     CT.Info = "implicit Self cycles, picking random values.";
   } else {
     CT.Info = "explicit self cycles, selecting one aliasing Conf.";
     // This is a self aliasing instruction so defs and uses are from the same
     // instance, hence twice IT in the following call.
     setRandomAliasing(SelfAliasing, IT, IT);
   }
   CT.Instructions.push_back(std::move(IT));
   return std::move(Result);
 }
 
 Expected<std::vector<CodeTemplate>>
 generateUnconstrainedCodeTemplates(const Instruction &Instr, StringRef Msg) {
   std::vector<CodeTemplate> Result;
   Result.emplace_back();
   CodeTemplate &CT = Result.back();
   CT.Info = formatv("{0}, repeating an unconstrained assignment", Msg);
-  CT.Instructions.emplace_back(Instr);
+  CT.Instructions.emplace_back(&Instr);
   return std::move(Result);
 }
 
 std::mt19937 &randomGenerator() {
   static std::random_device RandomDevice;
   static std::mt19937 RandomGenerator(RandomDevice());
   return RandomGenerator;
 }
void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
   const auto &RandomConf = randomElement(AliasingConfigurations.Configurations);
   setRegisterOperandValue(randomElement(RandomConf.Defs), DefIB);
   setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
 }
 
 void randomizeUnsetVariables(const ExegesisTarget &Target,
                              const BitVector &ForbiddenRegs,
                              InstructionTemplate &IT) {
-  for (const Variable &Var : IT.Instr.Variables) {
+  for (const Variable &Var : IT.getInstr().Variables) {
     MCOperand &AssignedValue = IT.getValueFor(Var);
     if (!AssignedValue.isValid())
-      Target.randomizeMCOperand(IT.Instr, Var, AssignedValue, ForbiddenRegs);
+      Target.randomizeMCOperand(IT.getInstr(), Var, AssignedValue,
+                                ForbiddenRegs);
   }
 }
 
 } // namespace exegesis
 } // namespace llvm

llvm/tools/llvm-exegesis/lib/Uops.cpp

static std::vector<InstructionTemplate> generateSnippetUsingStaticRenaming(
     const ArrayRef<const Variable *> TiedVariables,
     const BitVector &ForbiddenRegisters) {
   std::vector<InstructionTemplate> Instructions;
   // Assign registers to variables in a round-robin manner. This is simple but
   // ensures that the most register-constrained variable does not get starved.
   std::vector<BitVector> PossibleRegsForVar;
   for (const Variable *Var : TiedVariables) {
     assert(Var);
-    const Operand &Op = IT.Instr.getPrimaryOperand(*Var);
+    const Operand &Op = IT.getInstr().getPrimaryOperand(*Var);
     assert(Op.isReg());
     BitVector PossibleRegs = Op.getRegisterAliasing().sourceBits();
     remove(PossibleRegs, ForbiddenRegisters);
     PossibleRegsForVar.push_back(std::move(PossibleRegs));
   }
   SmallVector<int, 2> Iterators(TiedVariables.size(), 0);
   while (true) {
     InstructionTemplate TmpIT = IT;
Expected<std::vector<CodeTemplate>> UopsSnippetGenerator::generateCodeTemplates(
     const Instruction &Instr, const BitVector &ForbiddenRegisters) const {
   CodeTemplate CT;
   CT.ScratchSpacePointerInReg =
       Instr.hasMemoryOperands()
           ? State.getExegesisTarget().getScratchMemoryRegister(
                 State.getTargetMachine().getTargetTriple())
           : 0;
   const AliasingConfigurations SelfAliasing(Instr, Instr);
-  InstructionTemplate IT(Instr);
+  InstructionTemplate IT(&Instr);
   if (SelfAliasing.empty()) {
     CT.Info = "instruction is parallel, repeating a random one.";
     CT.Instructions.push_back(std::move(IT));
     instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
     return getSingleton(std::move(CT));
   }
   if (SelfAliasing.hasImplicitAliasing()) {
     CT.Info = "instruction is serial, repeating a random one.";

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

 #include "llvm/Support/FormatVariadic.h"
 
 namespace llvm {
 namespace exegesis {
 
 // Returns an error if we cannot handle the memory references in this
 // instruction.
 static Error isInvalidMemoryInstr(const Instruction &Instr) {
-  switch (Instr.Description->TSFlags & X86II::FormMask) {
+  switch (Instr.Description.TSFlags & X86II::FormMask) {
   default:
     llvm_unreachable("Unknown FormMask value");
   // These have no memory access.
   case X86II::Pseudo:
   case X86II::RawFrm:
   case X86II::AddCCFrm:
   case X86II::MRMDestReg:
   case X86II::MRMSrcReg:
static Error isInvalidMemoryInstr(const Instruction &Instr) {
   case X86II::MRM_FB:
   case X86II::MRM_FC:
   case X86II::MRM_FD:
   case X86II::MRM_FE:
   case X86II::MRM_FF:
   case X86II::RawFrmImm8:
     return Error::success();
   case X86II::AddRegFrm:
-    return (Instr.Description->Opcode == X86::POP16r ||
-            Instr.Description->Opcode == X86::POP32r ||
-            Instr.Description->Opcode == X86::PUSH16r ||
-            Instr.Description->Opcode == X86::PUSH32r)
+    return (Instr.Description.Opcode == X86::POP16r ||
+            Instr.Description.Opcode == X86::POP32r ||
+            Instr.Description.Opcode == X86::PUSH16r ||
+            Instr.Description.Opcode == X86::PUSH32r)
                ? make_error<Failure>(
                      "unsupported opcode: unsupported memory access")
                : Error::success();
   // These access memory and are handled.
   case X86II::MRMDestMem:
   case X86II::MRMSrcMem:
   case X86II::MRMSrcMem4VOp3:
   case X86II::MRMSrcMemOp4:
static Error isInvalidMemoryInstr(const Instruction &Instr) {
   case X86II::RawFrmDst:
   case X86II::RawFrmDstSrc:
     return make_error<Failure>("unsupported opcode: non uniform memory access");
   }
 }
 
 static Error IsInvalidOpcode(const Instruction &Instr) {
   const auto OpcodeName = Instr.Name;
-  if ((Instr.Description->TSFlags & X86II::FormMask) == X86II::Pseudo)
+  if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo)
     return make_error<Failure>("unsupported opcode: pseudo instruction");
   if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") ||
       OpcodeName.startswith("ADJCALLSTACK"))
     return make_error<Failure>("unsupported opcode: Push/Pop/AdjCallStack");
   if (Error Error = isInvalidMemoryInstr(Instr))
     return Error;
   // We do not handle instructions with OPERAND_PCREL.
   for (const Operand &Op : Instr.Operands)
     if (Op.isExplicit() &&
         Op.getExplicitOperandInfo().OperandType == MCOI::OPERAND_PCREL)
       return make_error<Failure>("unsupported opcode: PC relative operand");
   // We do not handle second-form X87 instructions. We only handle first-form
   // ones (_Fp), see comment in X86InstrFPStack.td.
   for (const Operand &Op : Instr.Operands)
     if (Op.isReg() && Op.isExplicit() &&
         Op.getExplicitOperandInfo().RegClass == X86::RSTRegClassID)
       return make_error<Failure>("unsupported second-form X87 instruction");
   return Error::success();
 }
 
 static unsigned getX86FPFlags(const Instruction &Instr) {
-  return Instr.Description->TSFlags & X86II::FPTypeMask;
+  return Instr.Description.TSFlags & X86II::FPTypeMask;
 }
 
 // Helper to fill a memory operand with a value.
 static void setMemOp(InstructionTemplate &IT, int OpIdx,
                      const MCOperand &OpVal) {
-  const auto Op = IT.Instr.Operands[OpIdx];
+  const auto Op = IT.getInstr().Operands[OpIdx];
   assert(Op.isExplicit() && "invalid memory pattern");
   IT.getValueFor(Op) = OpVal;
 }
 
 // Common (latency, uops) code for LEA templates. `GetDestReg` takes the
 // addressing base and index registers and returns the LEA destination register.
 static Expected<std::vector<CodeTemplate>> generateLEATemplatesCommon(
     const Instruction &Instr, const BitVector &ForbiddenRegisters,
     const LLVMState &State, const SnippetGenerator::Options &Opts,
     std::function<unsigned(unsigned, unsigned)> GetDestReg) {
   assert(Instr.Operands.size() == 6 && "invalid LEA");
-  assert(X86II::getMemoryOperandNo(Instr.Description->TSFlags) == 1 &&
+  assert(X86II::getMemoryOperandNo(Instr.Description.TSFlags) == 1 &&
          "invalid LEA");
 
   constexpr const int kDestOp = 0;
   constexpr const int kBaseOp = 1;
   constexpr const int kIndexOp = 3;
   auto PossibleDestRegs =
       Instr.Operands[kDestOp].getRegisterAliasing().sourceBits();
   remove(PossibleDestRegs, ForbiddenRegisters);
   auto PossibleBaseRegs =
       Instr.Operands[kBaseOp].getRegisterAliasing().sourceBits();
   remove(PossibleBaseRegs, ForbiddenRegisters);
   auto PossibleIndexRegs =
       Instr.Operands[kIndexOp].getRegisterAliasing().sourceBits();
   remove(PossibleIndexRegs, ForbiddenRegisters);
 
   const auto &RegInfo = State.getRegInfo();
   std::vector<CodeTemplate> Result;
   for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) {
     for (const unsigned IndexReg : PossibleIndexRegs.set_bits()) {
       for (int LogScale = 0; LogScale <= 3; ++LogScale) {
         // FIXME: Add an option for controlling how we explore immediates.
         for (const int Disp : {0, 42}) {
-          InstructionTemplate IT(Instr);
+          InstructionTemplate IT(&Instr);
           const int64_t Scale = 1ull << LogScale;
           setMemOp(IT, 1, MCOperand::createReg(BaseReg));
           setMemOp(IT, 2, MCOperand::createImm(Scale));
           setMemOp(IT, 3, MCOperand::createReg(IndexReg));
           setMemOp(IT, 4, MCOperand::createImm(Disp));
           // SegmentReg must be 0 for LEA.
           setMemOp(IT, 5, MCOperand::createReg(0));
 

 
 Expected<std::vector<CodeTemplate>>
 X86LatencySnippetGenerator::generateCodeTemplates(
     const Instruction &Instr, const BitVector &ForbiddenRegisters) const {
   if (auto E = IsInvalidOpcode(Instr))
     return std::move(E);
 
   // LEA gets special attention.
-  const auto Opcode = Instr.Description->getOpcode();
+  const auto Opcode = Instr.Description.getOpcode();
   if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r) {
     return generateLEATemplatesCommon(Instr, ForbiddenRegisters, State, Opts,
                                       [](unsigned BaseReg, unsigned IndexReg) {
                                         // We just select the same base and
                                         // output register.
                                         return BaseReg;
                                       });
   }

 
 Expected<std::vector<CodeTemplate>>
 X86UopsSnippetGenerator::generateCodeTemplates(
     const Instruction &Instr, const BitVector &ForbiddenRegisters) const {
   if (auto E = IsInvalidOpcode(Instr))
     return std::move(E);
 
   // LEA gets special attention.
-  const auto Opcode = Instr.Description->getOpcode();
+  const auto Opcode = Instr.Description.getOpcode();
   if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r) {
     // Any destination register that is not used for adddressing is fine.
     auto PossibleDestRegs =
         Instr.Operands[0].getRegisterAliasing().sourceBits();
     remove(PossibleDestRegs, ForbiddenRegisters);
     return generateLEATemplatesCommon(
         Instr, ForbiddenRegisters, State, Opts,
         [this, &PossibleDestRegs](unsigned BaseReg, unsigned IndexReg) {
void ExegesisX86Target::randomizeMCOperand(
   default:
     break;
   }
 }
 
 void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
                                            unsigned Reg,
                                            unsigned Offset) const {
-  assert(!isInvalidMemoryInstr(IT.Instr) &&
+  assert(!isInvalidMemoryInstr(IT.getInstr()) &&
          "fillMemoryOperands requires a valid memory instruction");
-  int MemOpIdx = X86II::getMemoryOperandNo(IT.Instr.Description->TSFlags);
+  int MemOpIdx = X86II::getMemoryOperandNo(IT.getInstr().Description.TSFlags);
   assert(MemOpIdx >= 0 && "invalid memory operand index");
   // getMemoryOperandNo() ignores tied operands, so we have to add them back.
   for (unsigned I = 0; I <= static_cast<unsigned>(MemOpIdx); ++I) {
-    const auto &Op = IT.Instr.Operands[I];
+    const auto &Op = IT.getInstr().Operands[I];
     if (Op.isTied() && Op.getTiedToIndex() < I) {
       ++MemOpIdx;
     }
   }
   setMemOp(IT, MemOpIdx + 0, MCOperand::createReg(Reg));    // BaseReg
   setMemOp(IT, MemOpIdx + 1, MCOperand::createImm(1));      // ScaleAmt
   setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(0));      // IndexReg
   setMemOp(IT, MemOpIdx + 3, MCOperand::createImm(Offset)); // Disp

llvm/tools/llvm-exegesis/llvm-exegesis.cpp

static std::vector<unsigned> getOpcodesOrDie(const MCInstrInfo &MCInstrInfo) {
   return Result;
 }
 
 // Generates code snippets for opcode `Opcode`.
 static Expected<std::vector<BenchmarkCode>>
 generateSnippets(const LLVMState &State, unsigned Opcode,
                  const BitVector &ForbiddenRegs) {
   const Instruction &Instr = State.getIC().getInstr(Opcode);
-  const MCInstrDesc &InstrDesc = *Instr.Description;
+  const MCInstrDesc &InstrDesc = Instr.Description;
   // Ignore instructions that we cannot run.
   if (InstrDesc.isPseudo())
     return make_error<Failure>("Unsupported opcode: isPseudo");
   if (InstrDesc.isBranch() || InstrDesc.isIndirectBranch())
     return make_error<Failure>("Unsupported opcode: isBranch/isIndirectBranch");
   if (InstrDesc.isCall() || InstrDesc.isReturn())
     return make_error<Failure>("Unsupported opcode: isCall/isReturn");
 

llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp

TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
   const unsigned Opcode = Mips::ADD;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(3));
-  EXPECT_THAT(IT.VariableValues,
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+  EXPECT_THAT(IT.getVariableValues(),
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
 }
 
 TEST_F(LatencySnippetGeneratorTest,
  ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
   // - XOR

llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
   EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], X86::EFLAGS);
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(1)); // Imm.
-  EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Immediate is not set";
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
+  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
   // - ADD16ri
   // - Op0 Explicit Def RegClass(GR16)
   // - Op1 Explicit Use RegClass(GR16) TiedToOp0
   // - Op2 Explicit Use Immediate
   // - Op3 Implicit Def Reg(EFLAGS)
   // - Var0 [Op0,Op1]
   // - Var1 [Op2]
   // - hasTiedRegisters (execution is always serial)
   // - hasAliasingRegisters
   const unsigned Opcode = X86::ADD16ri;
   EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS);
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(2));
-  EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Operand 1 is not set";
-  EXPECT_THAT(IT.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
+  EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
   // - VXORPSrr
   // - Op0 Explicit Def RegClass(VR128)
   // - Op1 Explicit Use RegClass(VR128)
   // - Op2 Explicit Use RegClass(VR128)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
   // - hasAliasingRegisters
   const unsigned Opcode = X86::VXORPSrr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(3));
-  EXPECT_THAT(IT.VariableValues,
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+  EXPECT_THAT(IT.getVariableValues(),
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
 }
 
 TEST_F(LatencySnippetGeneratorTest,
        ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
   // - VXORPSrr
TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) {
   const unsigned Opcode = X86::CMP64rr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
   for (const auto &CT : CodeTemplates) {
     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
-    ASSERT_THAT(IT.VariableValues, SizeIs(2));
-    EXPECT_THAT(IT.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
-                                         ElementsAre(IsInvalid(), IsReg())));
+    ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+    EXPECT_THAT(IT.getVariableValues(),
+                AnyOf(ElementsAre(IsReg(), IsInvalid()),
     EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
     // TODO: check that the two instructions alias each other.
   }
 }
 
 TEST_F(LatencySnippetGeneratorTest, LAHF) {
   // - LAHF
   // - Op0 Implicit Def Reg(AH)
   // - Op1 Implicit Use Reg(EFLAGS)
   const unsigned Opcode = X86::LAHF;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
   for (const auto &CT : CodeTemplates) {
     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
-    ASSERT_THAT(IT.VariableValues, SizeIs(0));
+    ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
   }
 }
 
 TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) {
   // - BNDCL32rr
   // - Op0 Explicit Use RegClass(BNDR)
   // - Op1 Explicit Use RegClass(GR32)
   // - Var0 [Op0]
   // - Var1 [Op1]
   const unsigned Opcode = X86::BNDCL32rr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("parallel"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(2));
-  EXPECT_THAT(IT.VariableValues[0], IsInvalid());
-  EXPECT_THAT(IT.VariableValues[1], IsInvalid());
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid());
+  EXPECT_THAT(IT.getVariableValues()[1], IsInvalid());
 }
 
 TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
   // - CDQ
   // - Op0 Implicit Def Reg(EAX)
   // - Op1 Implicit Def Reg(EDX)
   // - Op2 Implicit Use Reg(EAX)
   // - hasAliasingImplicitRegisters (execution is always serial)
   // - hasAliasingRegisters
   const unsigned Opcode = X86::CDQ;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("serial"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(0));
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
 }
 
 TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
   // CMOV32rr has tied variables, we enumerate the possible values to execute
   // as many in parallel as possible.
 
   // - CMOV32rr
   // - Op0 Explicit Def RegClass(GR32)
TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("static renaming"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   constexpr const unsigned kInstructionCount = 15;
   ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
   std::unordered_set<unsigned> AllDefRegisters;
   for (const auto &IT : CT.Instructions) {
-    ASSERT_THAT(IT.VariableValues, SizeIs(3));
-    AllDefRegisters.insert(IT.VariableValues[0].getReg());
+    ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+    AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
   }
   EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
       << "Each instruction writes to a different register";
 }
 
 TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
   // CMOV_GR32 has no tied variables, we make sure def and use are different
   // from each other.
TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(4));
-  EXPECT_THAT(IT.VariableValues[0].getReg(), Not(IT.VariableValues[1].getReg()))
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
+  EXPECT_THAT(IT.getVariableValues()[0].getReg(),
+              Not(IT.getVariableValues()[1].getReg()))
       << "Def is different from first Use";
-  EXPECT_THAT(IT.VariableValues[0].getReg(), Not(IT.VariableValues[2].getReg()))
+  EXPECT_THAT(IT.getVariableValues()[0].getReg(),
+              Not(IT.getVariableValues()[2].getReg()))
       << "Def is different from second Use";
-  EXPECT_THAT(IT.VariableValues[3], IsInvalid());
+  EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
 }
 
 TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
   // Mov32rm reads from memory.
   // - MOV32rm
   // - Op0 Explicit Def RegClass(GR32)
   // - Op1 Explicit Use Memory RegClass(GR8)
   // - Op2 Explicit Use Memory
TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
   ASSERT_THAT(CT.Instructions,
               SizeIs(UopsSnippetGenerator::kMinNumDifferentAddresses));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(6));
-  EXPECT_EQ(IT.VariableValues[2].getImm(), 1);
-  EXPECT_EQ(IT.VariableValues[3].getReg(), 0u);
-  EXPECT_EQ(IT.VariableValues[4].getImm(), 0);
-  EXPECT_EQ(IT.VariableValues[5].getReg(), 0u);
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
+  EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
+  EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
+  EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
+  EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
 }
 
 class FakeSnippetGenerator : public SnippetGenerator {
 public:
   FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
       : SnippetGenerator(State, Opts) {}
 
-  Instruction createInstruction(unsigned Opcode) {
+  const Instruction &getInstr(unsigned Opcode) {
     return State.getIC().getInstr(Opcode);
   }
 
+  InstructionTemplate getInstructionTemplate(unsigned Opcode) {
+    return {&getInstr(Opcode)};
+  }
+
 private:
   Expected<std::vector<CodeTemplate>>
   generateCodeTemplates(const Instruction &, const BitVector &) const override {
     return make_error<StringError>("not implemented", inconvertibleErrorCode());
   }
 };
 
 using FakeSnippetGeneratorTest = SnippetGeneratorTest<FakeSnippetGenerator>;

 }
 
 TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
   // ADD16ri:
   // explicit def 0       : reg RegClass=GR16
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
   // explicit use 2       : imm
   // implicit def         : EFLAGS
-  InstructionTemplate IT(Generator.createInstruction(X86::ADD16ri));
-  IT.getValueFor(IT.Instr.Variables[0]) = MCOperand::createReg(X86::AX);
+  InstructionTemplate IT = Generator.getInstructionTemplate(X86::ADD16ri);
+  IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
   std::vector<InstructionTemplate> Snippet;
   Snippet.push_back(std::move(IT));
   const auto RIV = Generator.computeRegisterInitialValues(Snippet);
   EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt())));
 }
 
 TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
   // ADD64rr:
   //  mov64ri rax, 42
   //  add64rr rax, rax, rbx
   // -> only rbx needs defining.
   std::vector<InstructionTemplate> Snippet;
   {
-    InstructionTemplate Mov(Generator.createInstruction(X86::MOV64ri));
-    Mov.getValueFor(Mov.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
-    Mov.getValueFor(Mov.Instr.Variables[1]) = MCOperand::createImm(42);
+    InstructionTemplate Mov = Generator.getInstructionTemplate(X86::MOV64ri);
+    Mov.getValueFor(Mov.getInstr().Variables[0]) =
+        MCOperand::createReg(X86::RAX);
+    Mov.getValueFor(Mov.getInstr().Variables[1]) = MCOperand::createImm(42);
     Snippet.push_back(std::move(Mov));
   }
   {
-    InstructionTemplate Add(Generator.createInstruction(X86::ADD64rr));
-    Add.getValueFor(Add.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
-    Add.getValueFor(Add.Instr.Variables[1]) = MCOperand::createReg(X86::RBX);
+    InstructionTemplate Add = Generator.getInstructionTemplate(X86::ADD64rr);
+    Add.getValueFor(Add.getInstr().Variables[0]) =
+        MCOperand::createReg(X86::RAX);
+    Add.getValueFor(Add.getInstr().Variables[1]) =
+        MCOperand::createReg(X86::RBX);
     Snippet.push_back(std::move(Add));
   }
 
   const auto RIV = Generator.computeRegisterInitialValues(Snippet);
   EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::RBX, APInt())));
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp

static void SetUpTestCase() {
     InitializeX86ExegesisTarget();
   }
 
   std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
     return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
                                               Value);
   }
 
+  const Instruction &getInstr(unsigned OpCode) {
+    return State.getIC().getInstr(OpCode);
+  }
+
   LLVMState State;
 };
 
 class Core2TargetTest : public X86TargetTest {
 public:
   Core2TargetTest() : X86TargetTest("") {}
 };
 
EXPECT_THAT(setRegTo(X86::FP1, APInt(4, 0x1ULL)),
               ElementsAre(IsStackAllocate(10),
                           IsMovValueToStack(X86::MOV32mi, 0x00000001UL, 0),
                           IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                           IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                           OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
 }
 
 TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
-  Instruction I(State.getInstrInfo(), State.getRATC(), X86::ADD64rm);
-  InstructionTemplate IT(I);
+  const Instruction &I = getInstr(X86::ADD64rm);
+  InstructionTemplate IT(&I);
   constexpr const int kOffset = 42;
   State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
   // Memory is operands 2-6.
   EXPECT_THAT(IT.getValueFor(I.Operands[2]), IsReg(X86::RDI));
   EXPECT_THAT(IT.getValueFor(I.Operands[3]), IsImm(1));
   EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(0));
   EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(kOffset));
   EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
 }
 
 TEST_F(Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
-  Instruction I(State.getInstrInfo(), State.getRATC(), X86::VGATHERDPSZ128rm);
-  InstructionTemplate IT(I);
+  const Instruction &I = getInstr(X86::VGATHERDPSZ128rm);
+  InstructionTemplate IT(&I);
   constexpr const int kOffset = 42;
   State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
   // Memory is operands 4-8.
   EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(X86::RDI));
   EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(1));
   EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
   EXPECT_THAT(IT.getValueFor(I.Operands[7]), IsImm(kOffset));
   EXPECT_THAT(IT.getValueFor(I.Operands[8]), IsReg(0));
 }
 
 } // namespace
 } // namespace exegesis
 } // namespace llvm