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Differential D71567

[InstCombine] Add tests for `select + mul` for power of twos. NFC
AcceptedPublic

Authored by danlark on Dec 16 2019, 1:32 PM.

Details

Reviewers
spatel
lebedev.ri
Summary

Add tests for select + mul for power of twos. NFC

Patch by Danila Kutenin. email:danilak at google.com, github:danlark1@ . I don't have commit rights.

Diff Detail

Event Timeline

danlark created this revision.Dec 16 2019, 1:32 PM
danlark retitled this revision from [InstCombine] Refactor FoldUDivAction for future usage with multiplication. NFC to [InstCombine] Add tests for `select + mul` for power of twos. NFC.Dec 16 2019, 1:33 PM
danlark edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B42594: Diff 234135.Dec 16 2019, 1:33 PM
danlark added a parent revision: D71561: [InstCombine] Refactor FoldUDivAction for future usage with multiplication. NFC.Dec 16 2019, 1:33 PM
danlark added a child revision: D71568: [InstCombine] `select + mul` -> `select + shl` with power of twos..Dec 16 2019, 1:50 PM
danlark updated this revision to Diff 234148.Dec 16 2019, 2:04 PM
danlark retitled this revision from [InstCombine] Add tests for `select + mul` for power of twos. NFC to [InstCombine] Add tests for `select + mul` for power of twos. NFC.
danlark edited the summary of this revision. (Show Details)
danlark updated this revision to Diff 234150.Dec 16 2019, 2:06 PM
This comment was removed by danlark.
Harbormaster completed remote builds in B42602: Diff 234148.Dec 16 2019, 2:07 PM
Harbormaster completed remote builds in B42604: Diff 234150.
danlark updated this revision to Diff 234151.Dec 16 2019, 2:08 PM

Trying to make chain review

Harbormaster completed remote builds in B42605: Diff 234151.Dec 16 2019, 2:11 PM
danlark updated this revision to Diff 234152.Dec 16 2019, 2:11 PM

Finally readable chain review

Harbormaster completed remote builds in B42606: Diff 234152.Dec 16 2019, 2:16 PM
lebedev.ri added a comment.Dec 16 2019, 2:27 PM

You probably want to throw in some vector undef tests as well.
(e.g. a singled lane in one of constants, the same lane in both, different lanes in each)

lebedev.ri added a comment.Dec 16 2019, 2:29 PM

Also, nuw/nsw/nuw+nsw propagation tests?

danlark updated this revision to Diff 234156.Dec 16 2019, 2:39 PM

Add nsw+nuw tests

Harbormaster completed remote builds in B42609: Diff 234156.Dec 16 2019, 2:39 PM
danlark updated this revision to Diff 234158.Dec 16 2019, 2:40 PM
This comment was removed by danlark.
Harbormaster completed remote builds in B42611: Diff 234158.Dec 16 2019, 2:44 PM
danlark updated this revision to Diff 234182.Dec 16 2019, 3:56 PM

Rebase

danlark added a comment.Dec 16 2019, 3:57 PM
In D71567#1786729, @lebedev.ri wrote:

You probably want to throw in some vector undef tests as well.
(e.g. a singled lane in one of constants, the same lane in both, different lanes in each)

All done

Harbormaster completed remote builds in B42619: Diff 234182.Dec 16 2019, 3:57 PM
danlark updated this revision to Diff 234191.Dec 16 2019, 4:48 PM

More robust zext tests

Harbormaster completed remote builds in B42625: Diff 234191.Dec 16 2019, 4:53 PM
danlark updated this revision to Diff 234235.Dec 17 2019, 12:48 AM

Correct INT_MIN test

Harbormaster completed remote builds in B42641: Diff 234235.Dec 17 2019, 12:57 AM
danlark updated this revision to Diff 237111.Jan 9 2020, 9:34 AM

Update tests

spatel accepted this revision.Jan 9 2020, 9:35 AM

LGTM

This revision is now accepted and ready to land.Jan 9 2020, 9:35 AM
danlark updated this revision to Diff 237112.Jan 9 2020, 9:35 AM

Rebase

Harbormaster completed remote builds in B43608: Diff 237111.Jan 9 2020, 9:36 AM
Harbormaster completed remote builds in B43609: Diff 237112.
lebedev.ri resigned from this revision.Jan 12 2023, 5:35 PM

This review seems to be stuck/dead, consider abandoning if no longer relevant.

Herald added a project: Restricted Project. · View Herald TranscriptJan 12 2023, 5:35 PM
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Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
233 lines

Diff 234191

llvm/test/Transforms/InstCombine/mul.ll

Show First 20 Lines • Show All 601 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]] ; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]
; CHECK-NEXT: ret i32 [[MUL]] ; CHECK-NEXT: ret i32 [[MUL]]
; ;
%div = udiv exact i32 %x, %y %div = udiv exact i32 %x, %y
%sel = select i1 %c, i32 %div, i32 1 %sel = select i1 %c, i32 %div, i32 1
%mul = mul i32 %sel, %y %mul = mul i32 %sel, %y
ret i32 %mul ret i32 %mul
} }
; TODO. 'select + mul' -> 'select + shl' for power of twos
define i32 @shift_if_power2(i32 %x, i1 %cond) {
; CHECK-LABEL: @shift_if_power2(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 16, i32 4
; CHECK-NEXT: [[R:%.*]] = mul i32 [[SEL]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 16, i32 4
%r = mul i32 %sel, %x
ret i32 %r
}
define i32 @shift_if_power2_nuw(i32 %x, i1 %cond) {
; CHECK-LABEL: @shift_if_power2_nuw(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 16, i32 4
; CHECK-NEXT: [[R:%.*]] = mul nuw i32 [[SEL]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 16, i32 4
%r = mul nuw i32 %sel, %x
ret i32 %r
}
define i32 @shift_if_power2_nsw(i32 %x, i1 %cond) {
; CHECK-LABEL: @shift_if_power2_nsw(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 16, i32 4
; CHECK-NEXT: [[R:%.*]] = mul nsw i32 [[SEL]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 16, i32 4
%r = mul nsw i32 %sel, %x
ret i32 %r
}
define i32 @shift_if_power2_nuw_nsw(i32 %x, i1 %cond) {
; CHECK-LABEL: @shift_if_power2_nuw_nsw(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 16, i32 4
; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i32 [[SEL]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 16, i32 4
%r = mul nuw nsw i32 %sel, %x
ret i32 %r
}
define i32 @shift_if_power2_nuw_nsw_min(i32 %x, i1 %cond) {
; CHECK-LABEL: @shift_if_power2_nuw_nsw_min(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 -2, i32 -2147483648
; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i32 [[SEL]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 -2, i32 -2147483648
%r = mul nuw nsw i32 %sel, %x
ret i32 %r
}
define i32 @shift_if_power2_double_select(i32 %x, i32 %y, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: @shift_if_power2_double_select(
; CHECK-NEXT: [[SHL_RES:%.*]] = shl i32 8, [[Y:%.*]]
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND1:%.*]], i32 [[SHL_RES]], i32 1024
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[COND2:%.*]], i32 16, i32 [[SEL1]]
; CHECK-NEXT: [[R:%.*]] = mul nuw i32 [[SEL2]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%shl.res = shl i32 8, %y
%sel1 = select i1 %cond1, i32 %shl.res, i32 1024
%sel2 = select i1 %cond2, i32 16, i32 %sel1
%r = mul nuw i32 %x, %sel2
ret i32 %r
}
define i32 @shift_if_power2_double_select_zext(i32 %x, i16 %y, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: @shift_if_power2_double_select_zext(
; CHECK-NEXT: [[SHL_RES:%.*]] = shl nsw i16 8, [[Y:%.*]]
; CHECK-NEXT: [[SHL:%.*]] = zext i16 [[SHL_RES]] to i32
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND1:%.*]], i32 [[SHL]], i32 1024
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[COND2:%.*]], i32 16, i32 [[SEL1]]
; CHECK-NEXT: [[R:%.*]] = mul nuw i32 [[SEL2]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%shl.res = shl nsw i16 8, %y
%shl = zext i16 %shl.res to i32
%sel1 = select i1 %cond1, i32 %shl, i32 1024
%sel2 = select i1 %cond2, i32 16, i32 %sel1
%r = mul nuw i32 %x, %sel2
ret i32 %r
}
define i32 @shift_if_power2_double_select_zext_mul_nsw(i32 %x, i16 %y, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: @shift_if_power2_double_select_zext_mul_nsw(
; CHECK-NEXT: [[SHL_RES:%.*]] = shl i16 8, [[Y:%.*]]
; CHECK-NEXT: [[SHL:%.*]] = zext i16 [[SHL_RES]] to i32
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND1:%.*]], i32 [[SHL]], i32 1024
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[COND2:%.*]], i32 16, i32 [[SEL1]]
; CHECK-NEXT: [[R:%.*]] = mul nsw i32 [[SEL2]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%shl.res = shl i16 8, %y
%shl = zext i16 %shl.res to i32
%sel1 = select i1 %cond1, i32 %shl, i32 1024
%sel2 = select i1 %cond2, i32 16, i32 %sel1
%r = mul nsw i32 %x, %sel2
ret i32 %r
}
define i32 @shift_if_power2_double_select_zext_shift_nsw(i32 %x, i16 %y, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: @shift_if_power2_double_select_zext_shift_nsw(
; CHECK-NEXT: [[SHL_RES:%.*]] = shl nsw i16 8, [[Y:%.*]]
; CHECK-NEXT: [[SHL:%.*]] = zext i16 [[SHL_RES]] to i32
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND1:%.*]], i32 [[SHL]], i32 1024
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[COND2:%.*]], i32 16, i32 [[SEL1]]
; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i32 [[SEL2]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%shl.res = shl nsw i16 8, %y
%shl = zext i16 %shl.res to i32
%sel1 = select i1 %cond1, i32 %shl, i32 1024
%sel2 = select i1 %cond2, i32 16, i32 %sel1
%r = mul nuw nsw i32 %x, %sel2
ret i32 %r
}
define i32 @shift_if_power2_zero(i32 %x, i1 %cond) {
; CHECK-LABEL: @shift_if_power2_zero(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 1, i32 4
; CHECK-NEXT: [[R:%.*]] = mul i32 [[SEL]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 1, i32 4
%r = mul i32 %sel, %x
ret i32 %r
}
define <2 x i8> @shift_if_power2_vector(<2 x i8> %px, i1 %cond) {
; CHECK-LABEL: @shift_if_power2_vector(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], <2 x i8> <i8 16, i8 4>, <2 x i8> <i8 1, i8 32>
; CHECK-NEXT: [[R:%.*]] = mul <2 x i8> [[SEL]], [[PX:%.*]]
; CHECK-NEXT: ret <2 x i8> [[R]]
;
%sel = select i1 %cond, <2 x i8> <i8 16, i8 4>, <2 x i8> <i8 1, i8 32>
%r = mul <2 x i8> %px, %sel
ret <2 x i8> %r
}
define i32 @shift_if_extra_use(i32 %x, i1 %cond) {
; CHECK-LABEL: @shift_if_extra_use(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 4, i32 128
; CHECK-NEXT: call void @use32(i32 [[SEL]])
; CHECK-NEXT: [[R:%.*]] = mul i32 [[SEL]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 4, i32 128
call void @use32(i32 %sel)
%r = mul i32 %sel, %x
ret i32 %r
}
; Negative tests for power2
define i32 @shift_if_one_not_power2(i32 %x, i1 %cond) {
; CHECK-LABEL: @shift_if_one_not_power2(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 5, i32 4
; CHECK-NEXT: [[R:%.*]] = mul i32 [[SEL]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%sel = select i1 %cond, i32 5, i32 4
%r = mul i32 %sel, %x
ret i32 %r
}
define i32 @shift_if_not_power2_double_select(i32 %x, i32 %y, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: @shift_if_not_power2_double_select(
; CHECK-NEXT: [[SHL_RES:%.*]] = shl i32 7, [[Y:%.*]]
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND1:%.*]], i32 [[SHL_RES]], i32 1024
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[COND2:%.*]], i32 16, i32 [[SEL1]]
; CHECK-NEXT: [[R:%.*]] = mul nuw i32 [[SEL2]], [[X:%.*]]
; CHECK-NEXT: ret i32 [[R]]
;
%shl.res = shl i32 7, %y
%sel1 = select i1 %cond1, i32 %shl.res, i32 1024
%sel2 = select i1 %cond2, i32 16, i32 %sel1
%r = mul nuw i32 %x, %sel2
ret i32 %r
}
define <2 x i8> @shift_if_one_not_power2_vector(<2 x i8> %px, i1 %cond) {
; CHECK-LABEL: @shift_if_one_not_power2_vector(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], <2 x i8> <i8 16, i8 4>, <2 x i8> <i8 0, i8 32>
; CHECK-NEXT: [[R:%.*]] = mul <2 x i8> [[SEL]], [[PX:%.*]]
; CHECK-NEXT: ret <2 x i8> [[R]]
;
%sel = select i1 %cond, <2 x i8> <i8 16, i8 4>, <2 x i8> <i8 0, i8 32>
%r = mul <2 x i8> %px, %sel
ret <2 x i8> %r
}
; Undef select + mul tests
define <2 x i8> @shift_if_undef_vector(<2 x i8> %px, i1 %cond) {
; CHECK-LABEL: @shift_if_undef_vector(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], <2 x i8> <i8 16, i8 4>, <2 x i8> <i8 undef, i8 32>
; CHECK-NEXT: [[R:%.*]] = mul <2 x i8> [[SEL]], [[PX:%.*]]
; CHECK-NEXT: ret <2 x i8> [[R]]
;
%sel = select i1 %cond, <2 x i8> <i8 16, i8 4>, <2 x i8> <i8 undef, i8 32>
%r = mul <2 x i8> %px, %sel
ret <2 x i8> %r
}
define <2 x i8> @shift_if_different_lanes_undef_vector(<2 x i8> %px, i1 %cond) {
; CHECK-LABEL: @shift_if_different_lanes_undef_vector(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], <2 x i8> <i8 16, i8 undef>, <2 x i8> <i8 undef, i8 32>
; CHECK-NEXT: [[R:%.*]] = mul <2 x i8> [[SEL]], [[PX:%.*]]
; CHECK-NEXT: ret <2 x i8> [[R]]
;
%sel = select i1 %cond, <2 x i8> <i8 16, i8 undef>, <2 x i8> <i8 undef, i8 32>
%r = mul <2 x i8> %px, %sel
ret <2 x i8> %r
}
define <2 x i8> @shift_if_same_lane_undef_vector(<2 x i8> %px, i1 %cond) {
; CHECK-LABEL: @shift_if_same_lane_undef_vector(
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], <2 x i8> <i8 undef, i8 4>, <2 x i8> <i8 undef, i8 32>
; CHECK-NEXT: [[R:%.*]] = mul <2 x i8> [[SEL]], [[PX:%.*]]
; CHECK-NEXT: ret <2 x i8> [[R]]
;
%sel = select i1 %cond, <2 x i8> <i8 undef, i8 4>, <2 x i8> <i8 undef, i8 32>
%r = mul <2 x i8> %px, %sel
ret <2 x i8> %r
}