[ARM] Move MVEOpcodes helpers to ARMBaseInstrInfo. NFC.

[SjoerdMeijer]

Summary

In files ARMLowOverheadLoops.cpp, MVETailPredication.cpp, and MVEVPTBlock.cpp we have quite a few helper functions all looking at the opcodes of MVE instructions. This moves all these utility functions to Utils/MVEOpcodes.cpp and namespace MVEOpcodes so that all these functions all clustered and we don't clutter the passes with them.

[samparker]

Do we need a cpp file..? Would be nice for these helpers to get inlined. Yaybe worth them living in ARMBaseInstrInfo.h as there's already a VPT opcode helper there too.

llvm/lib/Target/ARM/Utils/MVEOpcodes.cpp

17

This is only really ever going to be used in one place so I'd prefer it stay there really.

115

These aren't MVE instructions.

[SjoerdMeijer]

Ah yes, thanks, I forgot about ARMBaseInstrInfo, but that's definitely the place where this should live.

[samparker]

Cheers, LGTM

[SjoerdMeijer]

Committed in 049f9672d8566f0d0a115f11e2a53018ea502b10
(I had a typo in the tag Diferential Revision, so this didn't get closed automatically)

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

 #include "ARMSubtarget.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineLoopUtils.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/ReachingDefAnalysis.h"
 #include "llvm/MC/MCInstrDesc.h"
+#include "Utils/MVEOpcodes.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "arm-low-overhead-loops"
 #define ARM_LOW_OVERHEAD_LOOPS_NAME "ARM Low Overhead Loops pass"
 
 namespace {
 
MachineOperand &getCount() {
       return IsTailPredicationLegal() ?
         VCTP->getOperand(1) : Start->getOperand(0);
     }
 
     unsigned getStartOpcode() const {
       bool IsDo = Start->getOpcode() == ARM::t2DoLoopStart;
       if (!IsTailPredicationLegal())
         return IsDo ? ARM::t2DLS : ARM::t2WLS;
-      
-      switch (VCTP->getOpcode()) {
-      default:
-        llvm_unreachable("unhandled vctp opcode");
-        break;
-      case ARM::MVE_VCTP8:
-        return IsDo ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8;
-      case ARM::MVE_VCTP16:
-        return IsDo ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16;
-      case ARM::MVE_VCTP32:
-        return IsDo ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32;
-      case ARM::MVE_VCTP64:
-        return IsDo ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64;
-      }
-      return 0;
+      return MVEOpcodes::getVCTPLowOverheadLoop(VCTP->getOpcode(), IsDo);
     }
 
     void dump() const {
       if (Start) dbgs() << "ARM Loops: Found Loop Start: " << *Start;
       if (Dec) dbgs() << "ARM Loops: Found Loop Dec: " << *Dec;
       if (End) dbgs() << "ARM Loops: Found Loop End: " << *End;
       if (VCTP) dbgs() << "ARM Loops: Found VCTP: " << *VCTP;
       if (!FoundAllComponents())
namespace {
   };
 }
 
 char ARMLowOverheadLoops::ID = 0;
 
 INITIALIZE_PASS(ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME,
                 false, false)
 
-static bool IsLoopStart(MachineInstr &MI) {
-  return MI.getOpcode() == ARM::t2DoLoopStart ||
-         MI.getOpcode() == ARM::t2WhileLoopStart;
-}
-
-static bool IsVCTP(MachineInstr *MI) {
-  switch (MI->getOpcode()) {
-  default:
-    break;
-  case ARM::MVE_VCTP8:
-  case ARM::MVE_VCTP16:
-  case ARM::MVE_VCTP32:
-  case ARM::MVE_VCTP64:
-    return true;
-  }
-  return false;
-}
-
 MachineInstr *LowOverheadLoop::IsSafeToDefineLR(ReachingDefAnalysis *RDA) {
   // We can define LR because LR already contains the same value.
   if (Start->getOperand(0).getReg() == ARM::LR)
     return Start;
 
   unsigned CountReg = Start->getOperand(0).getReg();
   auto IsMoveLR = [&CountReg](MachineInstr *MI) {
     return MI->getOpcode() == ARM::tMOVr &&
LLVM_DEBUG(dbgs() << "ARM Loops: Processing loop containing:\n";
                dbgs() << " - " << MBB->getName() << "\n";
             );
 
   // Search the given block for a loop start instruction. If one isn't found,
   // and there's only one predecessor block, search that one too.
   std::function<MachineInstr*(MachineBasicBlock*)> SearchForStart =
     [&SearchForStart](MachineBasicBlock *MBB) -> MachineInstr* {
     for (auto &MI : *MBB) {
-      if (IsLoopStart(MI))
+      if (MVEOpcodes::IsLoopStart(MI.getOpcode()))
         return &MI;
     }
     if (MBB->pred_size() == 1)
       return SearchForStart(*MBB->pred_begin());
     return nullptr;
   };
 
   LowOverheadLoop LoLoop(ML);
bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
   // back to a normal loop. Also look for a vctp instructions and decide
   // whether we can convert that predicate using tail predication.
   for (auto *MBB : reverse(ML->getBlocks())) {
     for (auto &MI : *MBB) {
       if (MI.getOpcode() == ARM::t2LoopDec)
         LoLoop.Dec = &MI;
       else if (MI.getOpcode() == ARM::t2LoopEnd)
         LoLoop.End = &MI;
-      else if (IsLoopStart(MI))
+      else if (MVEOpcodes::IsLoopStart(MI.getOpcode()))
         LoLoop.Start = &MI;
-      else if (IsVCTP(&MI))
+      else if (MVEOpcodes::IsVCTP(MI.getOpcode()))
         LoLoop.addVCTP(&MI);
       else if (MI.getDesc().isCall()) {
         // TODO: Though the call will require LE to execute again, does this
         // mean we should revert? Always executing LE hopefully should be
         // faster than performing a sub,cmp,br or even subs,br.
         LoLoop.Revert = true;
         LLVM_DEBUG(dbgs() << "ARM Loops: Found call.\n");
       } else {
bool ARMLowOverheadLoops::RevertNonLoops() {
   bool Changed = false;
 
   for (auto &MBB : *MF) {
     SmallVector<MachineInstr*, 4> Starts;
     SmallVector<MachineInstr*, 4> Decs;
     SmallVector<MachineInstr*, 4> Ends;
 
     for (auto &I : MBB) {
-      if (IsLoopStart(I))
+      if (MVEOpcodes::IsLoopStart(I.getOpcode()))
         Starts.push_back(&I);
       else if (I.getOpcode() == ARM::t2LoopDec)
         Decs.push_back(&I);
       else if (I.getOpcode() == ARM::t2LoopEnd)
         Ends.push_back(&I);
     }
 
     if (Starts.empty() && Decs.empty() && Ends.empty())

llvm/lib/Target/ARM/MVETailPredication.cpp

 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicsARM.h"
 #include "llvm/IR/PatternMatch.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
+#include "Utils/MVEOpcodes.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "mve-tail-predication"
 #define DESC "Transform predicated vector loops to use MVE tail predication"
 
 cl::opt<bool>
 DisableTailPredication("disable-mve-tail-predication", cl::Hidden,
for (auto *I : MaskedInsts) {
     IRBuilder<> Builder(L->getHeader()->getFirstNonPHI());
     PHINode *Processed = Builder.CreatePHI(Ty, 2);
     Processed->addIncoming(NumElements, L->getLoopPreheader());
 
     // Insert the intrinsic to represent the effect of tail predication.
     Builder.SetInsertPoint(cast<Instruction>(Predicate));
     ConstantInt *Factor =
       ConstantInt::get(cast<IntegerType>(Ty), VecTy->getNumElements());
-    Intrinsic::ID VCTPID;
-    switch (VecTy->getNumElements()) {
-    default:
-      llvm_unreachable("unexpected number of lanes");
-    case 4:  VCTPID = Intrinsic::arm_mve_vctp32; break;
-    case 8:  VCTPID = Intrinsic::arm_mve_vctp16; break;
-    case 16: VCTPID = Intrinsic::arm_mve_vctp8; break;
-
-      // FIXME: vctp64 currently not supported because the predicate
-      // vector wants to be <2 x i1>, but v2i1 is not a legal MVE
-      // type, so problems happen at isel time.
-      // Intrinsic::arm_mve_vctp64 exists for ACLE intrinsics
-      // purposes, but takes a v4i1 instead of a v2i1.
-    }
+
+    Intrinsic::ID VCTPID = MVEOpcodes::getVCTPInstricID(VecTy->getNumElements());
     Function *VCTP = Intrinsic::getDeclaration(M, VCTPID);
     Value *TailPredicate = Builder.CreateCall(VCTP, Processed);
     Predicate->replaceAllUsesWith(TailPredicate);
     NewPredicates[Predicate] = cast<Instruction>(TailPredicate);
 
     // Add the incoming value to the new phi.
     // TODO: This add likely already exists in the loop.
     Value *Remaining = Builder.CreateSub(Processed, Factor);

llvm/lib/Target/ARM/MVEVPTBlockPass.cpp

 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineInstrBundle.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/ReachingDefAnalysis.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Support/Debug.h"
+#include "Utils/MVEOpcodes.h"
 #include <cassert>
 #include <new>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "arm-mve-vpt"
 
 namespace {
enum VPTMaskValue {
   TTEE  =  5, // 0b0101
   TTET  =  7, // 0b0111
   TEEE  =  9, // 0b1001
   TEET  = 11, // 0b1011
   TETT  = 13, // 0b1101
   TETE  = 15  // 0b1111
 };
 
-static unsigned VCMPOpcodeToVPT(unsigned Opcode) {
-  switch (Opcode) {
-  case ARM::MVE_VCMPf32:
-    return ARM::MVE_VPTv4f32;
-  case ARM::MVE_VCMPf16:
-    return ARM::MVE_VPTv8f16;
-  case ARM::MVE_VCMPi8:
-    return ARM::MVE_VPTv16i8;
-  case ARM::MVE_VCMPi16:
-    return ARM::MVE_VPTv8i16;
-  case ARM::MVE_VCMPi32:
-    return ARM::MVE_VPTv4i32;
-  case ARM::MVE_VCMPu8:
-    return ARM::MVE_VPTv16u8;
-  case ARM::MVE_VCMPu16:
-    return ARM::MVE_VPTv8u16;
-  case ARM::MVE_VCMPu32:
-    return ARM::MVE_VPTv4u32;
-  case ARM::MVE_VCMPs8:
-    return ARM::MVE_VPTv16s8;
-  case ARM::MVE_VCMPs16:
-    return ARM::MVE_VPTv8s16;
-  case ARM::MVE_VCMPs32:
-    return ARM::MVE_VPTv4s32;
-
-  case ARM::MVE_VCMPf32r:
-    return ARM::MVE_VPTv4f32r;
-  case ARM::MVE_VCMPf16r:
-    return ARM::MVE_VPTv8f16r;
-  case ARM::MVE_VCMPi8r:
-    return ARM::MVE_VPTv16i8r;
-  case ARM::MVE_VCMPi16r:
-    return ARM::MVE_VPTv8i16r;
-  case ARM::MVE_VCMPi32r:
-    return ARM::MVE_VPTv4i32r;
-  case ARM::MVE_VCMPu8r:
-    return ARM::MVE_VPTv16u8r;
-  case ARM::MVE_VCMPu16r:
-    return ARM::MVE_VPTv8u16r;
-  case ARM::MVE_VCMPu32r:
-    return ARM::MVE_VPTv4u32r;
-  case ARM::MVE_VCMPs8r:
-    return ARM::MVE_VPTv16s8r;
-  case ARM::MVE_VCMPs16r:
-    return ARM::MVE_VPTv8s16r;
-  case ARM::MVE_VCMPs32r:
-    return ARM::MVE_VPTv4s32r;
-
-  default:
-    return 0;
-  }
-}
-
 static MachineInstr *findVCMPToFoldIntoVPST(MachineInstr *MI,
                                             ReachingDefAnalysis *RDA,
                                             unsigned &NewOpcode) {
   // First, search backwards to the instruction that defines VPR
   auto *Def = RDA->getReachingMIDef(MI, ARM::VPR);
   if (!Def)
     return nullptr;
 
   // Now check that Def is a VCMP
-  if (!(NewOpcode = VCMPOpcodeToVPT(Def->getOpcode())))
+  if (!(NewOpcode = MVEOpcodes::VCMPOpcodeToVPT(Def->getOpcode())))
     return nullptr;
 
   // Check that Def's operands are not defined between the VCMP and MI, i.e.
   // check that they have the same reaching def.
   if (!RDA->hasSameReachingDef(Def, MI, Def->getOperand(1).getReg()) ||
       !RDA->hasSameReachingDef(Def, MI, Def->getOperand(2).getReg()))
     return nullptr;
 

llvm/lib/Target/ARM/Utils/CMakeLists.txt

 add_llvm_component_library(LLVMARMUtils
   ARMBaseInfo.cpp
+  MVEOpcodes.cpp
   )

llvm/lib/Target/ARM/Utils/MVEOpcodes.h

+//===-- MVEOpcodes.h- MVE utilities to query MVE instructions -------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+namespace llvm {
+namespace MVEOpcodes {
+
+Intrinsic::ID getVCTPInstricID(int NumElements);
+unsigned VCMPOpcodeToVPT(unsigned Opcode); 
+unsigned getVCTPLowOverheadLoop(unsigned Opcode, bool IsDoLoop);
+bool IsVCTP(unsigned Opcode);
+bool IsLoopStart(unsigned Opcode);
+
+} // MVEOpcodes
+} // llvm

llvm/lib/Target/ARM/Utils/MVEOpcodes.cpp

+//===-- MVEOpcodes.cpp - MVE utilities to query MVE instructions ----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Thumb2InstrInfo.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicsARM.h"
+
+using namespace llvm;
+namespace llvm {
+namespace MVEOpcodes {
+
+Intrinsic::ID getVCTPInstricID(int NumElements) {
+  switch (NumElements) {
+  default:
+    llvm_unreachable("unexpected number of lanes");
+  case 4:  return Intrinsic::arm_mve_vctp32;
+  case 8:  return Intrinsic::arm_mve_vctp16;
+  case 16: return Intrinsic::arm_mve_vctp8;
+
+  // FIXME: vctp64 currently not supported because the predicate
+  // vector wants to be <2 x i1>, but v2i1 is not a legal MVE
+  // type, so problems happen at isel time.
+  // Intrinsic::arm_mve_vctp64 exists for ACLE intrinsics
+  // purposes, but takes a v4i1 instead of a v2i1.
+  }
+}
+
+unsigned getVCTPLowOverheadLoop(unsigned Opcode, bool IsDoLoop) {
+  switch (Opcode) {
+  default:
+    llvm_unreachable("unhandled vctp opcode");
+    break;
+  case ARM::MVE_VCTP8:
+    return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8;
+  case ARM::MVE_VCTP16:
+    return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16;
+  case ARM::MVE_VCTP32:
+    return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32;
+  case ARM::MVE_VCTP64:
+    return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64;
+  }
+  return 0;
+}
+
+unsigned VCMPOpcodeToVPT(unsigned Opcode) {
+  switch (Opcode) {
+  case ARM::MVE_VCMPf32:
+    return ARM::MVE_VPTv4f32;
+  case ARM::MVE_VCMPf16:
+    return ARM::MVE_VPTv8f16;
+  case ARM::MVE_VCMPi8:
+    return ARM::MVE_VPTv16i8;
+  case ARM::MVE_VCMPi16:
+    return ARM::MVE_VPTv8i16;
+  case ARM::MVE_VCMPi32:
+    return ARM::MVE_VPTv4i32;
+  case ARM::MVE_VCMPu8:
+    return ARM::MVE_VPTv16u8;
+  case ARM::MVE_VCMPu16:
+    return ARM::MVE_VPTv8u16;
+  case ARM::MVE_VCMPu32:
+    return ARM::MVE_VPTv4u32;
+  case ARM::MVE_VCMPs8:
+    return ARM::MVE_VPTv16s8;
+  case ARM::MVE_VCMPs16:
+    return ARM::MVE_VPTv8s16;
+  case ARM::MVE_VCMPs32:
+    return ARM::MVE_VPTv4s32;
+
+  case ARM::MVE_VCMPf32r:
+    return ARM::MVE_VPTv4f32r;
+  case ARM::MVE_VCMPf16r:
+    return ARM::MVE_VPTv8f16r;
+  case ARM::MVE_VCMPi8r:
+    return ARM::MVE_VPTv16i8r;
+  case ARM::MVE_VCMPi16r:
+    return ARM::MVE_VPTv8i16r;
+  case ARM::MVE_VCMPi32r:
+    return ARM::MVE_VPTv4i32r;
+  case ARM::MVE_VCMPu8r:
+    return ARM::MVE_VPTv16u8r;
+  case ARM::MVE_VCMPu16r:
+    return ARM::MVE_VPTv8u16r;
+  case ARM::MVE_VCMPu32r:
+    return ARM::MVE_VPTv4u32r;
+  case ARM::MVE_VCMPs8r:
+    return ARM::MVE_VPTv16s8r;
+  case ARM::MVE_VCMPs16r:
+    return ARM::MVE_VPTv8s16r;
+  case ARM::MVE_VCMPs32r:
+    return ARM::MVE_VPTv4s32r;
+
+  default:
+    return 0;
+  }
+}
+
+bool IsVCTP(unsigned Opcode) {
+  switch (Opcode) {
+  default: break;
+  case ARM::MVE_VCTP8:
+  case ARM::MVE_VCTP16:
+  case ARM::MVE_VCTP32:
+  case ARM::MVE_VCTP64:
+    return true;
+  }
+  return false;
+}
+
+bool IsLoopStart(unsigned Opcode) {
+  return Opcode == ARM::t2DoLoopStart ||
+         Opcode == ARM::t2WhileLoopStart;
+}
+
+} // end namespace MVEOpcodes 
+} // end namespace llvm