Allow negative offsets in MipsMCInstLower::LowerOperand

[arichardson]

Summary

We rely on this in our CHERI backend to address the GOT by generating a
$pc-relative addresses. For this we emit the following code sequence:

lui $1, %pcrel_hi(_CHERI_CAPABILITY_TABLE_-8)
daddiu $1, $1, %pcrel_lo(_CHERI_CAPABILITY_TABLE_-4)
cgetpccincoffset $c1, $1

However, without this change the addend is implicitly converted to
UINT32_MAX and an invalid pointer value is generated.

[arichardson]

Add missing changes to header

[arichardson]

clang-format

[merge_guards_bot]

Build result: FAILURE -
Log files: console-log.txt, CMakeCache.txt

[merge_guards_bot]

Build result: pass - 60404 tests passed, 0 failed and 726 were skipped.

Log files: console-log.txt, CMakeCache.txt

[merge_guards_bot]

Build result: pass - 60404 tests passed, 0 failed and 726 were skipped.

Log files: console-log.txt, CMakeCache.txt

[atanasyan]

LGTM

llvm/lib/Target/Mips/MipsMCInstLower.h

class LLVM_LIBRARY_VISIBILITY MipsMCInstLower {
   MCContext *Ctx;
   MipsAsmPrinter &AsmPrinter;
 
 public:
   MipsMCInstLower(MipsAsmPrinter &asmprinter);
 
   void Initialize(MCContext *C);
   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
-  MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
+  MCOperand LowerOperand(const MachineOperand &MO, int64_t offset = 0) const;
 
 private:
   MCOperand LowerSymbolOperand(const MachineOperand &MO,
-                               MachineOperandType MOTy, unsigned Offset) const;
+                               MachineOperandType MOTy, int64_t Offset) const;
   MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
                       MipsMCExpr::MipsExprKind Kind) const;
   void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
   void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
                             int Opcode) const;
   bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H

llvm/lib/Target/Mips/MipsMCInstLower.cpp

MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter)
   : AsmPrinter(asmprinter) {}
 
 void MipsMCInstLower::Initialize(MCContext *C) {
   Ctx = C;
 }
 
 MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
                                               MachineOperandType MOTy,
-                                              unsigned Offset) const {
+                                              int64_t Offset) const {
   MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
   MipsMCExpr::MipsExprKind TargetKind = MipsMCExpr::MEK_None;
   bool IsGpOff = false;
   const MCSymbol *Symbol;
 
   switch(MO.getTargetFlags()) {
   default:
     llvm_unreachable("Invalid target flag!");
MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
 
   default:
     llvm_unreachable("<unknown operand type>");
   }
 
   const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, Kind, *Ctx);
 
   if (Offset) {
-    // Assume offset is never negative.
-    assert(Offset > 0);
-
+    // Note: Offset can also be negative
     Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(Offset, *Ctx),
                                    *Ctx);
   }
 
   if (IsGpOff)
     Expr = MipsMCExpr::createGpOff(TargetKind, Expr, *Ctx);
   else if (TargetKind != MipsMCExpr::MEK_None)
     Expr = MipsMCExpr::create(TargetKind, Expr, *Ctx);
 
   return MCOperand::createExpr(Expr);
 }
 
 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
-                                        unsigned offset) const {
+                                        int64_t offset) const {
   MachineOperandType MOTy = MO.getType();
 
   switch (MOTy) {
   default: llvm_unreachable("unknown operand type");
   case MachineOperand::MO_Register:
     // Ignore all implicit register operands.
     if (MO.isImplicit()) break;
     return MCOperand::createReg(MO.getReg());