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Differential D70813

[AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly.
ClosedPublic

Authored by simon_tatham on Nov 28 2019, 4:07 AM.

Details

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ab
ostannard
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rGacd7fe8636ab: [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly.
Summary

In rG643ac6c0420b, the syntax ldraa x1, [x0]! was added as an alias
for ldraa x1, [x0, #0]!. That syntax is less obvious in meaning, and
also will not be accepted by assemblers that haven't been updated yet.
So it would be better not to emit it as the preferred disassembly for
that instruction.

This change lowers the EmitPriority of the new alias so that the more
explicit syntax [x0, #0]! is preferred by the disassembler. The new
syntax is still accepted by the assembler.

Diff Detail

Event Timeline

simon_tatham created this revision.Nov 28 2019, 4:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 28 2019, 4:07 AM
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls. · View Herald Transcript
Harbormaster completed remote builds in B41608: Diff 231402.Nov 28 2019, 4:14 AM
ostannard accepted this revision.Nov 28 2019, 5:57 AM

LGTM

This revision is now accepted and ready to land.Nov 28 2019, 5:57 AM
Closed by commit rGacd7fe8636ab: [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly. (authored by simon_tatham). · Explain WhyNov 28 2019, 7:32 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
2 lines
test/
MC/
AArch64/
4 lines
Disassembler/
AArch64/
4 lines

Diff 231433

llvm/lib/Target/AArch64/AArch64InstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,467 Lines • ▼ Show 20 Lines def writeback : BaseAuthLoad<M, 1, (outs GPR64sp:$wback, GPR64:$Rt),
(ins GPR64sp:$Rn, opr:$offset), (ins GPR64sp:$Rn, opr:$offset),
asm, "\t$Rt, [$Rn, $offset]!", asm, "\t$Rt, [$Rn, $offset]!",
"$Rn = $wback,@earlyclobber $wback", opr>; "$Rn = $wback,@earlyclobber $wback", opr>;
def : InstAlias<asm # "\t$Rt, [$Rn]", def : InstAlias<asm # "\t$Rt, [$Rn]",
(!cast<Instruction>(NAME # "indexed") GPR64:$Rt, GPR64sp:$Rn, 0)>; (!cast<Instruction>(NAME # "indexed") GPR64:$Rt, GPR64sp:$Rn, 0)>;
def : InstAlias<asm # "\t$Rt, [$wback]!", def : InstAlias<asm # "\t$Rt, [$wback]!",
(!cast<Instruction>(NAME # "writeback") GPR64sp:$wback, GPR64:$Rt, 0)>; (!cast<Instruction>(NAME # "writeback") GPR64sp:$wback, GPR64:$Rt, 0), 0>;
} }
//--- //---
// Conditional branch instruction. // Conditional branch instruction.
//--- //---
// Condition code. // Condition code.
// 4-bit immediate. Pretty-printed as <cc> // 4-bit immediate. Pretty-printed as <cc>
▲ Show 20 Lines • Show All 9,280 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/armv8.3a-signed-pointer.s

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// CHECK-NEXT: ldraa x0, [x1] // encoding: [0x20,0x04,0x20,0xf8] // CHECK-NEXT: ldraa x0, [x1] // encoding: [0x20,0x04,0x20,0xf8]
// CHECK-REQ: error: instruction requires: pa // CHECK-REQ: error: instruction requires: pa
// CHECK-REQ-NEXT: ldraa x0, [x1] // CHECK-REQ-NEXT: ldraa x0, [x1]
ldrab x0, [x1] ldrab x0, [x1]
// CHECK-NEXT: ldrab x0, [x1] // encoding: [0x20,0x04,0xa0,0xf8] // CHECK-NEXT: ldrab x0, [x1] // encoding: [0x20,0x04,0xa0,0xf8]
// CHECK-REQ: error: instruction requires: pa // CHECK-REQ: error: instruction requires: pa
// CHECK-REQ-NEXT: ldrab x0, [x1] // CHECK-REQ-NEXT: ldrab x0, [x1]
ldraa x0, [x1]! ldraa x0, [x1]!
// CHECK-NEXT: ldraa x0, [x1]! // encoding: [0x20,0x0c,0x20,0xf8] // CHECK-NEXT: ldraa x0, [x1, #0]! // encoding: [0x20,0x0c,0x20,0xf8]
// CHECK-REQ: error: instruction requires: pa // CHECK-REQ: error: instruction requires: pa
// CHECK-REQ-NEXT: ldraa x0, [x1]! // CHECK-REQ-NEXT: ldraa x0, [x1]!
ldrab x0, [x1]! ldrab x0, [x1]!
// CHECK-NEXT: ldrab x0, [x1]! // encoding: [0x20,0x0c,0xa0,0xf8] // CHECK-NEXT: ldrab x0, [x1, #0]! // encoding: [0x20,0x0c,0xa0,0xf8]
// CHECK-REQ: error: instruction requires: pa // CHECK-REQ: error: instruction requires: pa
// CHECK-REQ-NEXT: ldrab x0, [x1]! // CHECK-REQ-NEXT: ldrab x0, [x1]!

llvm/test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt

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[0x20,0xfc,0xbf,0xf8] [0x20,0xfc,0xbf,0xf8]
[0x20,0x0c,0xe0,0xf8] [0x20,0x0c,0xe0,0xf8]
# CHECK: ldraa x0, [x1] # CHECK: ldraa x0, [x1]
# CHECK: ldrab x0, [x1] # CHECK: ldrab x0, [x1]
[0x20,0x04,0x20,0xf8] [0x20,0x04,0x20,0xf8]
[0x20,0x04,0xa0,0xf8] [0x20,0x04,0xa0,0xf8]
# CHECK: ldraa x0, [x1]! # CHECK: ldraa x0, [x1, #0]!
# CHECK: ldrab x0, [x1]! # CHECK: ldrab x0, [x1, #0]!
[0x20,0x0c,0x20,0xf8] [0x20,0x0c,0x20,0xf8]
[0x20,0x0c,0xa0,0xf8] [0x20,0x0c,0xa0,0xf8]