GlobalISel: Lower s1 source G_SITOFP/G_UITOFP

[arsenm]

bc276c6379fd0a7bca78d53026e346ea0c8b7cff

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

 
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
   Register Dst = MI.getOperand(0).getReg();
   Register Src = MI.getOperand(1).getReg();
   LLT DstTy = MRI.getType(Dst);
   LLT SrcTy = MRI.getType(Src);
 
+  if (SrcTy == LLT::scalar(1)) {
+    auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
+    auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
+    MIRBuilder.buildSelect(Dst, Src, True, False);
+    MI.eraseFromParent();
+    return Legalized;
+  }
+
   if (SrcTy != LLT::scalar(64))
     return UnableToLegalize;
 
   if (DstTy == LLT::scalar(32)) {
     // TODO: SelectionDAG has several alternative expansions to port which may
     // be more reasonble depending on the available instructions. If a target
     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
     // intermediate type, this is probably worse.
LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
   Register Src = MI.getOperand(1).getReg();
   LLT DstTy = MRI.getType(Dst);
   LLT SrcTy = MRI.getType(Src);
 
   const LLT S64 = LLT::scalar(64);
   const LLT S32 = LLT::scalar(32);
   const LLT S1 = LLT::scalar(1);
 
+  if (SrcTy == S1) {
+    auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
+    auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
+    MIRBuilder.buildSelect(Dst, Src, True, False);
+    MI.eraseFromParent();
+    return Legalized;
+  }
+
   if (SrcTy != S64)
     return UnableToLegalize;
 
   if (DstTy == S32) {
     // signed cl2f(long l) {
     //   long s = l >> 63;
     //   float r = cul2f((l + s) ^ s);
     //   return s ? -r : r;

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

private:
 
   MachineOperand getSubOperand64(MachineOperand &MO,
                                  const TargetRegisterClass &SubRC,
                                  unsigned SubIdx) const;
   bool selectCOPY(MachineInstr &I) const;
   bool selectPHI(MachineInstr &I) const;
   bool selectG_TRUNC(MachineInstr &I) const;
   bool selectG_SZA_EXT(MachineInstr &I) const;
-  bool selectG_SITOFP_UITOFP(MachineInstr &I) const;
   bool selectG_CONSTANT(MachineInstr &I) const;
   bool selectG_AND_OR_XOR(MachineInstr &I) const;
   bool selectG_ADD_SUB(MachineInstr &I) const;
   bool selectG_UADDO_USUBO(MachineInstr &I) const;
   bool selectG_EXTRACT(MachineInstr &I) const;
   bool selectG_MERGE_VALUES(MachineInstr &I) const;
   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
   bool selectG_PTR_ADD(MachineInstr &I) const;

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

if (SrcBank->getID() == AMDGPU::SGPRRegBankID && DstSize <= 64) {
 
     I.eraseFromParent();
     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);
   }
 
   return false;
 }
 
-static int64_t getFPTrueImmVal(unsigned Size, bool Signed) {
-  switch (Size) {
-  case 16:
-    return Signed ? 0xBC00 : 0x3C00;
-  case 32:
-    return Signed ? 0xbf800000 : 0x3f800000;
-  case 64:
-    return Signed ? 0xbff0000000000000 : 0x3ff0000000000000;
-  default:
-    llvm_unreachable("Invalid FP type size");
-  }
-}
-
-bool AMDGPUInstructionSelector::selectG_SITOFP_UITOFP(MachineInstr &I) const {
-  MachineBasicBlock *MBB = I.getParent();
-  MachineFunction *MF = MBB->getParent();
-  MachineRegisterInfo &MRI = MF->getRegInfo();
-  Register Src = I.getOperand(1).getReg();
-  if (!isSCC(Src, MRI))
-    return selectImpl(I, *CoverageInfo);
-
-  bool Signed = I.getOpcode() == AMDGPU::G_SITOFP;
-  Register DstReg = I.getOperand(0).getReg();
-  const LLT DstTy = MRI.getType(DstReg);
-  const unsigned DstSize = DstTy.getSizeInBits();
-  const DebugLoc &DL = I.getDebugLoc();
-
-  BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
-    .addReg(Src);
-
-  unsigned NewOpc =
-    DstSize > 32 ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
-  auto MIB = BuildMI(*MBB, I, DL, TII.get(NewOpc), DstReg)
-    .addImm(0)
-    .addImm(getFPTrueImmVal(DstSize, Signed));
-
-  if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
-    return false;
-
-  I.eraseFromParent();
-  return true;
-}
-
 bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
   MachineBasicBlock *BB = I.getParent();
   MachineOperand &ImmOp = I.getOperand(1);
 
   // The AMDGPU backend only supports Imm operands and not CImm or FPImm.
   if (ImmOp.isFPImm()) {
     const APInt &Imm = ImmOp.getFPImm()->getValueAPF().bitcastToAPInt();
     ImmOp.ChangeToImmediate(Imm.getZExtValue());
bool AMDGPUInstructionSelector::select(MachineInstr &I) {
   case TargetOpcode::G_STORE:
     return selectG_STORE(I);
   case TargetOpcode::G_TRUNC:
     return selectG_TRUNC(I);
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
   case TargetOpcode::G_ANYEXT:
     return selectG_SZA_EXT(I);
-  case TargetOpcode::G_SITOFP:
-  case TargetOpcode::G_UITOFP:
-    return selectG_SITOFP_UITOFP(I);
   case TargetOpcode::G_BRCOND:
     return selectG_BRCOND(I);
   case TargetOpcode::G_FRAME_INDEX:
     return selectG_FRAME_INDEX(I);
   case TargetOpcode::G_FENCE:
     // FIXME: Tablegen importer doesn't handle the imm operands correctly, and
     // is checking for G_CONSTANT
     I.setDesc(TII.get(AMDGPU::ATOMIC_FENCE));

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

.legalFor({{S64, S32}, {S32, S16}, {S64, S16},
                {S96, S32},
                // FIXME: Hack
                {S64, LLT::scalar(33)},
                {S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}})
     .scalarize(0);
 
   // TODO: Split s1->s64 during regbankselect for VALU.
   auto &IToFP = getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
-    .legalFor({{S32, S32}, {S64, S32}, {S16, S32}, {S32, S1}, {S16, S1}, {S64, S1}})
+    .legalFor({{S32, S32}, {S64, S32}, {S16, S32}})
     .lowerFor({{S32, S64}})
+    .lowerIf(typeIs(1, S1))
     .customFor({{S64, S64}});
   if (ST.has16BitInsts())
     IToFP.legalFor({{S16, S16}});
   IToFP.clampScalar(1, S32, S64)
        .scalarize(0);
 
   auto &FPToI = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
     .legalFor({{S32, S32}, {S32, S64}, {S32, S16}});

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir

bb.0:
     ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
     ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
     ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s16) = G_SITOFP %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 ...
-
----
-name: sitofp_s1_to_s32_s_scc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; WAVE64-LABEL: name: sitofp_s1_to_s32_s_scc
-    ; WAVE64: liveins: $sgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE64: $scc = COPY [[COPY1]]
-    ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 3212836864, implicit $scc
-    ; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
-    ; WAVE32-LABEL: name: sitofp_s1_to_s32_s_scc
-    ; WAVE32: liveins: $sgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE32: $scc = COPY [[COPY1]]
-    ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 3212836864, implicit $scc
-    ; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s32) = G_CONSTANT i32 0
-    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:sgpr(s32) = G_SITOFP %2
-    $sgpr0 = COPY %3
-...
-
----
-name: sitofp_s1_to_s16_to_s_scc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; WAVE64-LABEL: name: sitofp_s1_to_s16_to_s_scc
-    ; WAVE64: liveins: $sgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE64: $scc = COPY [[COPY1]]
-    ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 48128, implicit $scc
-    ; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
-    ; WAVE32-LABEL: name: sitofp_s1_to_s16_to_s_scc
-    ; WAVE32: liveins: $sgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE32: $scc = COPY [[COPY1]]
-    ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 48128, implicit $scc
-    ; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s32) = G_CONSTANT i32 0
-    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:sgpr(s16) = G_SITOFP %2
-    %4:sgpr(s32) = G_ANYEXT %3
-    $sgpr0 = COPY %4
-...
-
----
-name: sitofp_s1_to_s64_s_scc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; WAVE64-LABEL: name: sitofp_s1_to_s64_s_scc
-    ; WAVE64: liveins: $sgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE64: $scc = COPY [[COPY1]]
-    ; WAVE64: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, -4616189618054758400, implicit $scc
-    ; WAVE64: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
-    ; WAVE32-LABEL: name: sitofp_s1_to_s64_s_scc
-    ; WAVE32: liveins: $sgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE32: $scc = COPY [[COPY1]]
-    ; WAVE32: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, -4616189618054758400, implicit $scc
-    ; WAVE32: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s32) = G_CONSTANT i32 0
-    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:sgpr(s64) = G_SITOFP %2
-    $sgpr0_sgpr1 = COPY %3
-...
-
----
-name: sitofp_s1_to_s32_v_vcc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; WAVE64-LABEL: name: sitofp_s1_to_s32_v_vcc
-    ; WAVE64: liveins: $vgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 3212836864, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE64: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
-    ; WAVE32-LABEL: name: sitofp_s1_to_s32_v_vcc
-    ; WAVE32: liveins: $vgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 3212836864, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE32: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s32) = G_CONSTANT i32 0
-    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:vgpr(s32) = G_SITOFP %2
-    $vgpr0 = COPY %3
-...
-
----
-name: sitofp_s1_to_s16_to_v_vcc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; WAVE64-LABEL: name: sitofp_s1_to_s16_to_v_vcc
-    ; WAVE64: liveins: $vgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 3212836864, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
-    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
-    ; WAVE32-LABEL: name: sitofp_s1_to_s16_to_v_vcc
-    ; WAVE32: liveins: $vgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 3212836864, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
-    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s32) = G_CONSTANT i32 0
-    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:vgpr(s16) = G_SITOFP %2
-    %4:vgpr(s32) = G_ANYEXT %3
-    $vgpr0 = COPY %4
-...
-
----
-name: sitofp_s1_to_s64_v_vcc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; WAVE64-LABEL: name: sitofp_s1_to_s64_v_vcc
-    ; WAVE64: liveins: $vgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE64: [[V_CVT_F64_I32_e32_:%[0-9]+]]:vreg_64 = V_CVT_F64_I32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
-    ; WAVE64: $vgpr0_vgpr1 = COPY [[V_CVT_F64_I32_e32_]]
-    ; WAVE32-LABEL: name: sitofp_s1_to_s64_v_vcc
-    ; WAVE32: liveins: $vgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE32: [[V_CVT_F64_I32_e32_:%[0-9]+]]:vreg_64 = V_CVT_F64_I32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
-    ; WAVE32: $vgpr0_vgpr1 = COPY [[V_CVT_F64_I32_e32_]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s32) = G_CONSTANT i32 0
-    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:vgpr(s64) = G_SITOFP %2
-    $vgpr0_vgpr1 = COPY %3
-...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir

bb.0:
     ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
     ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
     ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s16) = G_UITOFP %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 ...
-
----
-name: uitofp_s1_to_s32_s_scc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; WAVE64-LABEL: name: uitofp_s1_to_s32_s_scc
-    ; WAVE64: liveins: $sgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE64: $scc = COPY [[COPY1]]
-    ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1065353216, implicit $scc
-    ; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
-    ; WAVE32-LABEL: name: uitofp_s1_to_s32_s_scc
-    ; WAVE32: liveins: $sgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE32: $scc = COPY [[COPY1]]
-    ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1065353216, implicit $scc
-    ; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s32) = G_CONSTANT i32 0
-    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:sgpr(s32) = G_UITOFP %2
-    $sgpr0 = COPY %3
-...
-
----
-name: uitofp_s1_to_s16_to_s_scc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; WAVE64-LABEL: name: uitofp_s1_to_s16_to_s_scc
-    ; WAVE64: liveins: $sgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE64: $scc = COPY [[COPY1]]
-    ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 15360, implicit $scc
-    ; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
-    ; WAVE32-LABEL: name: uitofp_s1_to_s16_to_s_scc
-    ; WAVE32: liveins: $sgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE32: $scc = COPY [[COPY1]]
-    ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 15360, implicit $scc
-    ; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s32) = G_CONSTANT i32 0
-    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:sgpr(s16) = G_UITOFP %2
-    %4:sgpr(s32) = G_ANYEXT %3
-    $sgpr0 = COPY %4
-...
-
----
-name: uitofp_s1_to_s64_s_scc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; WAVE64-LABEL: name: uitofp_s1_to_s64_s_scc
-    ; WAVE64: liveins: $sgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE64: $scc = COPY [[COPY1]]
-    ; WAVE64: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, 4607182418800017408, implicit $scc
-    ; WAVE64: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
-    ; WAVE32-LABEL: name: uitofp_s1_to_s64_s_scc
-    ; WAVE32: liveins: $sgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
-    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
-    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
-    ; WAVE32: $scc = COPY [[COPY1]]
-    ; WAVE32: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, 4607182418800017408, implicit $scc
-    ; WAVE32: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s32) = G_CONSTANT i32 0
-    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:sgpr(s64) = G_UITOFP %2
-    $sgpr0_sgpr1 = COPY %3
-...
-
----
-name: uitofp_s1_to_s32_v_vcc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; WAVE64-LABEL: name: uitofp_s1_to_s32_v_vcc
-    ; WAVE64: liveins: $vgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1065353216, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE64: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
-    ; WAVE32-LABEL: name: uitofp_s1_to_s32_v_vcc
-    ; WAVE32: liveins: $vgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1065353216, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE32: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s32) = G_CONSTANT i32 0
-    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:vgpr(s32) = G_UITOFP %2
-    $vgpr0 = COPY %3
-...
-
----
-name: uitofp_s1_to_s16_to_v_vcc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; WAVE64-LABEL: name: uitofp_s1_to_s16_to_v_vcc
-    ; WAVE64: liveins: $vgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1065353216, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
-    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
-    ; WAVE32-LABEL: name: uitofp_s1_to_s16_to_v_vcc
-    ; WAVE32: liveins: $vgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1065353216, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
-    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s32) = G_CONSTANT i32 0
-    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:vgpr(s16) = G_UITOFP %2
-    %4:vgpr(s32) = G_ANYEXT %3
-    $vgpr0 = COPY %4
-...
-
----
-name: uitofp_s1_to_s64_v_vcc
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; WAVE64-LABEL: name: uitofp_s1_to_s64_v_vcc
-    ; WAVE64: liveins: $vgpr0
-    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE64: [[V_CVT_F64_U32_e32_:%[0-9]+]]:vreg_64 = V_CVT_F64_U32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
-    ; WAVE64: $vgpr0_vgpr1 = COPY [[V_CVT_F64_U32_e32_]]
-    ; WAVE32-LABEL: name: uitofp_s1_to_s64_v_vcc
-    ; WAVE32: liveins: $vgpr0
-    ; WAVE32: $vcc_hi = IMPLICIT_DEF
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
-    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec
-    ; WAVE32: [[V_CVT_F64_U32_e32_:%[0-9]+]]:vreg_64 = V_CVT_F64_U32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
-    ; WAVE32: $vgpr0_vgpr1 = COPY [[V_CVT_F64_U32_e32_]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s32) = G_CONSTANT i32 0
-    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
-    %3:vgpr(s64) = G_UITOFP %2
-    $vgpr0_vgpr1 = COPY %3
-...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir

bb.0:
     ; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
     ; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
     ; GFX8: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
     %0:_(s32) = COPY $vgpr0
     %1:_(s8) = G_TRUNC %0
     %2:_(s64) = G_SITOFP %1
     $vgpr0_vgpr1 = COPY %2
 ...
+
+---
+name: test_sitofp_s1_to_s16
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GFX6-LABEL: name: test_sitofp_s1_to_s16
+    ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX6: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
+    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
+    ; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; GFX8-LABEL: name: test_sitofp_s1_to_s16
+    ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xHBC00
+    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
+    ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s1) = G_TRUNC %0
+    %2:_(s16) = G_SITOFP %1
+    %3:_(s32) = G_ANYEXT %2
+    $vgpr0 = COPY %3
+...
+
+---
+name: test_sitofp_s1_to_s32
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GFX6-LABEL: name: test_sitofp_s1_to_s32
+    ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
+    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX6: $vgpr0 = COPY [[SELECT]](s32)
+    ; GFX8-LABEL: name: test_sitofp_s1_to_s32
+    ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX8: $vgpr0 = COPY [[SELECT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s1) = G_TRUNC %0
+    %2:_(s32) = G_SITOFP %1
+    $vgpr0 = COPY %2
+...
+
+---
+name: test_sitofp_s1_to_s64
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GFX6-LABEL: name: test_sitofp_s1_to_s64
+    ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX6: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
+    ; GFX6: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX6: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
+    ; GFX8-LABEL: name: test_sitofp_s1_to_s64
+    ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX8: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s1) = G_TRUNC %0
+    %2:_(s64) = G_SITOFP %1
+    $vgpr0_vgpr1 = COPY %2
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir

bb.0:
     ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; GFX8: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
     ; GFX8: $vgpr0_vgpr1 = COPY [[UITOFP]](s64)
     %0:_(s32) = COPY $vgpr0
     %1:_(s8) = G_TRUNC %0
     %2:_(s64) = G_UITOFP %1
     $vgpr0_vgpr1 = COPY %2
 ...
+
+---
+name: test_uitofp_s1_to_s16
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GFX6-LABEL: name: test_uitofp_s1_to_s16
+    ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX6: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+    ; GFX6: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
+    ; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; GFX8-LABEL: name: test_uitofp_s1_to_s16
+    ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+    ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
+    ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s1) = G_TRUNC %0
+    %2:_(s16) = G_UITOFP %1
+    %3:_(s32) = G_ANYEXT %2
+    $vgpr0 = COPY %3
+...
+
+---
+name: test_uitofp_s1_to_s32
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GFX6-LABEL: name: test_uitofp_s1_to_s32
+    ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX6: $vgpr0 = COPY [[SELECT]](s32)
+    ; GFX8-LABEL: name: test_uitofp_s1_to_s32
+    ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX8: $vgpr0 = COPY [[SELECT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s1) = G_TRUNC %0
+    %2:_(s32) = G_UITOFP %1
+    $vgpr0 = COPY %2
+...
+
+---
+name: test_uitofp_s1_to_s64
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GFX6-LABEL: name: test_uitofp_s1_to_s64
+    ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX6: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+    ; GFX6: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX6: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX6: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
+    ; GFX8-LABEL: name: test_uitofp_s1_to_s64
+    ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+    ; GFX8: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
+    ; GFX8: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s1) = G_TRUNC %0
+    %2:_(s64) = G_UITOFP %1
+    $vgpr0_vgpr1 = COPY %2
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir

body: |
   bb.0:
     liveins: $vgpr0
     ; CHECK-LABEL: name: sitofp_v
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[COPY]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_SITOFP %0
 ...
-
----
-name: sitofp_s_s1
-legalized: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-    ; CHECK-LABEL: name: sitofp_s_s1
-    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
-    ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
-    ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[ICMP]](s1)
-    %0:_(s32) = COPY $sgpr0
-    %1:_(s32) = G_CONSTANT i32 0
-    %2:_(s1) = G_ICMP intpred(eq), %0, %1
-    %3:_(s32) = G_SITOFP %2
-...
-
----
-name: sitofp_v_s1
-legalized: true
-
-body: |
-  bb.0:
-    liveins: $vgpr0
-    ; CHECK-LABEL: name: sitofp_v_s1
-    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
-    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
-    ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[ICMP]](s1)
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s32) = G_CONSTANT i32 0
-    %2:_(s1) = G_ICMP intpred(eq), %0, %1
-    %3:_(s32) = G_SITOFP %2
-...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir

body: |
   bb.0:
     liveins: $vgpr0
     ; CHECK-LABEL: name: uitofp_v
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[COPY]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_UITOFP %0
 ...
-
----
-name: uitofp_s_s1
-legalized: true
-
-body: |
-  bb.0:
-    liveins: $sgpr0
-    ; CHECK-LABEL: name: uitofp_s_s1
-    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
-    ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
-    ; CHECK: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[ICMP]](s1)
-    %0:_(s32) = COPY $sgpr0
-    %1:_(s32) = G_CONSTANT i32 0
-    %2:_(s1) = G_ICMP intpred(eq), %0, %1
-    %3:_(s32) = G_UITOFP %2
-...
-
----
-name: uitofp_v_s1
-legalized: true
-
-body: |
-  bb.0:
-    liveins: $vgpr0
-    ; CHECK-LABEL: name: uitofp_v_s1
-    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
-    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
-    ; CHECK: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[ICMP]](s1)
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s32) = G_CONSTANT i32 0
-    %2:_(s1) = G_ICMP intpred(eq), %0, %1
-    %3:_(s32) = G_UITOFP %2
-...