[mips][FastISel] Implement div instruction.

[vkalintiris]

Summary

Implement div in MIPS FastISel.

Based on a patch by Reed Kotler.

[dsanders]

lib/Target/Mips/MipsFastISel.cpp

1621–1655

This should be merged with the near-identical selectRem added in D7027 to make a selectDivRem which uses mfhi/mflo depending on whether div/rem is desired.

test/CodeGen/Mips/Fast-ISel/div1.ll

12

As mentioned in D6774, we can significantly simplify this using arguments and returns.

As noted there, I don't mind if this is part of the big cleanup.

[vkalintiris]

Cleaned-up tests and merged implementation of selectDiv() with the
implementation of selectRem() under the new name: selectDivRem().

[dsanders]

LGTM with a couple nits

lib/Target/Mips/MipsFastISel.cpp

99

Nit: Not needed anymore.

99

Not done.

1556–1558

Nit: Use ternary operator

test/CodeGen/Mips/Fast-ISel/div1.ll

12

Not done, but I'm ok with this tidy up being in the cleanup so this is not a problem.

lib/Target/Mips/MipsFastISel.cpp

private:
   bool selectLoad(const Instruction *I);
   bool selectStore(const Instruction *I);
   bool selectBranch(const Instruction *I);
   bool selectSelect(const Instruction *I);
   bool selectCmp(const Instruction *I);
   bool selectFPExt(const Instruction *I);
   bool selectFPTrunc(const Instruction *I);
   bool selectFPToInt(const Instruction *I, bool IsSigned);
   bool selectRem(const Instruction *I, unsigned ISDOpcode);
   bool selectRet(const Instruction *I);
   bool selectTrunc(const Instruction *I);
   bool selectIntExt(const Instruction *I);
   bool selectShift(const Instruction *I);
+  bool selectDiv(const Instruction *I, unsigned ISDOpcode);
 
   // Utility helper routines.
   bool isTypeLegal(Type *Ty, MVT &VT);
   bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
   bool isValueAvailable(const Value *V) const;
   bool isLoadTypeLegal(Type *Ty, MVT &VT);
   bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
   bool computeCallAddress(const Value *V, Address &Addr);
bool MipsFastISel::selectRem(const Instruction *I, unsigned ISDOpcode) {
   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
   if (!ResultReg)
     return false;
   emitInst(Mips::MFHI, ResultReg);
   updateValueMap(I, ResultReg);
   return true;
 }
 
 bool MipsFastISel::selectShift(const Instruction *I) {
   MVT RetVT;
   if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/false))
     return false;
   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
   if (!ResultReg)
     return false;
   unsigned Opcode = I->getOpcode();
   const Value *Op0 = I->getOperand(0);
   unsigned Op0Reg = getRegForValue(Op0);
   if (!Op0Reg)
case Instruction::LShr:
     Opcode = Mips::SRLV;
     break;
   }
   emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
   updateValueMap(I, ResultReg);
   return true;
 }
 
+bool MipsFastISel::selectDiv(const Instruction *I, unsigned ISDOpcode) {
+  EVT DestEVT = TLI.getValueType(I->getType(), true);
+  if (!DestEVT.isSimple())
+    return false;
+
+  MVT DestVT = DestEVT.getSimpleVT();
+  if (DestVT != MVT::i32)
+    return false;
+  unsigned DivOpc;
+  switch (ISDOpcode) {
+  default:
+    return false;
+  case ISD::SDIV:
+    DivOpc = Mips::SDIV;
+    break;
+  case ISD::UDIV:
+    DivOpc = Mips::UDIV;
+    break;
+  }
+  unsigned Src0Reg = getRegForValue(I->getOperand(0));
+  if (!Src0Reg)
+    return false;
+  unsigned Src1Reg = getRegForValue(I->getOperand(1));
+  if (!Src1Reg)
+    return false;
+  emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
+  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
+  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
+  if (!ResultReg)
+    return false;
+  emitInst(Mips::MFLO, ResultReg);
+  updateValueMap(I, ResultReg);
+  return true;
+}
+
 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
   if (!TargetSupported)
     return false;
   switch (I->getOpcode()) {
   default:
     break;
   case Instruction::Load:
     return selectLoad(I);
   case Instruction::Store:
     return selectStore(I);
+  case Instruction::SDiv:
+    if (!selectBinaryOp(I, ISD::SDIV))
+      return selectDiv(I, ISD::SDIV);
+    return true;
+  case Instruction::UDiv:
+    if (!selectBinaryOp(I, ISD::UDIV))
+      return selectDiv(I, ISD::UDIV);
+    return true;
   case Instruction::SRem:
     if (!selectBinaryOp(I, ISD::SREM))
       return selectRem(I, ISD::SREM);
     return true;
   case Instruction::URem:
     if (!selectBinaryOp(I, ISD::UREM))
       return selectRem(I, ISD::UREM);
     return true;

test/CodeGen/Mips/Fast-ISel/div1.ll

+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+
+@sj = global i32 200000, align 4
+@sk = global i32 -47, align 4
+@uj = global i32 200000, align 4
+@uk = global i32 43, align 4
+@si = common global i32 0, align 4
+@ui = common global i32 0, align 4
+
+; Function Attrs: noinline nounwind
+define void @divs() #0 {
+entry:
+; CHECK-LABEL:  .ent  divs 
+  %0 = load i32* @sj, align 4
+  %1 = load i32* @sk, align 4
+  %div = sdiv i32 %0, %1
+  store i32 %div, i32* @si, align 4
+; CHECK:        lui     $[[GOT1:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
+; CHECK:        addu    $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
+; CHECK-DAG:    lw      $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]])
+; CHECK-DAG:    lw      $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]])
+; CHECK-DAG:    lw      $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]])
+; CHECK-DAG:    lw      $[[J:[0-9]+]], 0($[[J_ADDR]])
+; CHECK-DAG:    lw      $[[K:[0-9]+]], 0($[[K_ADDR]])
+; CHECK-DAG:  div $zero, $[[J]], $[[K]]
+; CHECK_DAG:  teq $[[K]], $zero, 7
+; CHECK-DAG:  mflo  $[[RESULT:[0-9]+]]
+; CHECK:  sw  $[[RESULT]], 0($[[I_ADDR]])
+
+  ret void
+}
+
+; Function Attrs: noinline nounwind
+define void @divu() #0 {
+entry:
+; CHECK-LABEL:  .ent  divu 
+  %0 = load i32* @uj, align 4
+  %1 = load i32* @uk, align 4
+  %div = udiv i32 %0, %1
+  store i32 %div, i32* @ui, align 4
+; CHECK:        lui     $[[GOT1:[0-9]+]], %hi(_gp_disp)
+; CHECK:        addiu   $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp)
+; CHECK:        addu    $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25
+; CHECK-DAG:    lw      $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]])
+; CHECK-DAG:    lw      $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]])
+; CHECK-DAG:    lw      $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]])
+; CHECK-DAG:    lw      $[[J:[0-9]+]], 0($[[J_ADDR]])
+; CHECK-DAG:    lw      $[[K:[0-9]+]], 0($[[K_ADDR]])
+; CHECK-DAG:  divu  $zero, $[[J]], $[[K]]
+; CHECK_DAG:  teq $[[K]], $zero, 7
+; CHECK-DAG:  mflo  $[[RESULT:[0-9]+]]
+; CHECK:  sw  $[[RESULT]], 0($[[I_ADDR]])
+  ret void
+}
+
+; Function Attrs: nounwind
+define i32 @main() #1 {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  call void @divs()
+  call void @divu()
+  %0 = load i32* @si, align 4
+  %cmp = icmp ne i32 %0, -4255
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  call void @abort() #3
+  unreachable
+
+if.end:                                           ; preds = %entry
+  %1 = load i32* @ui, align 4
+  %cmp1 = icmp ne i32 %1, 4651
+  br i1 %cmp1, label %if.then2, label %if.end3
+
+if.then2:                                         ; preds = %if.end
+  call void @abort() #3
+  unreachable
+
+if.end3:                                          ; preds = %if.end
+  ret i32 0
+}
+
+; Function Attrs: noreturn
+declare void @abort() #2
+
+attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { noreturn "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { noreturn }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 3.7.0 ([e-mail]:clang.git 1d11866537a9bf722c9c5b516151c23434242e24) ([e-mail]:llvm.git bad245f051b31c78846be1afe26a31eb2337deb2)"}