[AMDGPU][MC][GFX10] Enabled v_movrel*[sdwa|dpp|dpp8] opcodes

[dp]

Summary

See https://bugs.llvm.org/show_bug.cgi?id=43712

[rampitec]

LGTM with a nit: please remove the comment.

llvm/lib/Target/AMDGPU/VOP1Instructions.td

282

I do not think you can really limit it to asm only. If you have defined it then eventually compiler may combine it. I'd suggest to remove the comment.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

private:
   bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
   bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
   bool validateSOPLiteral(const MCInst &Inst) const;
   bool validateConstantBusLimitations(const MCInst &Inst);
   bool validateEarlyClobberLimitations(const MCInst &Inst);
   bool validateIntClampSupported(const MCInst &Inst);
   bool validateMIMGAtomicDMask(const MCInst &Inst);
   bool validateMIMGGatherDMask(const MCInst &Inst);
+  bool validateMovrels(const MCInst &Inst);
   bool validateMIMGDataSize(const MCInst &Inst);
   bool validateMIMGAddrSize(const MCInst &Inst);
   bool validateMIMGD16(const MCInst &Inst);
   bool validateMIMGDim(const MCInst &Inst);
   bool validateLdsDirect(const MCInst &Inst);
   bool validateOpSel(const MCInst &Inst);
   bool validateVccOperand(unsigned Reg) const;
   bool validateVOP3Literal(const MCInst &Inst) const;
bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {
   // GATHER4 instructions use dmask in a different fashion compared to
   // other MIMG instructions. The only useful DMASK values are
   // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
   // (red,red,red,red) etc.) The ISA document doesn't mention
   // this.
   return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8;
 }
 
+static bool IsMovrelsSDWAOpcode(const unsigned Opcode)
+{
+  switch (Opcode) {
+  case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:
+  case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:
+  case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:
+    return true;
+  default:
+    return false;
+  }
+}
+
+// movrels* opcodes should only allow VGPRS as src0.
+// This is specified in .td description for vop1/vop3,
+// but sdwa is handled differently. See isSDWAOperand.
+bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst) {
+
+  const unsigned Opc = Inst.getOpcode();
+  const MCInstrDesc &Desc = MII.get(Opc);
+
+  if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc))
+    return true;
+
+  const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
+  assert(Src0Idx != -1);
+  
+  const MCOperand &Src0 = Inst.getOperand(Src0Idx);
+  if (!Src0.isReg())
+    return false;
+
+  auto Reg = Src0.getReg();
+  const MCRegisterInfo *TRI = getContext().getRegisterInfo();
+  return !isSGPR(mc2PseudoReg(Reg), TRI);
+}
+
 bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
 
   const unsigned Opc = Inst.getOpcode();
   const MCInstrDesc &Desc = MII.get(Opc);
 
   if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)
     return true;
 
Error(IDLoc,
       "invalid atomic image dmask");
     return false;
   }
   if (!validateMIMGGatherDMask(Inst)) {
     Error(IDLoc,
       "invalid image_gather dmask: only one bit must be set");
     return false;
   }
+  if (!validateMovrels(Inst)) {
+    Error(IDLoc, "source operand must be a VGPR");
+    return false;
+  }
   if (!validateFlatOffset(Inst, Operands)) {
     return false;
   }
 
   return true;
 }
 
 static std::string AMDGPUMnemonicSpellCheck(StringRef S,

llvm/lib/Target/AMDGPU/VOP1Instructions.td

 defm V_FREXP_EXP_I32_F32 : VOP1Inst <"v_frexp_exp_i32_f32", VOP_I32_F32, int_amdgcn_frexp_exp>;
 defm V_FREXP_MANT_F32 : VOP1Inst <"v_frexp_mant_f32", VOP_F32_F32, int_amdgcn_frexp_mant>;
 
 let VOPAsmPrefer32Bit = 1 in {
 defm V_CLREXCP : VOP1Inst <"v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
 }
 
 // Restrict src0 to be VGPR
-def VOP_I32_VI32_NO_EXT : VOPProfile<[i32, i32, untyped, untyped]> {
+def VOP_MOVRELS : VOPProfile<[i32, i32, untyped, untyped]> {
   let Src0RC32 = VRegSrc_32;
   let Src0RC64 = VRegSrc_32;
-
-  let HasExt = 0;
-  let HasExtDPP = 0;
-  let HasExtSDWA = 0;
-  let HasExtSDWA9 = 0;
 }
 
 // Special case because there are no true output operands.  Hack vdst
 // to be a src operand. The custom inserter must add a tied implicit
 // def and use of the super register since there seems to be no way to
 // add an implicit def of a virtual register in tablegen.
 class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
   let Src0RC32 = VOPDstOperand<VGPR_32>;
   let Src0RC64 = VOPDstOperand<VGPR_32>;
 
   let Outs = (outs);
   let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
   let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
-  let InsDPP = (ins DstRC:$vdst, DstRC:$old, Src0RC32:$src0,
-                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
-                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
-  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
-
-  let InsSDWA = (ins Src0RC32:$vdst, Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
-                     clampmod:$clamp, omod:$omod, dst_sel:$dst_sel, dst_unused:$dst_unused,
-                     src0_sel:$src0_sel);
-
   let Asm32 = getAsm32<1, 1>.ret;
   let Asm64 = getAsm64<1, 1, 0, 0, 1>.ret;
-  let AsmDPP = getAsmDPP<1, 1, 0>.ret;
-  let AsmDPP16 = getAsmDPP16<1, 1, 0>.ret;
-  let AsmSDWA = getAsmSDWA<1, 1>.ret;
-  let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;
-
-  let HasExt = 0;
-  let HasExtDPP = 0;
-  let HasExtSDWA = 0;
-  let HasExtSDWA9 = 0;
+
+  // sdwa/dpp/dpp8 are defined with dst - for use in assembler only.
+
+  let OutsSDWA = (outs Src0RC32:$vdst);
+  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
+                     clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
+                     src0_sel:$src0_sel);
+  let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;
+
+  let OutsDPP = (outs Src0RC32:$vdst);
+  let InsDPP16 = (ins Src0RC32:$old, Src0RC32:$src0,
+                      dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
+                      bank_mask:$bank_mask, bound_ctrl:$bound_ctrl, FI:$fi);
+  let AsmDPP16 = getAsmDPP16<1, 1, 0>.ret;
+
+  let OutsDPP8 = (outs Src0RC32:$vdst);
+  let InsDPP8 = (ins Src0RC32:$old, Src0RC32:$src0, dpp8:$dpp8, FI:$fi);
+  let AsmDPP8 = getAsmDPP8<1, 1, 0>.ret;
 
   let HasDst = 0;
   let EmitDst = 1; // force vdst emission
 }
 
 def VOP_MOVRELD : VOP_MOVREL<VSrc_b32>;
 def VOP_MOVRELSD : VOP_MOVREL<VRegSrc_32>;
 
 let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {
  // v_movreld_b32 is a special case because the destination output
  // register is really a source. It isn't actually read (but may be
  // written), and is only to provide the base register to start
  // indexing from. Tablegen seems to not let you define an implicit
  // virtual register output for the super register being written into,
  // so this must have an implicit def of the register added to it.
-defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>;
-defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_I32_VI32_NO_EXT>;
-defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>;
+defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>;
+defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_MOVRELS>;
+defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>;
 } // End Uses = [M0, EXEC]
 
 defm V_MOV_FED_B32 : VOP1Inst <"v_mov_fed_b32", VOP_I32_I32>;
 
 let SubtargetPredicate = isGFX6GFX7 in {
   let SchedRW = [WriteQuarterRate32] in {
     defm V_LOG_CLAMP_F32 :
       VOP1Inst<"v_log_clamp_f32", VOP_F32_F32, int_amdgcn_log_clamp>;
let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
   multiclass VOP1_Real_dpp8_gfx10<bits<9> op> {
     foreach _ = BoolToList<!cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
     def _dpp8_gfx10 : VOP1_DPP8<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32")> {
       let DecoderNamespace = "DPP8";
     }
   }
 } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
 
-multiclass VOP1_Real_gfx10_no_dpp<bits<9> op> :
-  VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
-  VOP1_Real_sdwa_gfx10<op>;
-
-multiclass VOP1_Real_gfx10_no_dpp8<bits<9> op> :
-  VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
-  VOP1_Real_sdwa_gfx10<op>, VOP1_Real_dpp_gfx10<op>;
-
 multiclass VOP1_Real_gfx10<bits<9> op> :
-  VOP1_Real_gfx10_no_dpp8<op>, VOP1_Real_dpp8_gfx10<op>;
+  VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
+  VOP1_Real_sdwa_gfx10<op>, VOP1_Real_dpp_gfx10<op>,
+  VOP1_Real_dpp8_gfx10<op>;
 
 defm V_PIPEFLUSH         : VOP1_Real_gfx10<0x01b>;
 defm V_MOVRELSD_2_B32    : VOP1_Real_gfx10<0x048>;
 defm V_CVT_F16_U16       : VOP1_Real_gfx10<0x050>;
 defm V_CVT_F16_I16       : VOP1_Real_gfx10<0x051>;
 defm V_CVT_U16_F16       : VOP1_Real_gfx10<0x052>;
 defm V_CVT_I16_F16       : VOP1_Real_gfx10<0x053>;
 defm V_RCP_F16           : VOP1_Real_gfx10<0x054>;

 } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
 
 multiclass VOP1_Real_gfx6_gfx7<bits<9> op> :
   VOP1_Real_e32_gfx6_gfx7<op>, VOP1_Real_e64_gfx6_gfx7<op>;
 
 multiclass VOP1_Real_gfx6_gfx7_gfx10<bits<9> op> :
   VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10<op>;
 
-multiclass VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<bits<9> op> :
-  VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10_no_dpp8<op>;
-
-multiclass VOP1_Real_gfx6_gfx7_gfx10_no_dpp<bits<9> op> :
-  VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10_no_dpp<op>;
-
 defm V_LOG_CLAMP_F32  : VOP1_Real_gfx6_gfx7<0x026>;
 defm V_RCP_CLAMP_F32  : VOP1_Real_gfx6_gfx7<0x028>;
 defm V_RCP_LEGACY_F32 : VOP1_Real_gfx6_gfx7<0x029>;
 defm V_RSQ_CLAMP_F32  : VOP1_Real_gfx6_gfx7<0x02c>;
 defm V_RSQ_LEGACY_F32 : VOP1_Real_gfx6_gfx7<0x02d>;
 defm V_RCP_CLAMP_F64  : VOP1_Real_gfx6_gfx7<0x030>;
 defm V_RSQ_CLAMP_F64  : VOP1_Real_gfx6_gfx7<0x032>;
 

 defm V_FFBL_B32          : VOP1_Real_gfx6_gfx7_gfx10<0x03a>;
 defm V_FFBH_I32          : VOP1_Real_gfx6_gfx7_gfx10<0x03b>;
 defm V_FREXP_EXP_I32_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x03c>;
 defm V_FREXP_MANT_F64    : VOP1_Real_gfx6_gfx7_gfx10<0x03d>;
 defm V_FRACT_F64         : VOP1_Real_gfx6_gfx7_gfx10<0x03e>;
 defm V_FREXP_EXP_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x03f>;
 defm V_FREXP_MANT_F32    : VOP1_Real_gfx6_gfx7_gfx10<0x040>;
 defm V_CLREXCP           : VOP1_Real_gfx6_gfx7_gfx10<0x041>;
-defm V_MOVRELD_B32       : VOP1_Real_gfx6_gfx7_gfx10_no_dpp<0x042>;
-defm V_MOVRELS_B32       : VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<0x043>;
-defm V_MOVRELSD_B32      : VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<0x044>;
+defm V_MOVRELD_B32       : VOP1_Real_gfx6_gfx7_gfx10<0x042>;
+defm V_MOVRELS_B32       : VOP1_Real_gfx6_gfx7_gfx10<0x043>;
+defm V_MOVRELSD_B32      : VOP1_Real_gfx6_gfx7_gfx10<0x044>;
 
 //===----------------------------------------------------------------------===//
 // GFX8, GFX9 (VI).
 //===----------------------------------------------------------------------===//
 
 class VOP1_DPPe <bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
   VOP_DPPe <P> {
   bits<8> vdst;

llvm/test/MC/AMDGPU/gfx10_asm_all.s

 v_movreld_b32_e64 v5, -4.0
 // GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xf7,0x00,0x00,0x00]
 
+v_movreld_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movreld_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00]
+
+v_movreld_b32_sdwa v0, 64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00]
+
+v_movreld_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
 v_movrels_b32 v5, v1
 // GFX10: encoding: [0x01,0x87,0x0a,0x7e]
 

 v_movrels_b32_e64 v5, v255
 // GFX10: encoding: [0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
 
+v_movrels_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrels_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrels_b32_e32 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrels_b32_e32 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrels_b32_e64 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrels_b32_e64 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrels_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
+v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
 v_movrelsd_b32 v5, v1
 // GFX10: encoding: [0x01,0x89,0x0a,0x7e]
 

 v_movrelsd_b32_e64 v5, v255
 // GFX10: encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
 
-v_movrelsd_b32 v5, s1
+v_movrelsd_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrelsd_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00]
+
+v_movrelsd_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrelsd_b32_e32 v5, s1
 // GFX10-ERR: error: invalid operand for instruction
 
+v_movrelsd_b32_e32 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_b32_e64 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_b32_e64 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
+v_movrelsd_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
 v_movrelsd_2_b32 v5, v1
 // GFX10: encoding: [0x01,0x91,0x0a,0x7e]
 

 v_movrelsd_2_b32_e64 v5, v255
 // GFX10: encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
 
-v_movrelsd_2_b32 v5, s1
+v_movrelsd_2_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrelsd_2_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00]
+
+v_movrelsd_2_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrelsd_2_b32_e32 v5, s1
 // GFX10-ERR: error: invalid operand for instruction
 
+v_movrelsd_2_b32_e32 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_2_b32_e64 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_2_b32_e64 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_2_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
+v_movrelsd_2_b32_sdwa v0, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
+v_movrelsd_2_b32_sdwa v0, null dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
 v_cvt_f16_u16_e32 v5, v1
 // GFX10: encoding: [0x01,0xa1,0x0a,0x7e]
 

llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s

 
 v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 // GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
+
+v_movreld_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: [0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00]
+
+v_movrels_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX10: [0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00]
+
+v_movrelsd_2_b32_dpp v0, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: [0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00]
+
+v_movrelsd_b32_dpp v0, v255 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: [0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00]

llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s

 
 v_mac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
 // GFX10: v_mac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05]
+
+v_movreld_b32 v0, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX10: [0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05]
+
+v_movrels_b32 v0, v2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX10: [0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00]
+
+v_movrelsd_2_b32 v0, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX10: [0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05]
+
+v_movrelsd_b32 v0, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX10: [0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05]

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 # GFX10: v_movreld_b32_e64 v5, v255      ; encoding: [0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00]
 0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00
 
+# GFX10: v_movreld_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00]
+0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00
+
+# GFX10: v_movreld_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00]
+0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00
+
+# GFX10: v_movreld_b32_sdwa v0, 64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00]
+0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00
+
+# GFX10: v_movreld_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00]
+0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00
+
 # GFX10: v_movrels_b32_e32 v255, v1      ; encoding: [0x01,0x87,0xfe,0x7f]
 0x01,0x87,0xfe,0x7f
 

 # GFX10: v_movrels_b32_e64 v5, v255      ; encoding: [0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
 0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00
 
+# GFX10: v_movrels_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00]
+0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00
+
+# GFX10: v_movrels_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00]
+0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00
+
 # GFX10: v_movrelsd_2_b32_e32 v255, v1   ; encoding: [0x01,0x91,0xfe,0x7f]
 0x01,0x91,0xfe,0x7f
 

 # GFX10: v_movrelsd_2_b32_e64 v5, v255   ; encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
 0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00
 
+# GFX10: v_movrelsd_2_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00]
+0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00
+
+# GFX10: v_movrelsd_2_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00]
+0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00
+
+# GFX10: v_movrelsd_2_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00]
+0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00
+
 # GFX10: v_movrelsd_b32_e32 v255, v1     ; encoding: [0x01,0x89,0xfe,0x7f]
 0x01,0x89,0xfe,0x7f
 

 # GFX10: v_movrelsd_b32_e64 v5, v255     ; encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
 0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00
 
+# GFX10: v_movrelsd_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00]
+0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00
+
+# GFX10: v_movrelsd_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00]
+0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00
+
+# GFX10: v_movrelsd_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00]
+0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00
+
 # GFX10: v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4] ; encoding: [0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04]
 0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04
 

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_dpp16.txt

 
 # GFX10: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
 0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00
+
+# GFX10: v_movreld_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00]
+0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00
+
+# GFX10: v_movrels_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00]
+0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00
+
+# GFX10: v_movrelsd_2_b32_dpp v0, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00]
+0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00
+
+# GFX10: v_movrelsd_b32_dpp v0, v255 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00]
+0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_dpp8.txt

 
 # GFX10: v_mac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05]
 0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05
+
+# GFX10: v_movreld_b32_dpp v0, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05]
+0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05
+
+# GFX10: v_movrels_b32_dpp v0, v2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00]
+0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00
+
+# GFX10: v_movrelsd_2_b32_dpp v0, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05]
+0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05
+
+# GFX10: v_movrelsd_b32_dpp v0, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05]
+0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05