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[PoC][RISC-V][Vext] Unify masked and unmasked instructions
AbandonedPublic

Authored by rogfer01 on Nov 11 2019, 9:38 AM.

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Summary

(Not to be committed)

This is a PoC built on top of D69987

The goal is to halve the number of Instructions for V-ext by representing a mask as a register homogeneously: RISCV::V0 for instructions with mask (like vadd.vv v1, v2, v3, v0.t) and RISCV::NoRegister for instructions without mask (like vadd.vv v1, v2, v3).

This way we don't have VADD_VV and VADD_VV_T but just VADD_VV with an operand that is the mask.

Changes:

  • Mark the VPRMaskAsmOperand operand IsOptional, this allows it to be left empty in the instruction. If unspecified default make it be RISCV::NoRegister using defaultRVVMask.
  • Actually encode vm in the instruction instead of making it a parameter of the class of the instruction format
  • Encode, decode and print the mask operand as expected (i.e. RISCV::V0v0.t and RISCV::NoRegister ↔ "no mask")

Pros:

  • Half the number of instructions
  • Same number of operands both unmasked and masked instances of the same instruction

Cons:

  • The function RISCVAsmParser::validateInstruction might be a bit harder to write (not done in this patch)

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