[PoC][RISC-V][Vext] Unify masked and unmasked instructions

[rogfer01]

Summary

(Not to be committed)

This is a PoC built on top of D69987

The goal is to halve the number of Instructions for V-ext by representing a mask as a register homogeneously: RISCV::V0 for instructions with mask (like vadd.vv v1, v2, v3, v0.t) and RISCV::NoRegister for instructions without mask (like vadd.vv v1, v2, v3).

This way we don't have VADD_VV and VADD_VV_T but just VADD_VV with an operand that is the mask.

Changes:

• Mark the VPRMaskAsmOperand operand IsOptional, this allows it to be left empty in the instruction. If unspecified default make it be RISCV::NoRegister using defaultRVVMask.
• Actually encode vm in the instruction instead of making it a parameter of the class of the instruction format
• Encode, decode and print the mask operand as expected (i.e. RISCV::V0 ↔ v0.t and RISCV::NoRegister ↔ "no mask")

Pros:

• Half the number of instructions
• Same number of operands both unmasked and masked instances of the same instruction

Cons:

• The function RISCVAsmParser::validateInstruction might be a bit harder to write (not done in this patch)

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/RISCVAsmBackend.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "MCTargetDesc/RISCVTargetStreamer.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "Utils/RISCVBaseInfo.h"
 #include "Utils/RISCVMatInt.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallBitVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/CodeGen/Register.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
if (FeatureBitStack.empty())
       return true;
 
     FeatureBitset FeatureBits = FeatureBitStack.pop_back_val();
     copySTI().setFeatureBits(FeatureBits);
     setAvailableFeatures(ComputeAvailableFeatures(FeatureBits));
 
     return false;
   }
+
+  std::unique_ptr<RISCVOperand> defaultRVVMask() const;
+
 public:
   enum RISCVMatchResultTy {
     Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "RISCVGenAsmMatcher.inc"
 #undef GET_OPERAND_DIAGNOSTIC_TYPES
   };
 
RISCVFPRndMode::RoundingMode getRoundingMode() const {
     assert(FRM != RISCVFPRndMode::Invalid && "Invalid rounding mode");
     return FRM;
   }
 
   void addFRMArgOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(getRoundingMode()));
   }
+
 };
 } // end anonymous namespace.
 
+std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultRVVMask() const {
+  return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(),
+                                 llvm::SMLoc(), isRV64());
+}
+
 #define GET_REGISTER_MATCHER
 #define GET_MATCHER_IMPLEMENTATION
 #include "RISCVGenAsmMatcher.inc"
 
 static Register convertFPR64ToFPR32(Register Reg) {
   assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
   return Reg - RISCV::F0_D + RISCV::F0_F;
 }
return Error(ErrorLoc, "the second input operand must be tp/x4 when using "
                            "%tprel_add modifier");
   }
 
   return false;
 }
 
 bool RISCVAsmParser::validateInstruction(MCInst &Inst,
                                          OperandVector &Operands) {
+  // FIXME!
+  // We should look at the mask operand if any and update this code for the
+  // proper diagnostics.
+  return false;
+
+#if 0
   SMLoc Loc = Operands[0]->getStartLoc();
   const unsigned Opcode = Inst.getOpcode();
   switch (Opcode) {
   case RISCV::VWADDU_VV_T:
   case RISCV::VWADDU_VX_T:
   case RISCV::VWSUBU_VV_T:
   case RISCV::VWSUBU_VX_T:
   case RISCV::VWADD_VV_T:
if (DestReg == Src2Reg)
           Loc, "The destination vector register group cannot overlap"
                " the source vector register group.");
     break;
   }
   default:
     return false;
   }
   return false;
+#endif
 }
 
 bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
                                         OperandVector &Operands,
                                         MCStreamer &Out) {
   Inst.setLoc(IDLoc);
 
   switch (Inst.getOpcode()) {

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

static DecodeStatus DecodeVPRRegisterClass(MCInst &Inst, uint64_t RegNo,
   if (RegNo >= 32)
     return MCDisassembler::Fail;
 
   Register Reg = RISCV::V0 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeVPRV0RegisterClass(MCInst &Inst, uint64_t RegNo,
+                                             uint64_t Address,
+                                             const void *Decoder) {
+  Register Reg = RISCV::NoRegister;
+  switch (RegNo) {
+  default:
+    return MCDisassembler::Fail;
+  case 0:
+    Reg = RISCV::V0;
+    break;
+  case 1:
+    break;
+  }
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 // Add implied SP operand for instructions *SP compressed instructions. The SP
 // operand isn't explicitly encoded in the instruction.
 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
   if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
       Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
       Inst.getOpcode() == RISCV::C_FLWSP ||
       Inst.getOpcode() == RISCV::C_FSWSP ||
       Inst.getOpcode() == RISCV::C_FLDSP ||

 }
 
 static void addImplyVMask(MCInst &Inst, uint32_t Insn,
                           const MCInstrInfo &MCII) {
   MCInstrDesc const &Desc = MCII.get(Inst.getOpcode());
   if (Desc.TSFlags & RISCVII::InstVectorWithMask) {
     if ((Insn & (0x1 << 25)) == 0)
       Inst.addOperand(MCOperand::createReg(RISCV::V0));
+    else
+      Inst.addOperand(MCOperand::createReg(RISCV::NoRegister));
   }
 }
 
 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                                ArrayRef<uint8_t> Bytes,
                                                uint64_t Address,
                                                raw_ostream &OS,
                                                raw_ostream &CS) const {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

 }
 
 void RISCVInstPrinter::printVPRMaskOp(const MCInst *MI, unsigned OpNo,
                                       const MCSubtargetInfo &STI,
                                       raw_ostream &O) {
   const MCOperand &MO = MI->getOperand(OpNo);
 
   assert(MO.isReg() && "printVPRMaskOp can only print register operands");
+  if (MO.getReg() == RISCV::NoRegister)
+    return;
+  O << ", ";
   printRegName(O, MO.getReg());
   O << ".t";
-  return;
 }
 
 const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) {
   return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
                                              : RISCV::ABIRegAltName);
 }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

public:
 
   unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
   unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const;
+
+  unsigned getVPRMaskOp(const MCInst &MI, unsigned OpNo,
+                        SmallVectorImpl<MCFixup> &Fixups,
+                        const MCSubtargetInfo &STI) const;
 };
 } // end anonymous namespace
 
 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
                                               const MCRegisterInfo &MRI,
                                               MCContext &Ctx) {
   return new RISCVMCCodeEmitter(Ctx, MCII);
 }
if (EnableRelax && RelaxCandidate) {
     MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
                     MI.getLoc()));
     ++MCNumFixups;
   }
 
   return 0;
 }
 
+unsigned RISCVMCCodeEmitter::getVPRMaskOp(const MCInst &MI, unsigned OpNo,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  MCOperand MO = MI.getOperand(OpNo);
+  assert(MO.isReg() && "Expected a register");
+
+  switch (MO.getReg()) {
+  default:
+    llvm_unreachable("Invalid mask register");
+  case RISCV::V0:
+    return 0;
+  case RISCV::NoRegister:
+    return 1;
+  }
+}
+
 #include "RISCVGenMCCodeEmitter.inc"

llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
   let Inst{19-15} = rs1;
   let Inst{14-12} = 0b111;
   let Inst{11-7} = rd;
   let Opcode = OPC_OP_V.Value;
 
   let TSFlags{5} = InstVectorNoMask.Value;
 }
 
-class RVInstVV<bits<6> funct6, RISCVVFormat opv, bit vm, dag outs, dag ins,
+class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> vs1;
   bits<5> vd;
+  bits<1> vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = vs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstVX<bits<6> funct6, RISCVVFormat opv, bit vm, dag outs, dag ins,
+class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                 string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vd;
+  bits<1> vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, bit vm, dag outs, dag ins,
+class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
                 string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vd;
+  bits<1> vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstIVI<bits<6> funct6, bit vm, dag outs, dag ins, string opcodestr,
+class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> imm;
   bits<5> vd;
+  bits<1> vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = imm;
   let Inst{14-12} = 0b011;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, bit vm, dag outs,
+class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
               dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> vd;
+  bits<1> vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = vs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstVLU<bits<3> nf, RISCVMOP mop, bit vm, RISCVLSUMOP lumop,
+class RVInstVLU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP lumop,
                 RISCVWidth width, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vd;
+  bits<1> vm;
 
   let Inst{31-29} = nf;
   let Inst{28-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = lumop.Value;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstVLS<bits<3> nf, RISCVMOP mop, bit vm, RISCVWidth width,
+class RVInstVLS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> vd;
+  bits<1> vm;
 
   let Inst{31-29} = nf;
   let Inst{28-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstVLX<bits<3> nf, RISCVMOP mop, bit vm, RISCVWidth width,
+class RVInstVLX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vd;
+  bits<1> vm;
 
   let Inst{31-29} = nf;
   let Inst{28-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstVSU<bits<3> nf, RISCVMOP mop, bit vm, RISCVLSUMOP sumop,
+class RVInstVSU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP sumop,
                 RISCVWidth width, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vs3;
+  bits<1> vm;
 
   let Inst{31-29} = nf;
   let Inst{28-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = sumop.Value;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width.Value;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstVSS<bits<3> nf, RISCVMOP mop, bit vm, RISCVWidth width,
+class RVInstVSS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> vs3;
+  bits<1> vm;
 
   let Inst{31-29} = nf;
   let Inst{28-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width.Value;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }
 
-class RVInstVSX<bits<3> nf, RISCVMOP mop, bit vm, RISCVWidth width,
+class RVInstVSX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vs3;
+  bits<1> vm;
 
   let Inst{31-29} = nf;
   let Inst{28-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width.Value;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
 
   let TSFlags{5} = InstVectorWithMask.Value;
 }

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

def VPRRegOp: RegisterOperand<VPR> {
   let PrintMethod = "printOperand";
 }
 
 def VPRMaskAsmOperand : AsmOperandClass {
   let Name = "RVVMaskRegOpOperand";
   let RenderMethod = "addRegOperands";
   let PredicateMethod = "isReg";
   let ParserMethod = "parseMaskRegister";
+  let IsOptional = 1;
+  let DefaultMethod = "defaultRVVMask";
 }
 
 def VPRMaskRegOp: RegisterOperand<VPRV0> {
   let ParserMatchClass = VPRMaskAsmOperand;
   let PrintMethod = "printVPRMaskOp";
+  let EncoderMethod = "getVPRMaskOp";
 }
 
 def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<5>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<5>";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isInt<5>(Imm);
     return MCOp.isBareSymbolRef();
   }];
 }
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
-// load vd, (rs1) (without mask)
-class VUnitStrideLoad<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
-                      string opcodestr>
-    : RVInstVLU<0b000, mop, 1, lumop, width, (outs VPRRegOp:$vd),
-                (ins GPR:$rs1), opcodestr, "$vd, (${rs1})">;
-
 // load vd, (rs1), vm (with mask)
 class VUnitStrideLoad_t<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
                         string opcodestr>
-    : RVInstVLU<0b000, mop, 0, lumop, width, (outs VPRRegOp:$vd),
-                (ins GPR:$rs1, VPRMaskRegOp:$vm), opcodestr, "$vd, (${rs1}), $vm">;
-
-// load vd, (rs1), rs2 (without mask)
-class VStridedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVLS<0b000, mop, 1, width, (outs VPRRegOp:$vd),
-                (ins GPR:$rs1, GPR:$rs2), opcodestr, "$vd, (${rs1}), $rs2">;
+    : RVInstVLU<0b000, mop, lumop, width, (outs VPRRegOp:$vd),
+                (ins GPR:$rs1, VPRMaskRegOp:$vm), opcodestr, "$vd, (${rs1})${vm}">;
 
 // load vd, (rs1), rs2, vm (with mask)
 class VStridedLoad_t<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVLS<0b000, mop, 0, width, (outs VPRRegOp:$vd),
+    : RVInstVLS<0b000, mop, width, (outs VPRRegOp:$vd),
                 (ins GPR:$rs1, GPR:$rs2, VPRMaskRegOp:$vm), opcodestr,
-                "$vd, (${rs1}), $rs2, $vm">;
-
-// load vd, (rs1), vs2 (without mask)
-class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVLX<0b000, mop, 1, width, (outs VPRRegOp:$vd),
-                (ins GPR:$rs1, VPRRegOp:$vs2), opcodestr,
-                "$vd, (${rs1}), $vs2">;
+                "$vd, (${rs1}), $rs2${vm}">;
 
 // load vd, (rs1), vs2, vm (with mask)
 class VIndexedLoad_t<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVLX<0b000, mop, 0, width, (outs VPRRegOp:$vd),
+    : RVInstVLX<0b000, mop, width, (outs VPRRegOp:$vd),
                 (ins GPR:$rs1, VPRRegOp:$vs2, VPRMaskRegOp:$vm), opcodestr,
-                "$vd, (${rs1}), $vs2, $vm">;
+                "$vd, (${rs1}), $vs2${vm}">;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
-// store vd, vs3, (rs1) (without mask)
-class VUnitStrideStore<RISCVMOP mop, RISCVLSUMOP sumop, RISCVWidth width,
-                       string opcodestr>
-    : RVInstVSU<0b000, mop, 1, sumop, width, (outs),
-                (ins VPRRegOp:$vs3, GPR:$rs1), opcodestr, "$vs3, (${rs1})">;
-
 // store vd, vs3, (rs1), vm (with mask)
 class VUnitStrideStore_t<RISCVMOP mop, RISCVLSUMOP sumop, RISCVWidth width,
                          string opcodestr>
-    : RVInstVSU<0b000, mop, 0, sumop, width, (outs),
+    : RVInstVSU<0b000, mop, sumop, width, (outs),
                 (ins VPRRegOp:$vs3, GPR:$rs1, VPRMaskRegOp:$vm), opcodestr,
-                "$vs3, (${rs1}), $vm">;
-
-// store vd, vs3, (rs1), rs2 (without mask)
-class VStridedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVSS<0b000, mop, 1, width, (outs),
-                (ins VPRRegOp:$vs3, GPR:$rs1, GPR:$rs2), opcodestr,
-                "$vs3, (${rs1}), $rs2">;
+                "$vs3, (${rs1})${vm}">;
 
 // store vd, vs3, (rs1), rs2, vm (with mask)
 class VStridedStore_t<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVSS<0b000, mop, 0, width, (outs),
+    : RVInstVSS<0b000, mop, width, (outs),
                 (ins VPRRegOp:$vs3, GPR:$rs1, GPR:$rs2, VPRMaskRegOp:$vm),
-                opcodestr, "$vs3, (${rs1}), $rs2, $vm">;
-
-// store vd, vs3, (rs1), vs2 (without mask)
-class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVSX<0b000, mop, 1, width, (outs),
-                (ins VPRRegOp:$vs3, GPR:$rs1, VPRRegOp:$vs2), opcodestr,
-                "$vs3, (${rs1}), $vs2">;
+                opcodestr, "$vs3, (${rs1}), $rs2${vm}">;
 
 // store vd, vs3, (rs1), vs2, vm (with mask)
 class VIndexedStore_t<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVSX<0b000, mop, 0, width, (outs),
+    : RVInstVSX<0b000, mop, width, (outs),
                 (ins VPRRegOp:$vs3, GPR:$rs1, VPRRegOp:$vs2, VPRMaskRegOp:$vm),
-                opcodestr, "$vs3, (${rs1}), $vs2, $vm">;
+                opcodestr, "$vs3, (${rs1}), $vs2${vm}">;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // op vd, vs2, vs1 (without mask)
+let vm = 1 in
 class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVV<funct6, opv, 1, (outs VPRRegOp:$vd),
+    : RVInstVV<funct6, opv, (outs VPRRegOp:$vd),
                (ins VPRRegOp:$vs2, VPRRegOp:$vs1),
                opcodestr, "$vd, $vs2, $vs1">;
 
 // op vd, vs2, vs1, vm (with mask)
 class VALUVV_t<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVV<funct6, opv, 0, (outs VPRRegOp:$vd),
+    : RVInstVV<funct6, opv, (outs VPRRegOp:$vd),
                 (ins VPRRegOp:$vs2, VPRRegOp:$vs1, VPRMaskRegOp:$vm),
-                opcodestr, "$vd, $vs2, $vs1, $vm">;
+                opcodestr, "$vd, $vs2, $vs1${vm}">;
 
 // op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
+let vm = 1 in
 class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVV<funct6, opv, 1, (outs VPRRegOp:$vd),
+    : RVInstVV<funct6, opv, (outs VPRRegOp:$vd),
                 (ins VPRRegOp:$vs2, VPRRegOp:$vs1, VPRV0:$v0),
                 opcodestr, "$vd, $vs2, $vs1, v0">;
 
-// op vd, vs1, vs2 (without mask, reverse the order of vs1 and vs2)
-class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVV<funct6, opv, 1, (outs VPRRegOp:$vd),
-               (ins VPRRegOp:$vs1, VPRRegOp:$vs2),
-               opcodestr, "$vd, $vs1, $vs2">;
-
 // op vd, vs1, vs2, vm (with mask, reverse the order of vs1 and vs2)
 class VALUrVV_t<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVV<funct6, opv, 0, (outs VPRRegOp:$vd),
+    : RVInstVV<funct6, opv, (outs VPRRegOp:$vd),
                 (ins VPRRegOp:$vs1, VPRRegOp:$vs2, VPRMaskRegOp:$vm),
-                opcodestr, "$vd, $vs1, $vs2, $vm">;
-
-// op vd, vs2, rs1 (without mask)
-class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 1, (outs VPRRegOp:$vd),
-                (ins VPRRegOp:$vs2, GPR:$rs1),
-                opcodestr, "$vd, $vs2, $rs1">;
+                opcodestr, "$vd, $vs1, $vs2${vm}">;
 
 // op vd, vs2, rs1, vm (with mask)
 class VALUVX_t<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 0, (outs VPRRegOp:$vd),
+    : RVInstVX<funct6, opv, (outs VPRRegOp:$vd),
                 (ins VPRRegOp:$vs2, GPR:$rs1, VPRMaskRegOp:$vm),
-                opcodestr, "$vd, $vs2, $rs1, $vm">;
+                opcodestr, "$vd, $vs2, $rs1${vm}">;
 
 // op vd, vs2, rs1, v0 (without mask, use v0 as carry input)
+let vm = 1 in
 class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 1, (outs VPRRegOp:$vd),
+    : RVInstVX<funct6, opv, (outs VPRRegOp:$vd),
                 (ins VPRRegOp:$vs2, GPR:$rs1, VPRV0:$v0),
                 opcodestr, "$vd, $vs2, $rs1, v0">;
 
-// op vd, rs1, vs2 (without mask, reverse the order of rs1 and vs2)
-class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 1, (outs VPRRegOp:$vd),
-                (ins GPR:$rs1, VPRRegOp:$vs2),
-                opcodestr, "$vd, $rs1, $vs2">;
-
 // op vd, rs1, vs2, vm (with mask, reverse the order of rs1 and vs2)
 class VALUrVX_t<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 0, (outs VPRRegOp:$vd),
+    : RVInstVX<funct6, opv, (outs VPRRegOp:$vd),
                 (ins GPR:$rs1, VPRRegOp:$vs2, VPRMaskRegOp:$vm),
-                opcodestr, "$vd, $rs1, $vs2, $vm">;
-
-// op vd, vs2, imm (without mask)
-class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
-    : RVInstIVI<funct6, 1, (outs VPRRegOp:$vd),
-                (ins VPRRegOp:$vs2, optype:$imm),
-                opcodestr, "$vd, $vs2, $imm">;
+                opcodestr, "$vd, $rs1, $vs2${vm}">;
 
 // op vd, vs2, imm, vm (with mask)
 class VALUVI_t<bits<6> funct6, string opcodestr, Operand optype = simm5>
-    : RVInstIVI<funct6, 0, (outs VPRRegOp:$vd),
+    : RVInstIVI<funct6, (outs VPRRegOp:$vd),
                 (ins VPRRegOp:$vs2, optype:$imm, VPRMaskRegOp:$vm),
-                opcodestr, "$vd, $vs2, $imm, $vm">;
+                opcodestr, "$vd, $vs2, $imm${vm}">;
 
 // op vd, vs2, imm, v0 (without mask, use v0 as carry input)
 class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
-    : RVInstIVI<funct6, 1, (outs VPRRegOp:$vd),
+    : RVInstIVI<funct6, (outs VPRRegOp:$vd),
                 (ins VPRRegOp:$vs2, optype:$imm, VPRV0:$v0),
                 opcodestr, "$vd, $vs2, $imm, v0">;
 
-// op vd, vs2, rs1 (Float) (without mask)
-class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 1, (outs VPRRegOp:$vd),
-                (ins VPRRegOp:$vs2, FPR32:$rs1),
-                opcodestr, "$vd, $vs2, $rs1">;
-
 // op vd, vs2, rs1, vm (Float) (with mask)
 class VALUVF_t<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 0, (outs VPRRegOp:$vd),
+    : RVInstVX<funct6, opv, (outs VPRRegOp:$vd),
                 (ins VPRRegOp:$vs2, FPR32:$rs1, VPRMaskRegOp:$vm),
-                opcodestr, "$vd, $vs2, $rs1, $vm">;
-
-// op vd, rs1, vs2 (Float) (without mask, reverse the order of rs1 and vs2)
-class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 1, (outs VPRRegOp:$vd),
-                (ins FPR32:$rs1, VPRRegOp:$vs2),
-                opcodestr, "$vd, $rs1, $vs2">;
+                opcodestr, "$vd, $vs2, $rs1${vm}">;
 
 // op vd, rs1, vs2 (Float) (with mask, reverse the order of rs1 and vs2)
 class VALUrVF_t<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : RVInstVX<funct6, opv, 0, (outs VPRRegOp:$vd),
+    : RVInstVX<funct6, opv, (outs VPRRegOp:$vd),
                 (ins FPR32:$rs1, VPRRegOp:$vs2, VPRMaskRegOp:$vm),
-                opcodestr, "$vd, $rs1, $vs2, $vm">;
-
-// op vd, vs2 (without mask, use vs1 as instruction encoding)
-class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
-    : RVInstV<funct6, vs1, opv, 1, (outs VPRRegOp:$vd),
-               (ins VPRRegOp:$vs2),
-               opcodestr, "$vd, $vs2">;
+                opcodestr, "$vd, $rs1, $vs2${vm}">;
 
 // op vd, vs2, vm (with mask, use vs1 as instruction encoding)
 class VALUVs2_t<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
-    : RVInstV<funct6, vs1, opv, 0, (outs VPRRegOp:$vd),
+    : RVInstV<funct6, vs1, opv, (outs VPRRegOp:$vd),
                (ins VPRRegOp:$vs2, VPRMaskRegOp:$vm),
-               opcodestr, "$vd, $vs2, $vm">;
+               opcodestr, "$vd, $vs2${vm}">;
 }
 
 //===----------------------------------------------------------------------===//
 // Combination of instruction classes.
 // Use these multiclasses to define instructions more easily.
 //===----------------------------------------------------------------------===//
 
 multiclass VALUVV_Mask<bits<6> funct6, RISCVVFormat opv, string opcodestr> {
-  def "": VALUVV<funct6, opv, opcodestr>;
-  def _T : VALUVV_t<funct6, opv, opcodestr>;
+  def "" : VALUVV_t<funct6, opv, opcodestr>;
 }
 
 multiclass VALUrVV_Mask<bits<6> funct6, RISCVVFormat opv, string opcodestr> {
-  def "": VALUrVV<funct6, opv, opcodestr>;
-  def _T : VALUrVV_t<funct6, opv, opcodestr>;
+  def "" : VALUrVV_t<funct6, opv, opcodestr>;
 }
 
 multiclass VALUVX_Mask<bits<6> funct6, RISCVVFormat opv, string opcodestr> {
-  def "": VALUVX<funct6, opv, opcodestr>;
-  def _T : VALUVX_t<funct6, opv, opcodestr>;
+  def "" : VALUVX_t<funct6, opv, opcodestr>;
 }
 
 multiclass VALUrVX_Mask<bits<6> funct6, RISCVVFormat opv, string opcodestr> {
-  def "": VALUrVX<funct6, opv, opcodestr>;
-  def _T : VALUrVX_t<funct6, opv, opcodestr>;
+  def "" : VALUrVX_t<funct6, opv, opcodestr>;
 }
 
 multiclass VALUVI_Mask<bits<6> funct6, string opcodestr, Operand optype = simm5> {
-  def "": VALUVI<funct6, opcodestr, optype>;
-  def _T : VALUVI_t<funct6, opcodestr, optype>;
+  def "" : VALUVI_t<funct6, opcodestr, optype>;
 }
 
 multiclass VALUVF_Mask<bits<6> funct6, RISCVVFormat opv, string opcodestr> {
-  def "": VALUVF<funct6, opv, opcodestr>;
-  def _T : VALUVF_t<funct6, opv, opcodestr>;
+  def "" : VALUVF_t<funct6, opv, opcodestr>;
 }
 
 multiclass VALUrVF_Mask<bits<6> funct6, RISCVVFormat opv, string opcodestr> {
-  def "": VALUrVF<funct6, opv, opcodestr>;
-  def _T : VALUrVF_t<funct6, opv, opcodestr>;
+  def "" : VALUrVF_t<funct6, opv, opcodestr>;
 }
 
 multiclass VALUVs2_Mask<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> {
-  def "": VALUVs2<funct6, vs1, opv, opcodestr>;
-  def _T : VALUVs2_t<funct6, vs1, opv, opcodestr>;
+  def "" : VALUVs2_t<funct6, vs1, opv, opcodestr>;
 }
 
 multiclass VUnitStrideLoadMask<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
                                string opcodestr> {
-  def "": VUnitStrideLoad<mop, lumop, width, opcodestr>;
-  def _T : VUnitStrideLoad_t<mop, lumop, width, opcodestr>;
+  def "" : VUnitStrideLoad_t<mop, lumop, width, opcodestr>;
 }
 
 multiclass VStridedLoadMask<RISCVMOP mop, RISCVWidth width, string opcodestr> {
-  def "": VStridedLoad<mop, width, opcodestr>;
-  def _T : VStridedLoad_t<mop, width, opcodestr>;
+  def "" : VStridedLoad_t<mop, width, opcodestr>;
 }
 
 multiclass VIndexedLoadMask<RISCVMOP mop, RISCVWidth width, string opcodestr> {
-  def "": VIndexedLoad<mop, width, opcodestr>;
-  def _T : VIndexedLoad_t<mop, width, opcodestr>;
+  def "" : VIndexedLoad_t<mop, width, opcodestr>;
 }
 
 multiclass VUnitStrideStoreMask<RISCVMOP mop, RISCVLSUMOP sumop, RISCVWidth width,
                                 string opcodestr> {
-  def "": VUnitStrideStore<mop, sumop, width, opcodestr>;
-  def _T : VUnitStrideStore_t<mop, sumop, width, opcodestr>;
+  def "" : VUnitStrideStore_t<mop, sumop, width, opcodestr>;
 }
 
 multiclass VStridedStoreMask<RISCVMOP mop, RISCVWidth width, string opcodestr> {
-  def "": VStridedStore<mop, width, opcodestr>;
-  def _T : VStridedStore_t<mop, width, opcodestr>;
+  def "" : VStridedStore_t<mop, width, opcodestr>;
 }
 
 multiclass VIndexedStoreMask<RISCVMOP mop, RISCVWidth width, string opcodestr> {
-  def "": VIndexedStore<mop, width, opcodestr>;
-  def _T : VIndexedStore_t<mop, width, opcodestr>;
+  def "" : VIndexedStore_t<mop, width, opcodestr>;
 }
 
 multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
   defm V  : VALUVV_Mask<funct6, OPIVV, opcodestr # "." # vw # "v">;
   defm X  : VALUVX_Mask<funct6, OPIVX, opcodestr # "." # vw # "x">;
   defm I  : VALUVI_Mask<funct6, opcodestr # "." # vw # "i", optype>;
 }
 

 }
 
 // Vector Integer Merge Instructions
 defm VMERGE : VALU_IV_V_X_I_t<"vmerge", 0b010111>;
 
 // Vector Integer Move Instructions
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // op vd, vs1
-def VMV_V_V : RVInstVV<0b010111, OPIVV, 1, (outs VPRRegOp:$vd),
+def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VPRRegOp:$vd),
                        (ins VPRRegOp:$vs1), "vmv.v.v", "$vd, $vs1"> {
+  let vm = 1;
   let vs2 = 0;
 }
 // op vd, rs1
-def VMV_V_X : RVInstVX<0b010111, OPIVX, 1, (outs VPRRegOp:$vd),
+def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VPRRegOp:$vd),
                        (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1"> {
+  let vm = 1;
   let vs2 = 0;
 }
 // op vd, imm
-def VMV_V_I : RVInstIVI<0b010111, 1, (outs VPRRegOp:$vd),
+def VMV_V_I : RVInstIVI<0b010111, (outs VPRRegOp:$vd),
                        (ins simm5:$imm), "vmv.v.i", "$vd, $imm"> {
+  let vm = 1;
   let vs2 = 0;
 }
 }
 
 // Vector Fixed-Point Arithmetic Instructions
 defm VSADDU_V : VALU_IV_V_X_I<"vsaddu", 0b100000>;
 defm VSADD_V : VALU_IV_V_X_I<"vsadd", 0b100001>;
 defm VSSUBU_V : VALU_IV_V_X<"vssubu", 0b100010>;

 defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>;
 defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>;
 
 // Vector Floating-Point Classify Instruction
 defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // Vector Floating-Point Merge Instruction
-def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, 0, (outs VPRRegOp:$vd),
+def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VPRRegOp:$vd),
                            (ins VPRRegOp:$vs2, FPR32:$rs1, VPRV0:$v0),
-                           "vfmerge.vfm", "$vd, $vs2, $rs1, v0">;
+                           "vfmerge.vfm", "$vd, $vs2, $rs1, v0">
+{
+  let vm = 0;
+}
 
 // Vector Floating-Point Move Instruction
-def VFMV_V_F : RVInstVX<0b010111, OPFVF, 1, (outs VPRRegOp:$vd),
+def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VPRRegOp:$vd),
                        (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> {
+  let vm = 1;
   let vs2 = 0;
 }
 }
 
 // Single-Width Floating-Point/Integer Type-Convert Instructions
 defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
 defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
 defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;

 defm VMXOR_M : VALU_MV_M<"vmxor", 0b011011, "m">;
 defm VMOR_M : VALU_MV_M<"vmor", 0b011010, "m">;
 defm VMNOR_M : VALU_MV_M<"vmnor", 0b011110, "m">;
 defm VMORNOT_M : VALU_MV_M<"vmornot", 0b011100, "m">;
 defm VMXNOR_M : VALU_MV_M<"vmxnor", 0b011111, "m">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // Vector mask population count vpopc
-def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, 1, (outs GPR:$vd),
-                      (ins VPRRegOp:$vs2), "vpopc.m", "$vd, $vs2">;
-def VPOPC_M_T : RVInstV<0b010000, 0b10000, OPMVV, 0, (outs GPR:$vd),
+def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
                         (ins VPRRegOp:$vs2, VPRMaskRegOp:$vm),
-                        "vpopc.m", "$vd, $vs2, $vm">;
+                        "vpopc.m", "$vd, $vs2${vm}">;
 
 // vfirst find-first-set mask bit
-def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, 1, (outs GPR:$vd),
-                      (ins VPRRegOp:$vs2), "vfirst.m", "$vd, $vs2">;
-def VFIRST_M_T : RVInstV<0b010000, 0b10001, OPMVV, 0, (outs GPR:$vd),
+def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
                         (ins VPRRegOp:$vs2, VPRMaskRegOp:$vm),
-                        "vfirst.m", "$vd, $vs2, $vm">;
+                        "vfirst.m", "$vd, $vs2${vm}">;
 }
 
 // vmsbf.m set-before-first mask bit
 defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>;
 
 // vmsif.m set-including-first mask bit
 defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>;
 
 // vmsof.m set-only-first mask bit
 defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>;
 
 // Vector Iota Instruction
 let Constraints = "@earlyclobber $vd" in {
 defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>;
 }
 
 // Vector Element Index Instruction
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-def VID_V : RVInstV<0b010100, 0b10001, OPMVV, 1, (outs VPRRegOp:$vd),
-                    (ins), "vid.v", "$vd"> {
-  let vs2 = 0;
-}
 
-def VID_V_T : RVInstV<0b010100, 0b10001, OPMVV, 0, (outs VPRRegOp:$vd),
-                      (ins VPRMaskRegOp:$vm), "vid.v", "$vd, $vm"> {
+def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VPRRegOp:$vd),
+                      (ins VPRMaskRegOp:$vm), "vid.v", "$vd${vm}"> {
   let vs2 = 0;
 }
 
 // Integer Scalar Move Instructions
-def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, 1, (outs GPR:$vd),
-                      (ins VPRRegOp:$vs2), "vmv.x.s", "$vd, $vs2">;
-def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, 1, (outs VPRRegOp:$vd),
-                      (ins GPR:$rs1), "vmv.s.x", "$vd, $rs1">;
+def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
+                      (ins VPRRegOp:$vs2), "vmv.x.s", "$vd, $vs2">
+{
+  let vm = 1;
+}
+def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VPRRegOp:$vd),
+                      (ins GPR:$rs1), "vmv.s.x", "$vd, $rs1">
+{
+  let vm = 1;
+}
 
 // Floating-Point Scalar Move Instructions
-def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, 1, (outs FPR32:$vd),
-                      (ins VPRRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
-def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, 1, (outs VPRRegOp:$vd),
-                      (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">;
+def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
+                      (ins VPRRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">
+{
+  let vm = 1;
+}
+def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VPRRegOp:$vd),
+                      (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">
+{
+  let vm = 1;
+}
 }
 
 // Vector Slide Instructions
 let Constraints = "@earlyclobber $vd" in {
 defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
 }
 defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;