[MIPS GlobalISel] Select MSA insert_vector_elt with immediate index

[Petar.Avramovic]

Summary

Select G_INSERT_VECTOR_ELT when insert index is defined with G_CONSTANT,
and can be folded like an immediate, for MIPS32 with MSA.

[atanasyan]

When I apply this match to the master branch I get a couple of failed tests:

• CodeGen/Mips/GlobalISel/legalizer/insert_vector_elt_imm_index.mir
• CodeGen/Mips/GlobalISel/llvm-ir/insert_vector_elt_imm_index.ll

LLVM ERROR: unable to legalize instruction: %8:_(<16 x s32>) = G_INSERT_VECTOR_ELT %6:_, %7:_(s32), %5:_(s32) (in function: insert_i8)

Are there any other patches need to be applied first?

[Petar.Avramovic]

D69513 goes first, following what SDAG does
%8:_(<16 x s8>) = G_INSERT_VECTOR_ELT %6:_, %7:_(s8), %5:_(s32)
should change only insert elt scalar type, and leave vector scalar type as is
%8:_(<16 x s8>) = G_INSERT_VECTOR_ELT %6:_, %7:_(s32), %5:_(s32) (in function: insert_i8)
insert instruction is selected based on vector type, inserted scalar is always i32 (i32 or i64 for mips64)

[atanasyan]

LGTM

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

private:
   bool isRegInFprb(Register Reg, MachineRegisterInfo &MRI) const;
   bool materialize32BitImm(Register DestReg, APInt Imm,
                            MachineIRBuilder &B) const;
   bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
   const TargetRegisterClass *
   getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
   unsigned selectLoadStoreOpCode(MachineInstr &I,
                                  MachineRegisterInfo &MRI) const;
+  bool selectInsertVectorEltImmIndex(MachineInstr &I,
+                                     MachineRegisterInfo &MRI) const;
 
   const MipsTargetMachine &TM;
   const MipsSubtarget &STI;
   const MipsInstrInfo &TII;
   const MipsRegisterInfo &TRI;
   const MipsRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL
if (Ty.isVector()) {
         return Opc;
       }
     }
   }
 
   return Opc;
 }
 
+bool MipsInstructionSelector::selectInsertVectorEltImmIndex(
+    MachineInstr &I, MachineRegisterInfo &MRI) const {
+  MachineBasicBlock &MBB = *I.getParent();
+  Register Dst = I.getOperand(0).getReg();
+  Register Src = I.getOperand(1).getReg();
+  Register Elt = I.getOperand(2).getReg();
+  unsigned VectorElSize = MRI.getType(Src).getScalarSizeInBits();
+  unsigned Opcode;
+
+  Register IdxReg = I.getOperand(3).getReg();
+  MachineInstr *IdxI = MRI.getVRegDef(IdxReg);
+  APInt Idx = IdxI->getOperand(1).getCImm()->getValue();
+  if (isRegInGprb(Elt, MRI)) {
+    switch (VectorElSize) {
+    case 8:
+      Opcode = Mips::INSERT_B;
+      break;
+    case 16:
+      Opcode = Mips::INSERT_H;
+      break;
+    case 32:
+      Opcode = Mips::INSERT_W;
+      break;
+    default:
+      return false;
+    }
+    MachineInstr *MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
+                           .addDef(Dst)
+                           .addUse(Src)
+                           .addUse(Elt)
+                           .addImm(Idx.getLimitedValue());
+    I.eraseFromParent();
+    return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  }
+
+  if (isRegInFprb(Elt, MRI)) {
+    switch (VectorElSize) {
+    case 32:
+      Opcode = Mips::INSERT_FW_PSEUDO;
+      break;
+    case 64:
+      Opcode = Mips::INSERT_FD_PSEUDO;
+      break;
+    default:
+      return false;
+    }
+    MachineInstr *MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
+                           .addDef(Dst)
+                           .addUse(Src)
+                           .addImm(Idx.getLimitedValue())
+                           .addUse(Elt);
+    I.eraseFromParent();
+    return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  }
+
+  return false;
+}
+
 bool MipsInstructionSelector::select(MachineInstr &I) {
 
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   if (!isPreISelGenericOpcode(I.getOpcode())) {
     if (I.isCopy())
case G_SEXTLOAD: {
 
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
              .add(I.getOperand(0))
              .add(BaseAddr)
              .addImm(SignedOffset)
              .addMemOperand(*I.memoperands_begin());
     break;
   }
+  case G_INSERT_VECTOR_ELT: {
+    assert(STI.hasMSA() && "Vector instructions require target with MSA.");
+    Register IdxReg = I.getOperand(3).getReg();
+    MachineInstr *IdxI = MRI.getVRegDef(IdxReg);
+
+    if (IdxI->getOpcode() == G_CONSTANT)
+      return selectInsertVectorEltImmIndex(I, MRI);
+
+    return false;
+  }
   case G_UDIV:
   case G_UREM:
   case G_SDIV:
   case G_SREM: {
     Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
     bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV;
     bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV;
 

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

getActionDefinitionsBuilder({G_LOAD, G_STORE})
           return true;
         return false;
       })
       .minScalar(0, s32);
 
   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
       .legalFor({s32, s64});
 
+  getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
+      .legalIf([=, &ST](const LegalityQuery &Query) {
+        if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}) &&
+            CheckTyN(1, Query, {s32, s64}) && CheckTyN(2, Query, {s32}))
+          return true;
+        return false;
+      })
+      .minScalar(1, s32);
+
   getActionDefinitionsBuilder(G_UNMERGE_VALUES)
      .legalFor({{s32, s64}});
 
   getActionDefinitionsBuilder(G_MERGE_VALUES)
      .legalFor({{s64, s32}});
 
   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
       .legalForTypesWithMemDesc({{s32, p0, 8, 8},

llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

 
 static bool isAmbiguous(unsigned Opc) {
   switch (Opc) {
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
   case TargetOpcode::G_PHI:
   case TargetOpcode::G_SELECT:
   case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_INSERT_VECTOR_ELT:
     return true;
   default:
     return false;
   }
 }
 
 void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
     Register Reg, const MachineRegisterInfo &MRI) {
MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
 
   const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
 
   if (MI->getOpcode() == TargetOpcode::G_LOAD)
     addDefUses(MI->getOperand(0).getReg(), MRI);
 
   if (MI->getOpcode() == TargetOpcode::G_STORE)
     addUseDef(MI->getOperand(0).getReg(), MRI);
+  if (MI->getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT)
+    addUseDef(MI->getOperand(2).getReg(), MRI);
 
   if (MI->getOpcode() == TargetOpcode::G_PHI) {
     addDefUses(MI->getOperand(0).getReg(), MRI);
 
     for (unsigned i = 1; i < MI->getNumOperands(); i += 2)
       addUseDef(MI->getOperand(i).getReg(), MRI);
   }
 
if (!Op0Ty.isPointer())
       InstTy = TI.determineInstType(&MI);
 
     if (InstTy == InstType::FloatingPoint)
       OperandsMapping = getFprbMapping(Op0Size);
     else
       OperandsMapping = getGprbOrCustomMapping(Op0Size, MappingID);
 
     break;
+  case G_INSERT_VECTOR_ELT: {
+    const LLT Op2Ty = MRI.getType(MI.getOperand(2).getReg());
+    unsigned Op2Size = Op2Ty.getSizeInBits();
+
+    if (!Op2Ty.isPointer())
+      InstTy = TI.determineInstType(&MI);
+
+    const RegisterBankInfo::ValueMapping *MSABank = getMSAMapping(MF);
+    if (InstTy == InstType::FloatingPoint ||
+        (Op2Size == 64 && InstTy == InstType::Ambiguous))
+      OperandsMapping =
+          getOperandsMapping({MSABank, MSABank, getFprbMapping(Op2Size),
+                              &Mips::ValueMappings[Mips::GPRIdx]});
+    else
+      // Ambiguous 32 bit vector insert will be mapped to gprb to match the
+      // way other ambiguous 32 bit operands are mapped.
+      OperandsMapping = getOperandsMapping(
+          {MSABank, MSABank, getGprbOrCustomMapping(Op2Size, MappingID),
+           &Mips::ValueMappings[Mips::GPRIdx]});
+
+    break;
+  }
   case G_UNMERGE_VALUES:
     OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
                                           &Mips::ValueMappings[Mips::GPRIdx],
                                           &Mips::ValueMappings[Mips::DPRIdx]});
     MappingID = CustomMappingID;
     break;
   case G_MERGE_VALUES:
     OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx],

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/insert_vector_elt_imm_index.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @insert_i8(i8 %val, <16 x i8>* %V) { entry: ret void }
+  define void @insert_i16(i16 %val, <8 x i16>* %V) { entry: ret void }
+  define void @insert_i32(i32 %val, <4 x i32>* %V) { entry: ret void }
+  define void @insert_float_fprb(float %val, <4 x float>* %V) { entry: ret void }
+  define void @insert_double(double %val, <2 x double>* %V) { entry: ret void }
+
+...
+---
+name:            insert_i8
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i8
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_B:%[0-9]+]]:msa128b = INSERT_B [[LD_B]], [[COPY]], 7
+    ; P5600: ST_B [[INSERT_B]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %2:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %5:gprb(s32) = G_CONSTANT i32 7
+    %3:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %6:gprb(s32) = COPY %2(s32)
+    %4:fprb(<16 x s8>) = G_INSERT_VECTOR_ELT %3, %6(s32), %5(s32)
+    G_STORE %4(<16 x s8>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i16
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i16
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_H:%[0-9]+]]:msa128h = INSERT_H [[LD_H]], [[COPY]], 5
+    ; P5600: ST_H [[INSERT_H]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %2:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %5:gprb(s32) = G_CONSTANT i32 5
+    %3:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %6:gprb(s32) = COPY %2(s32)
+    %4:fprb(<8 x s16>) = G_INSERT_VECTOR_ELT %3, %6(s32), %5(s32)
+    G_STORE %4(<8 x s16>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i32
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_W:%[0-9]+]]:msa128w = INSERT_W [[LD_W]], [[COPY]], 2
+    ; P5600: ST_W [[INSERT_W]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_CONSTANT i32 2
+    %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %4(s32)
+    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_float_fprb
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a1, $f12
+
+    ; P5600-LABEL: name: insert_float_fprb
+    ; P5600: liveins: $a1, $f12
+    ; P5600: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128w = INSERT_FW_PSEUDO [[LD_W]], 3, [[COPY]]
+    ; P5600: ST_W [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:fprb(s32) = COPY $f12
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_CONSTANT i32 3
+    %2:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %4(s32)
+    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_double
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a2, $d12_64
+
+    ; P5600-LABEL: name: insert_double
+    ; P5600: liveins: $a2, $d12_64
+    ; P5600: [[COPY:%[0-9]+]]:fgr64 = COPY $d12_64
+    ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
+    ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.V)
+    ; P5600: [[INSERT_:%[0-9]+]]:msa128d = INSERT_FD_PSEUDO [[LD_D]], 1, [[COPY]]
+    ; P5600: ST_D [[INSERT_]], [[COPY1]], 0 :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:fprb(s64) = COPY $d12_64
+    %1:gprb(p0) = COPY $a2
+    %4:gprb(s32) = G_CONSTANT i32 1
+    %2:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:fprb(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %4(s32)
+    G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/insert_vector_elt_imm_index.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @insert_i8(i8 %val, <16 x i8>* %V) { entry: ret void }
+  define void @insert_i16(i16 %val, <8 x i16>* %V) { entry: ret void }
+  define void @insert_i32(i32 %val, <4 x i32>* %V) { entry: ret void }
+  define void @insert_i64_fprb(i64* %pval, <2 x i64>* %V) { entry: ret void }
+  define void @insert_float_fprb(float %val, <4 x float>* %V) { entry: ret void }
+  define void @insert_float_gprb(float* %pval, <4 x float>* %V) { entry: ret void }
+  define void @insert_double(double %val, <2 x double>* %V) { entry: ret void }
+
+...
+---
+name:            insert_i8
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i8
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; P5600: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY2]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %2:_(s32) = COPY $a0
+    %0:_(s8) = G_TRUNC %2(s32)
+    %1:_(p0) = COPY $a1
+    %5:_(s32) = G_CONSTANT i32 7
+    %3:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:_(<16 x s8>) = G_INSERT_VECTOR_ELT %3, %0(s8), %5(s32)
+    G_STORE %4(<16 x s8>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i16
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i16
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+    ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; P5600: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY2]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %2:_(s32) = COPY $a0
+    %0:_(s16) = G_TRUNC %2(s32)
+    %1:_(p0) = COPY $a1
+    %5:_(s32) = G_CONSTANT i32 5
+    %3:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:_(<8 x s16>) = G_INSERT_VECTOR_ELT %3, %0(s16), %5(s32)
+    G_STORE %4(<8 x s16>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i32
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_CONSTANT i32 2
+    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %4(s32)
+    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i64_fprb
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i64_fprb
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; P5600: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.pval)
+    ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[LOAD1]], [[LOAD]](s64), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %5:_(s32) = G_CONSTANT i32 0
+    %2:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.pval)
+    %3:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:_(<2 x s64>) = G_INSERT_VECTOR_ELT %3, %2(s64), %5(s32)
+    G_STORE %4(<2 x s64>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_float_fprb
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a1, $f12
+
+    ; P5600-LABEL: name: insert_float_fprb
+    ; P5600: liveins: $a1, $f12
+    ; P5600: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+    ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(s32) = COPY $f12
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_CONSTANT i32 3
+    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %4(s32)
+    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_float_gprb
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_float_gprb
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; P5600: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.pval)
+    ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[LOAD1]], [[LOAD]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %5:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.pval)
+    %3:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %3, %2(s32), %5(s32)
+    G_STORE %4(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_double
+alignment:       4
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a2, $d12_64
+
+    ; P5600-LABEL: name: insert_double
+    ; P5600: liveins: $a2, $d12_64
+    ; P5600: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64
+    ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a2
+    ; P5600: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY]](s64), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(s64) = COPY $d12_64
+    %1:_(p0) = COPY $a2
+    %4:_(s32) = G_CONSTANT i32 1
+    %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %4(s32)
+    G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/insert_vector_elt_imm_index.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
+
+define void @insert_i8(i8 %val, <16 x i8>* %V) {
+; P5600-LABEL: insert_i8:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.b $w0, 0($5)
+; P5600-NEXT:    insert.b $w0[7], $4
+; P5600-NEXT:    st.b $w0, 0($5)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <16 x i8>, <16 x i8>* %V, align 16
+  %vecins = insertelement <16 x i8> %0, i8 %val, i32 7
+  store <16 x i8> %vecins, <16 x i8>* %V, align 16
+  ret void
+}
+
+define void @insert_i16(i16 %val, <8 x i16>* %V) {
+; P5600-LABEL: insert_i16:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.h $w0, 0($5)
+; P5600-NEXT:    insert.h $w0[5], $4
+; P5600-NEXT:    st.h $w0, 0($5)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <8 x i16>, <8 x i16>* %V, align 16
+  %vecins = insertelement <8 x i16> %0, i16 %val, i32 5
+  store <8 x i16> %vecins, <8 x i16>* %V, align 16
+  ret void
+}
+
+define void @insert_i32(i32 %val, <4 x i32>* %V) {
+; P5600-LABEL: insert_i32:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.w $w0, 0($5)
+; P5600-NEXT:    insert.w $w0[2], $4
+; P5600-NEXT:    st.w $w0, 0($5)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %V, align 16
+  %vecins = insertelement <4 x i32> %0, i32 %val, i32 2
+  store <4 x i32> %vecins, <4 x i32>* %V, align 16
+  ret void
+}
+
+define void @insert_i64_fprb(i64* %pval, <2 x i64>* %V) {
+; P5600-LABEL: insert_i64_fprb:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ldc1 $f0, 0($4)
+; P5600-NEXT:    ld.d $w1, 0($5)
+; P5600-NEXT:    mov.d $f2, $f0
+; P5600-NEXT:    insve.d $w1[0], $w2[0]
+; P5600-NEXT:    st.d $w1, 0($5)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load i64, i64* %pval, align 8
+  %1 = load <2 x i64>, <2 x i64>* %V, align 16
+  %vecins = insertelement <2 x i64> %1, i64 %0, i32 0
+  store <2 x i64> %vecins, <2 x i64>* %V, align 16
+  ret void
+}
+
+define void @insert_float_fprb(float %val, <4 x float>* %V) {
+; P5600-LABEL: insert_float_fprb:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.w $w0, 0($5)
+; P5600-NEXT:    mov.s $f1, $f12
+; P5600-NEXT:    insve.w $w0[3], $w1[0]
+; P5600-NEXT:    st.w $w0, 0($5)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <4 x float>, <4 x float>* %V, align 16
+  %vecins = insertelement <4 x float> %0, float %val, i32 3
+  store <4 x float> %vecins, <4 x float>* %V, align 16
+  ret void
+}
+
+define void @insert_float_gprb(float* %pval, <4 x float>* %V) {
+; P5600-LABEL: insert_float_gprb:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    lw $1, 0($4)
+; P5600-NEXT:    ld.w $w0, 0($5)
+; P5600-NEXT:    insert.w $w0[1], $1
+; P5600-NEXT:    st.w $w0, 0($5)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load float, float* %pval, align 4
+  %1 = load <4 x float>, <4 x float>* %V, align 16
+  %vecins = insertelement <4 x float> %1, float %0, i32 1
+  store <4 x float> %vecins, <4 x float>* %V, align 16
+  ret void
+}
+
+define void @insert_double(double %val, <2 x double>* %V) {
+; P5600-LABEL: insert_double:
+; P5600:       # %bb.0: # %entry
+; P5600-NEXT:    ld.d $w0, 0($6)
+; P5600-NEXT:    mov.d $f1, $f12
+; P5600-NEXT:    insve.d $w0[1], $w1[0]
+; P5600-NEXT:    st.d $w0, 0($6)
+; P5600-NEXT:    jr $ra
+; P5600-NEXT:    nop
+entry:
+  %0 = load <2 x double>, <2 x double>* %V, align 16
+  %vecins = insertelement <2 x double> %0, double %val, i32 1
+  store <2 x double> %vecins, <2 x double>* %V, align 16
+  ret void
+}

llvm/test/CodeGen/Mips/GlobalISel/regbankselect/insert_vector_elt_imm_index.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
+--- |
+
+  define void @insert_i8(i8 %val, <16 x i8>* %V) { entry: ret void }
+  define void @insert_i16(i16 %val, <8 x i16>* %V) { entry: ret void }
+  define void @insert_i32(i32 %val, <4 x i32>* %V) { entry: ret void }
+  define void @insert_i64_fprb(i64* %pval, <2 x i64>* %V) { entry: ret void }
+  define void @insert_float_fprb(float %val, <4 x float>* %V) { entry: ret void }
+  define void @insert_float_gprb(float* %pval, <4 x float>* %V) { entry: ret void }
+  define void @insert_double(double %val, <2 x double>* %V) { entry: ret void }
+
+...
+---
+name:            insert_i8
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i8
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 7
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
+    ; P5600: [[IVEC:%[0-9]+]]:fprb(<16 x s8>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY2]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %2:_(s32) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %5:_(s32) = G_CONSTANT i32 7
+    %3:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %6:_(s32) = COPY %2(s32)
+    %4:_(<16 x s8>) = G_INSERT_VECTOR_ELT %3, %6(s32), %5(s32)
+    G_STORE %4(<16 x s8>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i16
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i16
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 5
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
+    ; P5600: [[IVEC:%[0-9]+]]:fprb(<8 x s16>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY2]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %2:_(s32) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %5:_(s32) = G_CONSTANT i32 5
+    %3:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %6:_(s32) = COPY %2(s32)
+    %4:_(<8 x s16>) = G_INSERT_VECTOR_ELT %3, %6(s32), %5(s32)
+    G_STORE %4(<8 x s16>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i32
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i32
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_CONSTANT i32 2
+    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %4(s32)
+    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_i64_fprb
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_i64_fprb
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.pval)
+    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:fprb(<2 x s64>) = G_INSERT_VECTOR_ELT [[LOAD1]], [[LOAD]](s64), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %5:_(s32) = G_CONSTANT i32 0
+    %2:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.pval)
+    %3:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:_(<2 x s64>) = G_INSERT_VECTOR_ELT %3, %2(s64), %5(s32)
+    G_STORE %4(<2 x s64>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_float_fprb
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a1, $f12
+
+    ; P5600-LABEL: name: insert_float_fprb
+    ; P5600: liveins: $a1, $f12
+    ; P5600: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(s32) = COPY $f12
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_CONSTANT i32 3
+    %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %4(s32)
+    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_float_gprb
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; P5600-LABEL: name: insert_float_gprb
+    ; P5600: liveins: $a0, $a1
+    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; P5600: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.pval)
+    ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:fprb(<4 x s32>) = G_INSERT_VECTOR_ELT [[LOAD1]], [[LOAD]](s32), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %5:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.pval)
+    %3:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %3, %2(s32), %5(s32)
+    G_STORE %4(<4 x s32>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...
+---
+name:            insert_double
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a2, $d12_64
+
+    ; P5600-LABEL: name: insert_double
+    ; P5600: liveins: $a2, $d12_64
+    ; P5600: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d12_64
+    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a2
+    ; P5600: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.V)
+    ; P5600: [[IVEC:%[0-9]+]]:fprb(<2 x s64>) = G_INSERT_VECTOR_ELT [[LOAD]], [[COPY]](s64), [[C]](s32)
+    ; P5600: G_STORE [[IVEC]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.V)
+    ; P5600: RetRA
+    %0:_(s64) = COPY $d12_64
+    %1:_(p0) = COPY $a2
+    %4:_(s32) = G_CONSTANT i32 1
+    %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.V)
+    %3:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %4(s32)
+    G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.V)
+    RetRA
+
+...