[Sparc] Fix "Cannot select" error for AtomicFence on 32-bit V9

[jrtc27]

Summary

This also adds testing of 32-bit V9 atomic lowering, splitting the
64-bit-only tests out into their own file.

llvm/lib/Target/Sparc/SparcInstr64Bit.td

def CASXrr: F3_1_asi<3, 0b111110,
                  "casx [$rs1], $rs2, $rd",
                  [(set i64:$rd,
                      (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>;
 
 } // Predicates = [Is64Bit], Constraints = ...
 
 let Predicates = [Is64Bit] in {
 
-def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
-
 // atomic_load_64 addr -> load addr
 def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
 def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;
 
 // atomic_store_64 val, addr -> store val, addr
 def : Pat<(atomic_store_64 ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>;
 def : Pat<(atomic_store_64 ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>;
 

llvm/lib/Target/Sparc/SparcInstrInfo.td

 // store 0, addr -> store %g0, addr
 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
 
 // store bar for all atomic_fence in V8.
 let Predicates = [HasNoV9] in
   def : Pat<(atomic_fence imm, imm), (STBAR)>;
 
+let Predicates = [HasV9] in
+  def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
+
 // atomic_load addr -> load addr
 def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
 def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
 def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
 def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
 def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>;
 def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>;
 

llvm/test/CodeGen/SPARC/64atomics.ll

+; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
+
+; CHECK-LABEL: test_atomic_i64
+; CHECK:       ldx [%o0]
+; CHECK:       membar
+; CHECK:       ldx [%o1]
+; CHECK:       membar
+; CHECK:       membar
+; CHECK:       stx {{.+}}, [%o2]
+define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
+entry:
+  %0 = load atomic i64, i64* %ptr1 acquire, align 8
+  %1 = load atomic i64, i64* %ptr2 acquire, align 8
+  %2 = add i64 %0, %1
+  store atomic i64 %2, i64* %ptr3 release, align 8
+  ret i64 %2
+}
+
+; CHECK-LABEL: test_cmpxchg_i64
+; CHECK:       mov 123, [[R:%[gilo][0-7]]]
+; CHECK:       casx [%o1], %o0, [[R]]
+
+define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
+entry:
+  %pair = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
+  %b = extractvalue { i64, i1 } %pair, 0
+  ret i64 %b
+}
+
+; CHECK-LABEL: test_swap_i64
+; CHECK:       casx [%o1],
+
+define i64 @test_swap_i64(i64 %a, i64* %ptr) {
+entry:
+  %b = atomicrmw xchg i64* %ptr, i64 42 monotonic
+  ret i64 %b
+}
+
+; CHECK-LABEL: test_load_sub_64
+; CHECK: membar
+; CHECK: sub
+; CHECK: casx [%o0]
+; CHECK: membar
+define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
+entry:
+  %0 = atomicrmw sub i64* %p, i64 %v seq_cst
+  ret i64 %0
+}
+
+; CHECK-LABEL: test_load_max_64
+; CHECK: membar
+; CHECK: cmp
+; CHECK: movg %xcc
+; CHECK: casx [%o0]
+; CHECK: membar
+define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
+entry:
+  %0 = atomicrmw max i64* %p, i64 %v seq_cst
+  ret i64 %0
+}

llvm/test/CodeGen/SPARC/atomics.ll

+; RUN: llc < %s -march=sparc -mcpu=v9 -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: test_atomic_i8
 ; CHECK:       ldub [%o0]
 ; CHECK:       membar
 ; CHECK:       ldub [%o1]
 ; CHECK:       membar
 ; CHECK:       membar

 entry:
   %0 = load atomic i32, i32* %ptr1 acquire, align 4
   %1 = load atomic i32, i32* %ptr2 acquire, align 4
   %2 = add i32 %0, %1
   store atomic i32 %2, i32* %ptr3 release, align 4
   ret i32 %2
 }
 
-; CHECK-LABEL: test_atomic_i64
-; CHECK:       ldx [%o0]
-; CHECK:       membar
-; CHECK:       ldx [%o1]
-; CHECK:       membar
-; CHECK:       membar
-; CHECK:       stx {{.+}}, [%o2]
-define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
-entry:
-  %0 = load atomic i64, i64* %ptr1 acquire, align 8
-  %1 = load atomic i64, i64* %ptr2 acquire, align 8
-  %2 = add i64 %0, %1
-  store atomic i64 %2, i64* %ptr3 release, align 8
-  ret i64 %2
-}
-
 ;; TODO: the "move %icc" and related instructions are totally
 ;; redundant here. There's something weird happening in optimization
 ;; of the success value of cmpxchg.
 
 ; CHECK-LABEL: test_cmpxchg_i8
 ; CHECK:       and %o1, -4, %o2
 ; CHECK:       mov  3, %o3
 ; CHECK:       andn %o3, %o1, %o1

 
 define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
 entry:
   %pair = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic monotonic
   %b = extractvalue { i32, i1 } %pair, 0
   ret i32 %b
 }
 
-; CHECK-LABEL: test_cmpxchg_i64
-; CHECK:       mov 123, [[R:%[gilo][0-7]]]
-; CHECK:       casx [%o1], %o0, [[R]]
-
-define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
-entry:
-  %pair = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
-  %b = extractvalue { i64, i1 } %pair, 0
-  ret i64 %b
-}
-
 ; CHECK-LABEL: test_swap_i8
 ; CHECK:       mov 42, [[R:%[gilo][0-7]]]
 ; CHECK:       cas
 
 define i8 @test_swap_i8(i8 %a, i8* %ptr) {
 entry:
   %b = atomicrmw xchg i8* %ptr, i8 42 monotonic
   ret i8 %b

 ; CHECK:       swap [%o1], [[R]]
 
 define i32 @test_swap_i32(i32 %a, i32* %ptr) {
 entry:
   %b = atomicrmw xchg i32* %ptr, i32 42 monotonic
   ret i32 %b
 }
 
-; CHECK-LABEL: test_swap_i64
-; CHECK:       casx [%o1],
-
-define i64 @test_swap_i64(i64 %a, i64* %ptr) {
-entry:
-  %b = atomicrmw xchg i64* %ptr, i64 42 monotonic
-  ret i64 %b
-}
-
 ; CHECK-LABEL: test_load_sub_i8
 ; CHECK: membar
 ; CHECK: .L{{.*}}:
 ; CHECK: sub
 ; CHECK: cas [{{%[gilo][0-7]}}]
 ; CHECK: membar
 define zeroext i8 @test_load_sub_i8(i8* %p, i8 zeroext %v) {
 entry:

 ; CHECK: cas [%o0], [[V]], [[V2]]
 ; CHECK: membar
 define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
 entry:
   %0 = atomicrmw add i32* %p, i32 %v seq_cst
   ret i32 %0
 }
 
-; CHECK-LABEL: test_load_sub_64
-; CHECK: membar
-; CHECK: sub
-; CHECK: casx [%o0]
-; CHECK: membar
-define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
-entry:
-  %0 = atomicrmw sub i64* %p, i64 %v seq_cst
-  ret i64 %0
-}
-
 ; CHECK-LABEL: test_load_xor_32
 ; CHECK: membar
 ; CHECK: xor
 ; CHECK: cas [%o0]
 ; CHECK: membar
 define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
 entry:
   %0 = atomicrmw xor i32* %p, i32 %v seq_cst

 ; CHECK: cas [%o0]
 ; CHECK: membar
 define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
 entry:
   %0 = atomicrmw nand i32* %p, i32 %v seq_cst
   ret i32 %0
 }
 
-; CHECK-LABEL: test_load_max_64
-; CHECK: membar
-; CHECK: cmp
-; CHECK: movg %xcc
-; CHECK: casx [%o0]
-; CHECK: membar
-define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
-entry:
-  %0 = atomicrmw max i64* %p, i64 %v seq_cst
-  ret i64 %0
-}
-
 ; CHECK-LABEL: test_load_umin_32
 ; CHECK: membar
 ; CHECK: cmp
 ; CHECK: movleu %icc
 ; CHECK: cas [%o0]
 ; CHECK: membar
 define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
 entry:
   %0 = atomicrmw umin i32* %p, i32 %v seq_cst
   ret i32 %0
 }