This is an archive of the discontinued LLVM Phabricator instance.

Differential D69306

[MIPS GlobalISel] Select MSA vector generic and builtin sub
ClosedPublic

Authored by Petar.Avramovic on Oct 22 2019, 8:06 AM.

Details

Reviewers
atanasyan
petarj
Commits
rGc46d24f5c314: [MIPS GlobalISel] Select MSA vector generic and builtin sub
Summary

Select vector G_SUB for MIPS32 with MSA. We have to set bank
for vector operands to fprb and selectImpl will do the rest.
builtin_msa_subv_<format> will be transformed into G_SUB
in legalizeIntrinsic and selected in the same way.
builtin_msa_subvi_<format> will be directly selected into
SUBVI_<format> in legalizeIntrinsic.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Oct 22 2019, 8:06 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 22 2019, 8:06 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 2 others. · View Herald Transcript
atanasyan accepted this revision.Oct 23 2019, 1:22 AM

LGTM

This revision is now accepted and ready to land.Oct 23 2019, 1:22 AM
Closed by commit rGc46d24f5c314: [MIPS GlobalISel] Select MSA vector generic and builtin sub (authored by Petar.Avramovic). · Explain WhyOct 23 2019, 2:18 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: hiraditya. · View Herald TranscriptOct 23 2019, 2:18 AM

Revision Contents

PathSize
llvm/
lib/
Target/
Mips/
17 lines
2 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
130 lines
legalizer/
122 lines
237 lines
llvm-ir/
70 lines
138 lines
regbankselect/
126 lines

Diff 226102

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
const LLT s32 = LLT::scalar(32); const LLT s32 = LLT::scalar(32);
const LLT s64 = LLT::scalar(64); const LLT s64 = LLT::scalar(64);
const LLT v16s8 = LLT::vector(16, 8); const LLT v16s8 = LLT::vector(16, 8);
const LLT v8s16 = LLT::vector(8, 16); const LLT v8s16 = LLT::vector(8, 16);
const LLT v4s32 = LLT::vector(4, 32); const LLT v4s32 = LLT::vector(4, 32);
const LLT v2s64 = LLT::vector(2, 64); const LLT v2s64 = LLT::vector(2, 64);
const LLT p0 = LLT::pointer(0, 32); const LLT p0 = LLT::pointer(0, 32);
getActionDefinitionsBuilder({G_SUB, G_MUL}) getActionDefinitionsBuilder(G_MUL)
.legalFor({s32}) .legalFor({s32})
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
getActionDefinitionsBuilder(G_ADD) getActionDefinitionsBuilder({G_ADD, G_SUB})
.legalIf([=, &ST](const LegalityQuery &Query) { .legalIf([=, &ST](const LegalityQuery &Query) {
if (CheckTyN(0, Query, {s32})) if (CheckTyN(0, Query, {s32}))
return true; return true;
if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
return true; return true;
return false; return false;
}) })
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
▲ Show 20 Lines • Show All 282 Lines • ▼ Show 20 Linesbool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
case Intrinsic::mips_addvi_b: case Intrinsic::mips_addvi_b:
return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST); return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
case Intrinsic::mips_addvi_h: case Intrinsic::mips_addvi_h:
return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST); return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
case Intrinsic::mips_addvi_w: case Intrinsic::mips_addvi_w:
return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST); return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
case Intrinsic::mips_addvi_d: case Intrinsic::mips_addvi_d:
return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST); return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
case Intrinsic::mips_subv_b:
case Intrinsic::mips_subv_h:
case Intrinsic::mips_subv_w:
case Intrinsic::mips_subv_d:
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SUB, MIRBuilder, ST);
case Intrinsic::mips_subvi_b:
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST);
case Intrinsic::mips_subvi_h:
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_H, MIRBuilder, ST);
case Intrinsic::mips_subvi_w:
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
case Intrinsic::mips_subvi_d:
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
default: default:
break; break;
} }
return true; return true;
} }

llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 431 Lines • ▼ Show 20 LinesMipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
} }
const LLT Op0Ty = MRI.getType(MI.getOperand(0).getReg()); const LLT Op0Ty = MRI.getType(MI.getOperand(0).getReg());
unsigned Op0Size = Op0Ty.getSizeInBits(); unsigned Op0Size = Op0Ty.getSizeInBits();
InstType InstTy = InstType::Integer; InstType InstTy = InstType::Integer;
switch (Opc) { switch (Opc) {
case G_TRUNC: case G_TRUNC:
case G_SUB:
case G_MUL: case G_MUL:
case G_UMULH: case G_UMULH:
case G_ZEXTLOAD: case G_ZEXTLOAD:
case G_SEXTLOAD: case G_SEXTLOAD:
case G_GEP: case G_GEP:
case G_INTTOPTR: case G_INTTOPTR:
case G_PTRTOINT: case G_PTRTOINT:
case G_AND: case G_AND:
case G_OR: case G_OR:
case G_XOR: case G_XOR:
case G_SHL: case G_SHL:
case G_ASHR: case G_ASHR:
case G_LSHR: case G_LSHR:
case G_SDIV: case G_SDIV:
case G_UDIV: case G_UDIV:
case G_SREM: case G_SREM:
case G_UREM: case G_UREM:
case G_BRINDIRECT: case G_BRINDIRECT:
case G_VASTART: case G_VASTART:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
break; break;
case G_ADD: case G_ADD:
case G_SUB:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
if (Op0Size == 128) if (Op0Size == 128)
OperandsMapping = getMSAMapping(MF); OperandsMapping = getMSAMapping(MF);
break; break;
case G_STORE: case G_STORE:
case G_LOAD: case G_LOAD:
if (Op0Size == 128) { if (Op0Size == 128) {
OperandsMapping = getOperandsMapping( OperandsMapping = getOperandsMapping(
▲ Show 20 Lines • Show All 235 Lines • Show Last 20 Lines

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
...
---
name: sub_v16i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v16i8
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
; P5600: [[SUBV_B:%[0-9]+]]:msa128b = SUBV_B [[LD_B1]], [[LD_B]]
; P5600: ST_B [[SUBV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
; P5600: RetRA
%0:gprb(p0) = COPY $a0
%1:gprb(p0) = COPY $a1
%2:gprb(p0) = COPY $a2
%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:fprb(<16 x s8>) = G_SUB %4, %3
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v8i16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v8i16
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a)
; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)
; P5600: [[SUBV_H:%[0-9]+]]:msa128h = SUBV_H [[LD_H1]], [[LD_H]]
; P5600: ST_H [[SUBV_H]], [[COPY2]], 0 :: (store 16 into %ir.c)
; P5600: RetRA
%0:gprb(p0) = COPY $a0
%1:gprb(p0) = COPY $a1
%2:gprb(p0) = COPY $a2
%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:fprb(<8 x s16>) = G_SUB %4, %3
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v4i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v4i32
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
; P5600: [[SUBV_W:%[0-9]+]]:msa128w = SUBV_W [[LD_W1]], [[LD_W]]
; P5600: ST_W [[SUBV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
; P5600: RetRA
%0:gprb(p0) = COPY $a0
%1:gprb(p0) = COPY $a1
%2:gprb(p0) = COPY $a2
%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:fprb(<4 x s32>) = G_SUB %4, %3
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v2i64
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v2i64
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a)
; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
; P5600: [[SUBV_D:%[0-9]+]]:msa128d = SUBV_D [[LD_D1]], [[LD_D]]
; P5600: ST_D [[SUBV_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
; P5600: RetRA
%0:gprb(p0) = COPY $a0
%1:gprb(p0) = COPY $a1
%2:gprb(p0) = COPY $a2
%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:fprb(<2 x s64>) = G_SUB %4, %3
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
RetRA
...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
...
---
name: sub_v16i8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v16i8
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<16 x s8>) = G_SUB %4, %3
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v8i16
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v8i16
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<8 x s16>) = G_SUB %4, %3
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v4i32
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v4i32
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<4 x s32>) = G_SUB %4, %3
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v2i64
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v2i64
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<2 x s64>) = G_SUB %4, %3
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
RetRA
...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
declare <16 x i8> @llvm.mips.subv.b(<16 x i8>, <16 x i8>)
define void @sub_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
declare <8 x i16> @llvm.mips.subv.h(<8 x i16>, <8 x i16>)
define void @sub_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
declare <4 x i32> @llvm.mips.subv.w(<4 x i32>, <4 x i32>)
define void @sub_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>)
define void @sub_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32 immarg)
define void @sub_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) { entry: ret void }
declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32 immarg)
define void @sub_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) { entry: ret void }
declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32 immarg)
define void @sub_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
declare <2 x i64> @llvm.mips.subvi.d(<2 x i64>, i32 immarg)
define void @sub_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) { entry: ret void }
...
---
name: sub_v16i8_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v16i8_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SUB]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.subv.b), %3(<16 x s8>), %4(<16 x s8>)
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v8i16_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v8i16_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SUB]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.subv.h), %3(<8 x s16>), %4(<8 x s16>)
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v4i32_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v4i32_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SUB]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.subv.w), %3(<4 x s32>), %4(<4 x s32>)
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v2i64_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v2i64_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SUB]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.subv.d), %3(<2 x s64>), %4(<2 x s64>)
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v16i8_builtin_imm
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; P5600-LABEL: name: sub_v16i8_builtin_imm
; P5600: liveins: $a0, $a1
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[LOAD:%[0-9]+]]:msa128b(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[SUBVI_B:%[0-9]+]]:msa128b(<16 x s8>) = SUBVI_B [[LOAD]](<16 x s8>), 3
; P5600: G_STORE [[SUBVI_B]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%3:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.subvi.b), %2(<16 x s8>), 3
G_STORE %3(<16 x s8>), %1(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v8i16_builtin_imm
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; P5600-LABEL: name: sub_v8i16_builtin_imm
; P5600: liveins: $a0, $a1
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[LOAD:%[0-9]+]]:msa128h(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[SUBVI_H:%[0-9]+]]:msa128h(<8 x s16>) = SUBVI_H [[LOAD]](<8 x s16>), 18
; P5600: G_STORE [[SUBVI_H]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%3:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.subvi.h), %2(<8 x s16>), 18
G_STORE %3(<8 x s16>), %1(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v4i32_builtin_imm
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; P5600-LABEL: name: sub_v4i32_builtin_imm
; P5600: liveins: $a0, $a1
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[SUBVI_W:%[0-9]+]]:msa128w(<4 x s32>) = SUBVI_W [[LOAD]](<4 x s32>), 25
; P5600: G_STORE [[SUBVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.subvi.w), %2(<4 x s32>), 25
G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v2i64_builtin_imm
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; P5600-LABEL: name: sub_v2i64_builtin_imm
; P5600: liveins: $a0, $a1
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[SUBVI_D:%[0-9]+]]:msa128d(<2 x s64>) = SUBVI_D [[LOAD]](<2 x s64>), 31
; P5600: G_STORE [[SUBVI_D]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.subvi.d), %2(<2 x s64>), 31
G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
RetRA
...

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
; P5600-LABEL: sub_v16i8:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.b $w0, 0($4)
; P5600-NEXT: ld.b $w1, 0($5)
; P5600-NEXT: subv.b $w0, $w1, $w0
; P5600-NEXT: st.b $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <16 x i8>, <16 x i8>* %a, align 16
%1 = load <16 x i8>, <16 x i8>* %b, align 16
%sub = sub <16 x i8> %1, %0
store <16 x i8> %sub, <16 x i8>* %c, align 16
ret void
}
define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
; P5600-LABEL: sub_v8i16:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.h $w0, 0($4)
; P5600-NEXT: ld.h $w1, 0($5)
; P5600-NEXT: subv.h $w0, $w1, $w0
; P5600-NEXT: st.h $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <8 x i16>, <8 x i16>* %a, align 16
%1 = load <8 x i16>, <8 x i16>* %b, align 16
%sub = sub <8 x i16> %1, %0
store <8 x i16> %sub, <8 x i16>* %c, align 16
ret void
}
define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
; P5600-LABEL: sub_v4i32:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.w $w0, 0($4)
; P5600-NEXT: ld.w $w1, 0($5)
; P5600-NEXT: subv.w $w0, $w1, $w0
; P5600-NEXT: st.w $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <4 x i32>, <4 x i32>* %a, align 16
%1 = load <4 x i32>, <4 x i32>* %b, align 16
%sub = sub <4 x i32> %1, %0
store <4 x i32> %sub, <4 x i32>* %c, align 16
ret void
}
define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
; P5600-LABEL: sub_v2i64:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.d $w0, 0($4)
; P5600-NEXT: ld.d $w1, 0($5)
; P5600-NEXT: subv.d $w0, $w1, $w0
; P5600-NEXT: st.d $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <2 x i64>, <2 x i64>* %a, align 16
%1 = load <2 x i64>, <2 x i64>* %b, align 16
%sub = sub <2 x i64> %1, %0
store <2 x i64> %sub, <2 x i64>* %c, align 16
ret void
}

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec_builtin.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
declare <16 x i8> @llvm.mips.subv.b(<16 x i8>, <16 x i8>)
define void @sub_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
; P5600-LABEL: sub_v16i8_builtin:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.b $w0, 0($4)
; P5600-NEXT: ld.b $w1, 0($5)
; P5600-NEXT: subv.b $w0, $w0, $w1
; P5600-NEXT: st.b $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <16 x i8>, <16 x i8>* %a, align 16
%1 = load <16 x i8>, <16 x i8>* %b, align 16
%2 = tail call <16 x i8> @llvm.mips.subv.b(<16 x i8> %0, <16 x i8> %1)
store <16 x i8> %2, <16 x i8>* %c, align 16
ret void
}
declare <8 x i16> @llvm.mips.subv.h(<8 x i16>, <8 x i16>)
define void @sub_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
; P5600-LABEL: sub_v8i16_builtin:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.h $w0, 0($4)
; P5600-NEXT: ld.h $w1, 0($5)
; P5600-NEXT: subv.h $w0, $w0, $w1
; P5600-NEXT: st.h $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <8 x i16>, <8 x i16>* %a, align 16
%1 = load <8 x i16>, <8 x i16>* %b, align 16
%2 = tail call <8 x i16> @llvm.mips.subv.h(<8 x i16> %0, <8 x i16> %1)
store <8 x i16> %2, <8 x i16>* %c, align 16
ret void
}
declare <4 x i32> @llvm.mips.subv.w(<4 x i32>, <4 x i32>)
define void @sub_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
; P5600-LABEL: sub_v4i32_builtin:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.w $w0, 0($4)
; P5600-NEXT: ld.w $w1, 0($5)
; P5600-NEXT: subv.w $w0, $w0, $w1
; P5600-NEXT: st.w $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <4 x i32>, <4 x i32>* %a, align 16
%1 = load <4 x i32>, <4 x i32>* %b, align 16
%2 = tail call <4 x i32> @llvm.mips.subv.w(<4 x i32> %0, <4 x i32> %1)
store <4 x i32> %2, <4 x i32>* %c, align 16
ret void
}
declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>)
define void @sub_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
; P5600-LABEL: sub_v2i64_builtin:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.d $w0, 0($4)
; P5600-NEXT: ld.d $w1, 0($5)
; P5600-NEXT: subv.d $w0, $w0, $w1
; P5600-NEXT: st.d $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <2 x i64>, <2 x i64>* %a, align 16
%1 = load <2 x i64>, <2 x i64>* %b, align 16
%2 = tail call <2 x i64> @llvm.mips.subv.d(<2 x i64> %0, <2 x i64> %1)
store <2 x i64> %2, <2 x i64>* %c, align 16
ret void
}
declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32 immarg)
define void @sub_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) {
; P5600-LABEL: sub_v16i8_builtin_imm:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.b $w0, 0($4)
; P5600-NEXT: subvi.b $w0, $w0, 3
; P5600-NEXT: st.b $w0, 0($5)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <16 x i8>, <16 x i8>* %a, align 16
%1 = tail call <16 x i8> @llvm.mips.subvi.b(<16 x i8> %0, i32 3)
store <16 x i8> %1, <16 x i8>* %c, align 16
ret void
}
declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32 immarg)
define void @sub_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) {
; P5600-LABEL: sub_v8i16_builtin_imm:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.h $w0, 0($4)
; P5600-NEXT: subvi.h $w0, $w0, 18
; P5600-NEXT: st.h $w0, 0($5)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <8 x i16>, <8 x i16>* %a, align 16
%1 = tail call <8 x i16> @llvm.mips.subvi.h(<8 x i16> %0, i32 18)
store <8 x i16> %1, <8 x i16>* %c, align 16
ret void
}
declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32 immarg)
define void @sub_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
; P5600-LABEL: sub_v4i32_builtin_imm:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.w $w0, 0($4)
; P5600-NEXT: subvi.w $w0, $w0, 25
; P5600-NEXT: st.w $w0, 0($5)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <4 x i32>, <4 x i32>* %a, align 16
%1 = tail call <4 x i32> @llvm.mips.subvi.w(<4 x i32> %0, i32 25)
store <4 x i32> %1, <4 x i32>* %c, align 16
ret void
}
declare <2 x i64> @llvm.mips.subvi.d(<2 x i64>, i32 immarg)
define void @sub_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) {
; P5600-LABEL: sub_v2i64_builtin_imm:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.d $w0, 0($4)
; P5600-NEXT: subvi.d $w0, $w0, 31
; P5600-NEXT: st.d $w0, 0($5)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
entry:
%0 = load <2 x i64>, <2 x i64>* %a, align 16
%1 = tail call <2 x i64> @llvm.mips.subvi.d(<2 x i64> %0, i32 31)
store <2 x i64> %1, <2 x i64>* %c, align 16
ret void
}

llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
...
---
name: sub_v16i8
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v16i8
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:fprb(<16 x s8>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<16 x s8>) = G_SUB %4, %3
G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v8i16
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v8i16
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:fprb(<8 x s16>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<8 x s16>) = G_SUB %4, %3
G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v4i32
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v4i32
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:fprb(<4 x s32>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<4 x s32>) = G_SUB %4, %3
G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
RetRA
...
---
name: sub_v2i64
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sub_v2i64
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
; P5600: [[SUB:%[0-9]+]]:fprb(<2 x s64>) = G_SUB [[LOAD1]], [[LOAD]]
; P5600: G_STORE [[SUB]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
%5:_(<2 x s64>) = G_SUB %4, %3
G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
RetRA
...