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Differential D69287

[AMDGPU] Allows tied operand subreg folding
ClosedPublic

Authored by rampitec on Oct 21 2019, 4:30 PM.

Details

Reviewers
arsenm
nhaehnle
Commits
rG48f57138be55: [AMDGPU] Allow tied operand subreg folding
Summary

Turns out it makes sense, contrarily to what comment said.

Diff Detail

Event Timeline

rampitec created this revision.Oct 21 2019, 4:30 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 21 2019, 4:30 PM
Herald added subscribers: hiraditya, t-tye, tpr and 6 others. · View Herald Transcript
rampitec added a parent revision: D69280: [AMDGPU] Allow folding of sgpr to vgpr copy.Oct 21 2019, 4:31 PM
rampitec mentioned this in D69280: [AMDGPU] Allow folding of sgpr to vgpr copy.
nhaehnle accepted this revision.Oct 22 2019, 4:56 AM

LGTM

This revision is now accepted and ready to land.Oct 22 2019, 4:56 AM
rampitec updated this revision to Diff 226062.Oct 22 2019, 11:19 AM

Rebased to master.

rampitec removed a parent revision: D69280: [AMDGPU] Allow folding of sgpr to vgpr copy.Oct 22 2019, 11:19 AM
Closed by commit rG48f57138be55: [AMDGPU] Allow tied operand subreg folding (authored by rampitec). · Explain WhyOct 22 2019, 11:34 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
12 lines
test/
CodeGen/
AMDGPU/
16 lines

Diff 226062

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Show First 20 Lines • Show All 507 Lines • ▼ Show 20 Linesvoid SIFoldOperands::foldOperand(
if (!isUseSafeToFold(TII, *UseMI, UseOp)) if (!isUseSafeToFold(TII, *UseMI, UseOp))
return; return;
// FIXME: Fold operands with subregs. // FIXME: Fold operands with subregs.
if (UseOp.isReg() && OpToFold.isReg()) { if (UseOp.isReg() && OpToFold.isReg()) {
if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister) if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
return; return;
// Don't fold subregister extracts into tied operands, only if it is a full
// copy since a subregister use tied to a full register def doesn't really
// make sense. e.g. don't fold:
//
// %1 = COPY %0:sub1
// %2<tied3> = V_MAC_{F16, F32} %3, %4, %1<tied0>
//
// into
// %2<tied3> = V_MAC_{F16, F32} %3, %4, %0:sub1<tied0>
if (UseOp.isTied() && OpToFold.getSubReg() != AMDGPU::NoSubRegister)
return;
} }
// Special case for REG_SEQUENCE: We can't fold literals into // Special case for REG_SEQUENCE: We can't fold literals into
// REG_SEQUENCE instructions, so we have to fold them into the // REG_SEQUENCE instructions, so we have to fold them into the
// uses of REG_SEQUENCE. // uses of REG_SEQUENCE.
if (UseMI->isRegSequence()) { if (UseMI->isRegSequence()) {
Register RegSeqDstReg = UseMI->getOperand(0).getReg(); Register RegSeqDstReg = UseMI->getOperand(0).getReg();
unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm(); unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm();
▲ Show 20 Lines • Show All 878 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir

Show All 19 Lines bb.0:
%0:vreg_64 = IMPLICIT_DEF %0:vreg_64 = IMPLICIT_DEF
%4 = IMPLICIT_DEF %4 = IMPLICIT_DEF
%3 = IMPLICIT_DEF %3 = IMPLICIT_DEF
%1:vgpr_32 = COPY %0.sub0 %1:vgpr_32 = COPY %0.sub0
%2:vgpr_32 = COPY %1 %2:vgpr_32 = COPY %1
DS_WRITE2_B32_gfx9 %2, killed %4, killed %3, 0, 1, 0, implicit $exec DS_WRITE2_B32_gfx9 %2, killed %4, killed %3, 0, 1, 0, implicit $exec
... ...
# GCN-LABEL: name: fma_sgpr_use
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
# GCN: %4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMAC_F32_e64 2, %0.sub0, 0, 1073741824, 0, %3, 0, 0, implicit $exec
---
name: fma_sgpr_use
body: |
bb.0:
%0:sreg_64_xexec = IMPLICIT_DEF
%1:sgpr_32 = COPY %0.sub0
%2:sgpr_32 = COPY %0.sub1
%3:vgpr_32 = COPY %2
%4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMAC_F32_e64 2, %1, 0, 1073741824, 0, %3, 0, 0, implicit $exec
DS_WRITE2_B32_gfx9 undef %5:vgpr_32, killed %4, undef %6:vgpr_32, 0, 1, 0, implicit $exec
...