AMDGPU: Use CopyToReg for interp intrinsic lowering

[arsenm]

Summary

This doesn't use the default value, so doesn't benefit from the hack
to help optimize it.

[rampitec]

LGTM

[arsenm]

r375450

lib/Target/AMDGPU/SIISelLowering.cpp

if (!parseCachePolicy(Op.getOperand(3), DAG, &GLC, nullptr,
                           IsGFX10 ? &DLC : nullptr))
       return Op;
     return lowerSBuffer(VT, DL, Op.getOperand(1), Op.getOperand(2), GLC, DLC,
                         DAG);
   }
   case Intrinsic::amdgcn_fdiv_fast:
     return lowerFDIV_FAST(Op, DAG);
   case Intrinsic::amdgcn_interp_mov: {
-    SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
-    SDValue Glue = M0.getValue(1);
+    SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
+                                    Op.getOperand(4), SDValue());
     return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32, Op.getOperand(1),
-                       Op.getOperand(2), Op.getOperand(3), Glue);
+                       Op.getOperand(2), Op.getOperand(3), ToM0.getValue(1));
   }
   case Intrinsic::amdgcn_interp_p1: {
-    SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
-    SDValue Glue = M0.getValue(1);
+    SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
+                                    Op.getOperand(4), SDValue());
     return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
-                       Op.getOperand(2), Op.getOperand(3), Glue);
+                       Op.getOperand(2), Op.getOperand(3), ToM0.getValue(1));
   }
   case Intrinsic::amdgcn_interp_p2: {
-    SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
-    SDValue Glue = SDValue(M0.getNode(), 1);
+    SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
+                                    Op.getOperand(5), SDValue());
     return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
                        Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
-                       Glue);
+                       ToM0.getValue(1));
   }
   case Intrinsic::amdgcn_interp_p1_f16: {
-    SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
-    SDValue Glue = M0.getValue(1);
+    SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
+                                    Op.getOperand(5), SDValue());
+
     if (getSubtarget()->getLDSBankCount() == 16) {
       // 16 bank LDS
       SDValue S = DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
                               DAG.getConstant(2, DL, MVT::i32), // P0
                               Op.getOperand(2), // Attrchan
                               Op.getOperand(3), // Attr
-                              Glue);
+                              ToM0.getValue(1));
       SDValue Ops[] = {
         Op.getOperand(1), // Src0
         Op.getOperand(2), // Attrchan
         Op.getOperand(3), // Attr
         DAG.getTargetConstant(0, DL, MVT::i32), // $src0_modifiers
         S, // Src2 - holds two f16 values selected by high
         DAG.getTargetConstant(0, DL, MVT::i32), // $src2_modifiers
         Op.getOperand(4), // high
         DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
         DAG.getTargetConstant(0, DL, MVT::i32) // $omod
       };
       return DAG.getNode(AMDGPUISD::INTERP_P1LV_F16, DL, MVT::f32, Ops);
     } else {
       // 32 bank LDS
       SDValue Ops[] = {
         Op.getOperand(1), // Src0
         Op.getOperand(2), // Attrchan
         Op.getOperand(3), // Attr
         DAG.getTargetConstant(0, DL, MVT::i32), // $src0_modifiers
         Op.getOperand(4), // high
         DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
         DAG.getTargetConstant(0, DL, MVT::i32), // $omod
-        Glue
+        ToM0.getValue(1)
       };
       return DAG.getNode(AMDGPUISD::INTERP_P1LL_F16, DL, MVT::f32, Ops);
     }
   }
   case Intrinsic::amdgcn_interp_p2_f16: {
-    SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(6));
-    SDValue Glue = SDValue(M0.getNode(), 1);
+    SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
+                                    Op.getOperand(6), SDValue());
     SDValue Ops[] = {
       Op.getOperand(2), // Src0
       Op.getOperand(3), // Attrchan
       Op.getOperand(4), // Attr
       DAG.getTargetConstant(0, DL, MVT::i32), // $src0_modifiers
       Op.getOperand(1), // Src2
       DAG.getTargetConstant(0, DL, MVT::i32), // $src2_modifiers
       Op.getOperand(5), // high
       DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
-      Glue
+      ToM0.getValue(1)
     };
     return DAG.getNode(AMDGPUISD::INTERP_P2_F16, DL, MVT::f16, Ops);
   }
   case Intrinsic::amdgcn_sin:
     return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
 
   case Intrinsic::amdgcn_cos:
     return DAG.getNode(AMDGPUISD::COS_HW, DL, VT, Op.getOperand(1));

test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-32BANK %s
 ; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-32BANK %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-16BANK %s
 
 define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
 ; GFX9-32BANK-LABEL: interp_f16:
 ; GFX9-32BANK:       ; %bb.0: ; %main_body
-; GFX9-32BANK-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, s2
+; GFX9-32BANK-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX9-32BANK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
 ; GFX9-32BANK-NEXT:    v_interp_p1ll_f16 v1, v0, attr2.y
 ; GFX9-32BANK-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-32BANK-NEXT:    v_interp_p1ll_f16 v0, v0, attr2.y high
 ; GFX9-32BANK-NEXT:    v_interp_p2_legacy_f16 v1, v2, attr2.y, v1
 ; GFX9-32BANK-NEXT:    v_interp_p2_legacy_f16 v0, v2, attr2.y, v0 high
 ; GFX9-32BANK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX9-32BANK-NEXT:    v_add_f16_e32 v0, v1, v0
 ; GFX9-32BANK-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-32BANK-LABEL: interp_f16:
 ; GFX8-32BANK:       ; %bb.0: ; %main_body
-; GFX8-32BANK-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, s2
+; GFX8-32BANK-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-32BANK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
 ; GFX8-32BANK-NEXT:    v_interp_p1ll_f16 v1, v0, attr2.y
 ; GFX8-32BANK-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX8-32BANK-NEXT:    v_interp_p1ll_f16 v0, v0, attr2.y high
 ; GFX8-32BANK-NEXT:    v_interp_p2_f16 v1, v2, attr2.y, v1
 ; GFX8-32BANK-NEXT:    v_interp_p2_f16 v0, v2, attr2.y, v0 high
 ; GFX8-32BANK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX8-32BANK-NEXT:    v_add_f16_e32 v0, v1, v0
main_body:
   %res = fadd half %p2_0, %mh
   ret half %res
 }
 
 ; check that m0 is setup correctly before the interp p2 instruction
 define amdgpu_ps half @interp_p2_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
 ; GFX9-32BANK-LABEL: interp_p2_m0_setup:
 ; GFX9-32BANK:       ; %bb.0: ; %main_body
-; GFX9-32BANK-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, s2
+; GFX9-32BANK-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX9-32BANK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
 ; GFX9-32BANK-NEXT:    v_interp_p1ll_f16 v0, v0, attr2.y
 ; GFX9-32BANK-NEXT:    ;;#ASMSTART
 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, 0
 ; GFX9-32BANK-NEXT:    ;;#ASMEND
 ; GFX9-32BANK-NEXT:    s_mov_b32 s0, m0
 ; GFX9-32BANK-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX9-32BANK-NEXT:    s_mov_b32 m0, s2
 ; GFX9-32BANK-NEXT:    v_interp_p2_legacy_f16 v0, v1, attr2.y, v0
 ; GFX9-32BANK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX9-32BANK-NEXT:    v_add_f16_e32 v0, s0, v0
 ; GFX9-32BANK-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-32BANK-LABEL: interp_p2_m0_setup:
 ; GFX8-32BANK:       ; %bb.0: ; %main_body
-; GFX8-32BANK-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, s2
+; GFX8-32BANK-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-32BANK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
 ; GFX8-32BANK-NEXT:    v_interp_p1ll_f16 v0, v0, attr2.y
 ; GFX8-32BANK-NEXT:    ;;#ASMSTART
 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, 0
 ; GFX8-32BANK-NEXT:    ;;#ASMEND
 ; GFX8-32BANK-NEXT:    s_mov_b32 s0, m0
 ; GFX8-32BANK-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX8-32BANK-NEXT:    s_mov_b32 m0, s2