[AArch64] Output the pseudo SPACE in asm and object files

[chill]

Summary

It outputs nothing, but is useful for writing tests, checking asm output.

[chill]

Ping?

[tellenbach]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

604

Although this case is certainly obvious: Don't use else after return (https://llvm.org/docs/CodingStandards.html#don-t-use-else-after-a-return).

[tellenbach]

LGTM, thanks!

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
   }
 
   if (Opcode == AArch64::CompilerBarrier) {
     O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
     printAnnotation(O, Annot);
     return;
   }
 
+  if (Opcode == AArch64::SPACE) {
+    O << '\t' << MAI.getCommentString() << " SPACE";
+    printAnnotation(O, Annot);
+    return;
+  }
+
   // Instruction TSB is specified as a one operand instruction, but 'csync' is
   // not encoded, so for printing it is treated as a special case here:
   if (Opcode == AArch64::TSB) {
     O << "\ttsb\tcsync";
     return;
   }
 
   if (!printAliasInstr(MI, STI, O))

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
 
   if (MI.getOpcode() == AArch64::TLSDESCCALL) {
     // This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
     // following (BLR) instruction. It doesn't emit any code itself so it
     // doesn't go through the normal TableGenerated channels.
     MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
     Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
     return;
-  } else if (MI.getOpcode() == AArch64::CompilerBarrier) {
-    // This just prevents the compiler from reordering accesses, no actual code.
+  } else if (MI.getOpcode() == AArch64::CompilerBarrier || MI.getOpcode() == AArch64::SPACE) {
+    // CompilerBarrier just prevents the compiler from reordering accesses, and
+    // SPACE just increases basic block size, in both cases no actual code.
     return;
   }
 
   uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
   support::endian::write<uint32_t>(OS, Binary, support::little);
   ++MCNumEmitted; // Keep track of the # of mi's emitted.
 }
 

llvm/test/CodeGen/AArch64/space.ll

+; RUN: llc -mtriple aarch64               %s -o - | FileCheck %s
+; RUN: llc -mtriple aarch64 -filetype=obj %s -o - | llvm-objdump --arch=aarch64  -d - | FileCheck %s --check-prefix=DUMP
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+
+define dso_local void @f(i64 %v) {
+entry:
+  %dummy = tail call i64 @llvm.aarch64.space(i32 32684, i64 %v)
+  ret void
+}
+; CHECK: // SPACE
+; CHECK-NEXT: ret
+; DUMP-LABEL: f:
+; DUMP-NEXT: ret
+
+declare dso_local i64 @llvm.aarch64.space(i32, i64) local_unnamed_addr #0