This is an archive of the discontinued LLVM Phabricator instance.

Show First 20 Lines • Show All 631 Lines • ▼ Show 20 Lines	const SDValue Ops[] = {
SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)};		SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)};

return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, VT, Ops);		return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, VT, Ops);
}		}

static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {		static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
switch (NumVectorElts) {		switch (NumVectorElts) {
case 1:		case 1:
return AMDGPU::SReg_32_XM0RegClassID;		return AMDGPU::SReg_32RegClassID;
case 2:		case 2:
return AMDGPU::SReg_64RegClassID;		return AMDGPU::SReg_64RegClassID;
case 3:		case 3:
return AMDGPU::SGPR_96RegClassID;		return AMDGPU::SGPR_96RegClassID;
case 4:		case 4:
return AMDGPU::SGPR_128RegClassID;		return AMDGPU::SGPR_128RegClassID;
case 5:		case 5:
return AMDGPU::SGPR_160RegClassID;		return AMDGPU::SGPR_160RegClassID;
▲ Show 20 Lines • Show All 2,098 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines	if (Register::isPhysicalRegister(Reg))
return Reg == AMDGPU::SCC;		return Reg == AMDGPU::SCC;

auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);		auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
const TargetRegisterClass *RC =		const TargetRegisterClass *RC =
RegClassOrBank.dyn_cast<const TargetRegisterClass*>();		RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
if (RC) {		if (RC) {
// FIXME: This is ambiguous for wave32. This could be SCC or VCC, but the		// FIXME: This is ambiguous for wave32. This could be SCC or VCC, but the
// context of the register bank has been lost.		// context of the register bank has been lost.
if (RC->getID() != AMDGPU::SReg_32_XM0RegClassID)		// Has a hack getRegClassForSizeOnBank uses exactly SGPR_32RegClass, which
		// won't ever beconstrained any further.
		if (RC != &AMDGPU::SGPR_32RegClass)
return false;		return false;
const LLT Ty = MRI.getType(Reg);		const LLT Ty = MRI.getType(Reg);
return Ty.isValid() && Ty.getSizeInBits() == 1;		return Ty.isValid() && Ty.getSizeInBits() == 1;
}		}

const RegisterBank RB = RegClassOrBank.get<const RegisterBank >();		const RegisterBank RB = RegClassOrBank.get<const RegisterBank >();
return RB->getID() == AMDGPU::SCCRegBankID;		return RB->getID() == AMDGPU::SCCRegBankID;
}		}
▲ Show 20 Lines • Show All 531 Lines • ▼ Show 20 Lines	BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::SI_IF_BREAK))
.add(I.getOperand(3));		.add(I.getOperand(3));

Register DstReg = I.getOperand(0).getReg();		Register DstReg = I.getOperand(0).getReg();
Register Src0Reg = I.getOperand(2).getReg();		Register Src0Reg = I.getOperand(2).getReg();
Register Src1Reg = I.getOperand(3).getReg();		Register Src1Reg = I.getOperand(3).getReg();

I.eraseFromParent();		I.eraseFromParent();

for (Register Reg : { DstReg, Src0Reg, Src1Reg }) {		for (Register Reg : { DstReg, Src0Reg, Src1Reg })
if (!MRI->getRegClassOrNull(Reg))
MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());		MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
}

return true;		return true;
}		}
default:		default:
return selectImpl(I, *CoverageInfo);		return selectImpl(I, *CoverageInfo);
}		}
}		}

▲ Show 20 Lines • Show All 793 Lines • ▼ Show 20 Lines	bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
APInt Imm(Size, I.getOperand(1).getImm());		APInt Imm(Size, I.getOperand(1).getImm());

MachineInstr *ResInst;		MachineInstr *ResInst;
if (IsSgpr && TII.isInlineConstant(Imm)) {		if (IsSgpr && TII.isInlineConstant(Imm)) {
ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B64), DstReg)		ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B64), DstReg)
.addImm(I.getOperand(1).getImm());		.addImm(I.getOperand(1).getImm());
} else {		} else {
const TargetRegisterClass *RC = IsSgpr ?		const TargetRegisterClass *RC = IsSgpr ?
&AMDGPU::SReg_32_XM0RegClass : &AMDGPU::VGPR_32RegClass;		&AMDGPU::SReg_32RegClass : &AMDGPU::VGPR_32RegClass;
Register LoReg = MRI->createVirtualRegister(RC);		Register LoReg = MRI->createVirtualRegister(RC);
Register HiReg = MRI->createVirtualRegister(RC);		Register HiReg = MRI->createVirtualRegister(RC);

BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)		BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
.addImm(Imm.trunc(32).getZExtValue());		.addImm(Imm.trunc(32).getZExtValue());

BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)		BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)
.addImm(Imm.ashr(32).getZExtValue());		.addImm(Imm.ashr(32).getZExtValue());
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines	bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
// In SelectionDAG, we inspect the IR block for uniformity metadata to decide		// In SelectionDAG, we inspect the IR block for uniformity metadata to decide
// whether the branch is uniform when selecting the instruction. In		// whether the branch is uniform when selecting the instruction. In
// GlobalISel, we should push that decision into RegBankSelect. Assume for now		// GlobalISel, we should push that decision into RegBankSelect. Assume for now
// RegBankSelect knows what it's doing if the branch condition is scc, even		// RegBankSelect knows what it's doing if the branch condition is scc, even
// though it currently does not.		// though it currently does not.
if (isSCC(CondReg, *MRI)) {		if (isSCC(CondReg, *MRI)) {
CondPhysReg = AMDGPU::SCC;		CondPhysReg = AMDGPU::SCC;
BrOpcode = AMDGPU::S_CBRANCH_SCC1;		BrOpcode = AMDGPU::S_CBRANCH_SCC1;
ConstrainRC = &AMDGPU::SReg_32_XM0RegClass;		// FIXME: Hack for isSCC tests
		ConstrainRC = &AMDGPU::SGPR_32RegClass;
} else if (isVCC(CondReg, *MRI)) {		} else if (isVCC(CondReg, *MRI)) {
// FIXME: Do we have to insert an and with exec here, like in SelectionDAG?		// FIXME: Do we have to insert an and with exec here, like in SelectionDAG?
// We sort of know that a VCC producer based on the register bank, that ands		// We sort of know that a VCC producer based on the register bank, that ands
// inactive lanes with 0. What if there was a logical operation with vcc		// inactive lanes with 0. What if there was a logical operation with vcc
// producers in different blocks/with different exec masks?		// producers in different blocks/with different exec masks?
// FIXME: Should scc->vcc copies and with exec?		// FIXME: Should scc->vcc copies and with exec?
CondPhysReg = TRI.getVCC();		CondPhysReg = TRI.getVCC();
BrOpcode = AMDGPU::S_CBRANCH_VCCNZ;		BrOpcode = AMDGPU::S_CBRANCH_VCCNZ;
▲ Show 20 Lines • Show All 348 Lines • ▼ Show 20 Lines	AMDGPUInstructionSelector::selectSmrdSgpr(MachineOperand &Root) const {
if (!GEPInfo.Imm \|\| !isUInt<32>(GEPInfo.Imm))		if (!GEPInfo.Imm \|\| !isUInt<32>(GEPInfo.Imm))
return None;		return None;

// If we make it this far we have a load with an 32-bit immediate offset.		// If we make it this far we have a load with an 32-bit immediate offset.
// It is OK to select this using a sgpr offset, because we have already		// It is OK to select this using a sgpr offset, because we have already
// failed trying to select this load into one of the _IMM variants since		// failed trying to select this load into one of the _IMM variants since
// the _IMM Patterns are considered before the _SGPR patterns.		// the _IMM Patterns are considered before the _SGPR patterns.
unsigned PtrReg = GEPInfo.SgprParts[0];		unsigned PtrReg = GEPInfo.SgprParts[0];
Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);		Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)		BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
.addImm(GEPInfo.Imm);		.addImm(GEPInfo.Imm);
return {{		return {{
[=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },		[=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
[=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); }		[=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); }
}};		}};
}		}

▲ Show 20 Lines • Show All 236 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines

SITargetLowering::SITargetLowering(const TargetMachine &TM,		SITargetLowering::SITargetLowering(const TargetMachine &TM,
const GCNSubtarget &STI)		const GCNSubtarget &STI)
: AMDGPUTargetLowering(TM, STI),		: AMDGPUTargetLowering(TM, STI),
Subtarget(&STI) {		Subtarget(&STI) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);		addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);		addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);

addRegisterClass(MVT::i32, &AMDGPU::SReg_32_XM0RegClass);		addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);		addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);

addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);		addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);		addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);		addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);

addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);		addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);		addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
Show All 9 Lines	SITargetLowering::SITargetLowering(const TargetMachine &TM,

addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);		addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);		addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);

addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);		addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);		addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);

if (Subtarget->has16BitInsts()) {		if (Subtarget->has16BitInsts()) {
addRegisterClass(MVT::i16, &AMDGPU::SReg_32_XM0RegClass);		addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
addRegisterClass(MVT::f16, &AMDGPU::SReg_32_XM0RegClass);		addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);

// Unless there are also VOP3P operations, not operations are really legal.		// Unless there are also VOP3P operations, not operations are really legal.
addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32_XM0RegClass);		addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32_XM0RegClass);		addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);		addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);		addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
}		}

if (Subtarget->hasMAIInsts()) {		if (Subtarget->hasMAIInsts()) {
addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);		addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);		addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
}		}
▲ Show 20 Lines • Show All 1,658 Lines • ▼ Show 20 Lines
// Allocate special input registers that are initialized per-wave.		// Allocate special input registers that are initialized per-wave.
void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,		void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
MachineFunction &MF,		MachineFunction &MF,
SIMachineFunctionInfo &Info,		SIMachineFunctionInfo &Info,
CallingConv::ID CallConv,		CallingConv::ID CallConv,
bool IsShader) const {		bool IsShader) const {
if (Info.hasWorkGroupIDX()) {		if (Info.hasWorkGroupIDX()) {
unsigned Reg = Info.addWorkGroupIDX();		unsigned Reg = Info.addWorkGroupIDX();
MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);		MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
CCInfo.AllocateReg(Reg);		CCInfo.AllocateReg(Reg);
}		}

if (Info.hasWorkGroupIDY()) {		if (Info.hasWorkGroupIDY()) {
unsigned Reg = Info.addWorkGroupIDY();		unsigned Reg = Info.addWorkGroupIDY();
MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);		MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
CCInfo.AllocateReg(Reg);		CCInfo.AllocateReg(Reg);
}		}

if (Info.hasWorkGroupIDZ()) {		if (Info.hasWorkGroupIDZ()) {
unsigned Reg = Info.addWorkGroupIDZ();		unsigned Reg = Info.addWorkGroupIDZ();
MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);		MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
CCInfo.AllocateReg(Reg);		CCInfo.AllocateReg(Reg);
}		}

if (Info.hasWorkGroupInfo()) {		if (Info.hasWorkGroupInfo()) {
unsigned Reg = Info.addWorkGroupInfo();		unsigned Reg = Info.addWorkGroupInfo();
MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);		MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
CCInfo.AllocateReg(Reg);		CCInfo.AllocateReg(Reg);
}		}

if (Info.hasPrivateSegmentWaveByteOffset()) {		if (Info.hasPrivateSegmentWaveByteOffset()) {
// Scratch wave offset passed in system SGPR.		// Scratch wave offset passed in system SGPR.
unsigned PrivateSegmentWaveByteOffsetReg;		unsigned PrivateSegmentWaveByteOffsetReg;

if (IsShader) {		if (IsShader) {
▲ Show 20 Lines • Show All 1,743 Lines • ▼ Show 20 Lines	case AMDGPU::S_SUB_U64_PSEUDO: {
const SIRegisterInfo *TRI = ST.getRegisterInfo();		const SIRegisterInfo *TRI = ST.getRegisterInfo();
const TargetRegisterClass *BoolRC = TRI->getBoolRC();		const TargetRegisterClass *BoolRC = TRI->getBoolRC();
const DebugLoc &DL = MI.getDebugLoc();		const DebugLoc &DL = MI.getDebugLoc();

MachineOperand &Dest = MI.getOperand(0);		MachineOperand &Dest = MI.getOperand(0);
MachineOperand &Src0 = MI.getOperand(1);		MachineOperand &Src0 = MI.getOperand(1);
MachineOperand &Src1 = MI.getOperand(2);		MachineOperand &Src1 = MI.getOperand(2);

Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);		Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);		Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);

MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,		MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
Src0, BoolRC, AMDGPU::sub0,		Src0, BoolRC, AMDGPU::sub0,
&AMDGPU::SReg_32_XM0RegClass);		&AMDGPU::SReg_32RegClass);
MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,		MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
Src0, BoolRC, AMDGPU::sub1,		Src0, BoolRC, AMDGPU::sub1,
&AMDGPU::SReg_32_XM0RegClass);		&AMDGPU::SReg_32RegClass);

MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,		MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
Src1, BoolRC, AMDGPU::sub0,		Src1, BoolRC, AMDGPU::sub0,
&AMDGPU::SReg_32_XM0RegClass);		&AMDGPU::SReg_32RegClass);
MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,		MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
Src1, BoolRC, AMDGPU::sub1,		Src1, BoolRC, AMDGPU::sub1,
&AMDGPU::SReg_32_XM0RegClass);		&AMDGPU::SReg_32RegClass);

bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);		bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);

unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;		unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;		unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)		BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
.add(Src0Sub0)		.add(Src0Sub0)
.add(Src1Sub0);		.add(Src1Sub0);
▲ Show 20 Lines • Show All 6,927 Lines • ▼ Show 20 Lines	default:
return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);		return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
case 's':		case 's':
case 'r':		case 'r':
switch (VT.getSizeInBits()) {		switch (VT.getSizeInBits()) {
default:		default:
return std::make_pair(0U, nullptr);		return std::make_pair(0U, nullptr);
case 32:		case 32:
case 16:		case 16:
RC = &AMDGPU::SReg_32_XM0RegClass;		RC = &AMDGPU::SReg_32RegClass;
break;		break;
case 64:		case 64:
RC = &AMDGPU::SGPR_64RegClass;		RC = &AMDGPU::SGPR_64RegClass;
break;		break;
case 96:		case 96:
RC = &AMDGPU::SReg_96RegClass;		RC = &AMDGPU::SReg_96RegClass;
break;		break;
case 128:		case 128:
▲ Show 20 Lines • Show All 377 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 5,101 Lines • ▼ Show 20 Lines	if (ST.hasDLInsts()) {
// invert either source and then perform the XOR. If either source is a		// invert either source and then perform the XOR. If either source is a
// scalar register, then we can leave the inversion on the scalar unit to		// scalar register, then we can leave the inversion on the scalar unit to
// acheive a better distrubution of scalar and vector instructions.		// acheive a better distrubution of scalar and vector instructions.
bool Src0IsSGPR = Src0.isReg() &&		bool Src0IsSGPR = Src0.isReg() &&
RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));		RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
bool Src1IsSGPR = Src1.isReg() &&		bool Src1IsSGPR = Src1.isReg() &&
RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));		RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
MachineInstr *Xor;		MachineInstr *Xor;
Register Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);		Register Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);		Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);

// Build a pair of scalar instructions and add them to the work list.		// Build a pair of scalar instructions and add them to the work list.
// The next iteration over the work list will lower these to the vector		// The next iteration over the work list will lower these to the vector
// unit as necessary.		// unit as necessary.
if (Src0IsSGPR) {		if (Src0IsSGPR) {
BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);		BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)		Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
.addReg(Temp)		.addReg(Temp)
Show All 27 Lines	void SIInstrInfo::splitScalarNotBinop(SetVectorType &Worklist,
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();		MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
MachineBasicBlock::iterator MII = Inst;		MachineBasicBlock::iterator MII = Inst;
const DebugLoc &DL = Inst.getDebugLoc();		const DebugLoc &DL = Inst.getDebugLoc();

MachineOperand &Dest = Inst.getOperand(0);		MachineOperand &Dest = Inst.getOperand(0);
MachineOperand &Src0 = Inst.getOperand(1);		MachineOperand &Src0 = Inst.getOperand(1);
MachineOperand &Src1 = Inst.getOperand(2);		MachineOperand &Src1 = Inst.getOperand(2);

Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);		Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);		Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);

MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm)		MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm)
.add(Src0)		.add(Src0)
.add(Src1);		.add(Src1);

MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)		MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
.addReg(Interm);		.addReg(Interm);

▲ Show 20 Lines • Show All 1,297 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIRegisterInfo.h

Show First 20 Lines • Show All 262 Lines • ▼ Show 20 Lines	getRegClassForTypeOnBank(LLT Ty,
return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank, MRI);		return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank, MRI);
}		}

const TargetRegisterClass *		const TargetRegisterClass *
getConstrainedRegClassForOperand(const MachineOperand &MO,		getConstrainedRegClassForOperand(const MachineOperand &MO,
const MachineRegisterInfo &MRI) const override;		const MachineRegisterInfo &MRI) const override;

const TargetRegisterClass *getBoolRC() const {		const TargetRegisterClass *getBoolRC() const {
return isWave32 ? &AMDGPU::SReg_32_XM0RegClass		return isWave32 ? &AMDGPU::SReg_32RegClass
: &AMDGPU::SReg_64RegClass;		: &AMDGPU::SReg_64RegClass;
}		}

const TargetRegisterClass *getWaveMaskRegClass() const {		const TargetRegisterClass *getWaveMaskRegClass() const {
return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass		return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
: &AMDGPU::SReg_64_XEXECRegClass;		: &AMDGPU::SReg_64_XEXECRegClass;
}		}

Show All 29 Lines

lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 1,940 Lines • ▼ Show 20 Lines	SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
case 1: {		case 1: {
switch (RB.getID()) {		switch (RB.getID()) {
case AMDGPU::VGPRRegBankID:		case AMDGPU::VGPRRegBankID:
return &AMDGPU::VGPR_32RegClass;		return &AMDGPU::VGPR_32RegClass;
case AMDGPU::VCCRegBankID:		case AMDGPU::VCCRegBankID:
return isWave32 ?		return isWave32 ?
&AMDGPU::SReg_32_XM0_XEXECRegClass : &AMDGPU::SReg_64_XEXECRegClass;		&AMDGPU::SReg_32_XM0_XEXECRegClass : &AMDGPU::SReg_64_XEXECRegClass;
case AMDGPU::SGPRRegBankID:		case AMDGPU::SGPRRegBankID:
return &AMDGPU::SReg_32_XM0RegClass;		return &AMDGPU::SReg_32RegClass;
case AMDGPU::SCCRegBankID:		case AMDGPU::SCCRegBankID:
// This needs to return an allocatable class, so don't bother returning		// This needs to return an allocatable class, so don't bother returning
// the dummy SCC class.		// the dummy SCC class.
return &AMDGPU::SReg_32_XM0RegClass;		//
		// FIXME: This is a grotesque hack. We use SGPR_32 as an indication this
		// was not an VCC bank value since we use the larger class SReg_32 for
		// other values. These should all use SReg_32.
		return &AMDGPU::SGPR_32RegClass;
default:		default:
llvm_unreachable("unknown register bank");		llvm_unreachable("unknown register bank");
}		}
}		}
case 32:		case 32:
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
&AMDGPU::SReg_32_XM0RegClass;		&AMDGPU::SReg_32RegClass;
case 64:		case 64:
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :
&AMDGPU::SReg_64_XEXECRegClass;		&AMDGPU::SReg_64_XEXECRegClass;
case 96:		case 96:
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_96RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_96RegClass :
&AMDGPU::SReg_96RegClass;		&AMDGPU::SReg_96RegClass;
case 128:		case 128:
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_128RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_128RegClass :
&AMDGPU::SGPR_128RegClass;		&AMDGPU::SGPR_128RegClass;
case 160:		case 160:
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_160RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_160RegClass :
&AMDGPU::SReg_160RegClass;		&AMDGPU::SReg_160RegClass;
case 256:		case 256:
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_256RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_256RegClass :
&AMDGPU::SReg_256RegClass;		&AMDGPU::SReg_256RegClass;
case 512:		case 512:
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_512RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_512RegClass :
&AMDGPU::SReg_512RegClass;		&AMDGPU::SReg_512RegClass;
case 1024:		case 1024:
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_1024RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_1024RegClass :
&AMDGPU::SReg_1024RegClass;		&AMDGPU::SReg_1024RegClass;
default:		default:
if (Size < 32)		if (Size < 32)
return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :		return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
&AMDGPU::SReg_32_XM0RegClass;		&AMDGPU::SReg_32RegClass;
return nullptr;		return nullptr;
}		}
}		}

const TargetRegisterClass *		const TargetRegisterClass *
SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,		SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
const MachineRegisterInfo &MRI) const {		const MachineRegisterInfo &MRI) const {
const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());		const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

Show All 11 Lines	body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4		liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4


; GFX6-LABEL: name: add_s32		; GFX6-LABEL: name: add_s32
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1		; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc		; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec		; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_U32_]], %7, 0, implicit $exec		; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_U32_]], %7, 0, implicit $exec
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec		; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit %9		; GFX6: S_ENDPGM 0, implicit %9
; GFX9-LABEL: name: add_s32		; GFX9-LABEL: name: add_s32
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1		; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc		; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec		; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_U32_]], [[V_ADD_U32_e64_]], 0, implicit $exec		; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_U32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec		; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_2]]		; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_2]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:vgpr(s32) = COPY $vgpr0		%2:vgpr(s32) = COPY $vgpr0
%3:vgpr(p1) = COPY $vgpr3_vgpr4		%3:vgpr(p1) = COPY $vgpr3_vgpr4
Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=WAVE64 %s		# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=WAVE64 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=WAVE32 %s		# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=WAVE32 %s

---		---
name: class_s32_vcc_sv		name: class_s32_vcc_sv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $vgpr0		liveins: $sgpr0, $vgpr0
; WAVE64-LABEL: name: class_s32_vcc_sv		; WAVE64-LABEL: name: class_s32_vcc_sv
; WAVE64: liveins: $sgpr0, $vgpr0		; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_sv		; WAVE32-LABEL: name: class_s32_vcc_sv
; WAVE32: liveins: $sgpr0, $vgpr0		; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1		%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: class_s32_vcc_vs		name: class_s32_vcc_vs
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $vgpr0		liveins: $sgpr0, $vgpr0
; WAVE64-LABEL: name: class_s32_vcc_vs		; WAVE64-LABEL: name: class_s32_vcc_vs
; WAVE64: liveins: $sgpr0, $vgpr0		; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_vs		; WAVE32-LABEL: name: class_s32_vcc_vs
; WAVE32: liveins: $sgpr0, $vgpr0		; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0		%1:sgpr(s32) = COPY $sgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1		%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
Show All 11 Lines	bb.0:
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_vv		; WAVE32-LABEL: name: class_s32_vcc_vv
; WAVE32: liveins: $vgpr0, $vgpr1		; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1		%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
Show All 11 Lines	bb.0:
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_sv		; WAVE32-LABEL: name: class_s64_vcc_sv
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0		; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1		; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1		%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1		%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: class_s64_vcc_vs		name: class_s64_vcc_vs
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0_sgpr1, $vgpr0		liveins: $sgpr0_sgpr1, $vgpr0

; WAVE64-LABEL: name: class_s64_vcc_vs		; WAVE64-LABEL: name: class_s64_vcc_vs
; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0		; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_vs		; WAVE32-LABEL: name: class_s64_vcc_vs
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0		; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr0		%1:sgpr(s32) = COPY $sgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1		%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
Show All 12 Lines	bb.0:
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_vv		; WAVE32-LABEL: name: class_s64_vcc_vv
; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2		; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = COPY $vgpr2		%1:vgpr(s32) = COPY $vgpr2
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1		%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir

Show All 15 Lines
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $vgpr0		liveins: $sgpr0, $vgpr0
; WAVE32-LABEL: name: class_s16_vcc_sv		; WAVE32-LABEL: name: class_s16_vcc_sv
; WAVE32: liveins: $sgpr0, $vgpr0		; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
; WAVE64-LABEL: name: class_s16_vcc_sv		; WAVE64-LABEL: name: class_s16_vcc_sv
; WAVE64: liveins: $sgpr0, $vgpr0		; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: $vcc_hi = IMPLICIT_DEF		; WAVE64: $vcc_hi = IMPLICIT_DEF
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%2:sgpr(s16) = G_TRUNC %0		%2:sgpr(s16) = G_TRUNC %0
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1		%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...

---		---
name: class_s16_vcc_vs		name: class_s16_vcc_vs
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $vgpr0		liveins: $sgpr0, $vgpr0
; WAVE32-LABEL: name: class_s16_vcc_vs		; WAVE32-LABEL: name: class_s16_vcc_vs
; WAVE32: liveins: $sgpr0, $vgpr0		; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
; WAVE64-LABEL: name: class_s16_vcc_vs		; WAVE64-LABEL: name: class_s16_vcc_vs
; WAVE64: liveins: $sgpr0, $vgpr0		; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: $vcc_hi = IMPLICIT_DEF		; WAVE64: $vcc_hi = IMPLICIT_DEF
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0		%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1		%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...

Show All 12 Lines	bb.0:
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
; WAVE64-LABEL: name: class_s16_vcc_vv		; WAVE64-LABEL: name: class_s16_vcc_vv
; WAVE64: liveins: $vgpr0, $vgpr1		; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: $vcc_hi = IMPLICIT_DEF		; WAVE64: $vcc_hi = IMPLICIT_DEF
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1		%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s

	---			---
	name: cos_s32_vs			name: cos_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: cos_s32_vs			; CHECK-LABEL: name: cos_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_COS_F32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_COS_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir

	Show All 10 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: cos_s16_vs			; CHECK-LABEL: name: cos_s16_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1			%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s

	---			---
	name: cvt_pk_i16_vsv			name: cvt_pk_i16_vsv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: cvt_pk_i16_vsv			; GCN-LABEL: name: cvt_pk_i16_vsv
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: cvt_pk_i16_vvs			name: cvt_pk_i16_vvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: cvt_pk_i16_vvs			; GCN-LABEL: name: cvt_pk_i16_vvs
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s

	---			---
	name: cvt_pk_u16_vsv			name: cvt_pk_u16_vsv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: cvt_pk_u16_vsv			; GCN-LABEL: name: cvt_pk_u16_vsv
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: cvt_pk_u16_vvs			name: cvt_pk_u16_vvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: cvt_pk_u16_vvs			; GCN-LABEL: name: cvt_pk_u16_vvs
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s

	---			---
	name: cvt_pknorm_i16_vsv			name: cvt_pknorm_i16_vsv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: cvt_pknorm_i16_vsv			; GCN-LABEL: name: cvt_pknorm_i16_vsv
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec			; GCN: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.i16), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.i16), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: cvt_pknorm_i16_vvs			name: cvt_pknorm_i16_vvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: cvt_pknorm_i16_vvs			; GCN-LABEL: name: cvt_pknorm_i16_vvs
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec			; GCN: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.i16), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.i16), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s

	---			---
	name: cvt_pknorm_u16_vsv			name: cvt_pknorm_u16_vsv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: cvt_pknorm_u16_vsv			; GCN-LABEL: name: cvt_pknorm_u16_vsv
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec			; GCN: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.u16), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.u16), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: cvt_pknorm_u16_vvs			name: cvt_pknorm_u16_vvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: cvt_pknorm_u16_vvs			; GCN-LABEL: name: cvt_pknorm_u16_vvs
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec			; GCN: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.u16), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.u16), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s

	---			---
	name: cvt_pkrtz_vsv			name: cvt_pkrtz_vsv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: cvt_pkrtz_vsv			; GCN-LABEL: name: cvt_pkrtz_vsv
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: cvt_pkrtz_vvs			name: cvt_pkrtz_vvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: cvt_pkrtz_vvs			; GCN-LABEL: name: cvt_pkrtz_vvs
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1			%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir

	Show All 31 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1			liveins: $sgpr0, $vgpr0, $vgpr1

	; GCN-LABEL: name: fmed3_s32_vsvv			; GCN-LABEL: name: fmed3_s32_vsvv
	; GCN: liveins: $sgpr0, $vgpr0, $vgpr1			; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec			; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]			; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = COPY $vgpr1			%2:vgpr(s32) = COPY $vgpr1
	%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2			%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3
	...			...

	---			---
	name: fmed3_s32_vvsv			name: fmed3_s32_vvsv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1			liveins: $sgpr0, $vgpr0, $vgpr1

	; GCN-LABEL: name: fmed3_s32_vvsv			; GCN-LABEL: name: fmed3_s32_vvsv
	; GCN: liveins: $sgpr0, $vgpr0, $vgpr1			; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec			; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]			; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = COPY $vgpr1			%2:vgpr(s32) = COPY $vgpr1
	%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2			%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3
	...			...

	---			---
	name: fmed3_s32_vvvs			name: fmed3_s32_vvvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1			liveins: $sgpr0, $vgpr0, $vgpr1

	; GCN-LABEL: name: fmed3_s32_vvvs			; GCN-LABEL: name: fmed3_s32_vvvs
	; GCN: liveins: $sgpr0, $vgpr0, $vgpr1			; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec			; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]			; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:sgpr(s32) = COPY $sgpr0			%2:sgpr(s32) = COPY $sgpr0
	%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2			%3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3
	...			...


	# Same SGPR used, so doesn't violate the constant bus restriction.			# Same SGPR used, so doesn't violate the constant bus restriction.
	---			---
	name: fmed3_s32_vssv			name: fmed3_s32_vssv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: fmed3_s32_vssv			; GCN-LABEL: name: fmed3_s32_vssv
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]			; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1			%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: fmed3_s32_vsvs			name: fmed3_s32_vsvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: fmed3_s32_vsvs			; GCN-LABEL: name: fmed3_s32_vsvs
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]			; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0			%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: fmed3_s32_vvss			name: fmed3_s32_vvss
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: fmed3_s32_vvss			; GCN-LABEL: name: fmed3_s32_vvss
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec			; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]			; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0			%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: fmed3_s32_vsss			name: fmed3_s32_vsss
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: fmed3_s32_vsss			; GCN-LABEL: name: fmed3_s32_vsss
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec			; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]			; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...


	Show All 17 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir

	Show All 39 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1			liveins: $sgpr0, $vgpr0, $vgpr1

	; GCN-LABEL: name: fmed3_s16_vsvv			; GCN-LABEL: name: fmed3_s16_vsvv
	; GCN: liveins: $sgpr0, $vgpr0, $vgpr1			; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec			; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]]			; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = COPY $vgpr1			%2:vgpr(s32) = COPY $vgpr1
	%3:sgpr(s16) = G_TRUNC %0			%3:sgpr(s16) = G_TRUNC %0
	%4:vgpr(s16) = G_TRUNC %1			%4:vgpr(s16) = G_TRUNC %1
	%5:vgpr(s16) = G_TRUNC %2			%5:vgpr(s16) = G_TRUNC %2
	%6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5			%6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
	S_ENDPGM 0, implicit %6			S_ENDPGM 0, implicit %6
	...			...

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s

	---			---
	name: fract_s32_vs			name: fract_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: fract_s32_vs			; CHECK-LABEL: name: fract_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir

	Show All 10 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: fract_s16_vs			; CHECK-LABEL: name: fract_s16_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1			%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=GCN %s

	---			---
	name: ldexp_s32_vsv			name: ldexp_s32_vsv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: ldexp_s32_vsv			; GCN-LABEL: name: ldexp_s32_vsv
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1			%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: ldexp_s32_vvs			name: ldexp_s32_vvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: ldexp_s32_vvs			; GCN-LABEL: name: ldexp_s32_vvs
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1			%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $vgpr0			liveins: $sgpr0_sgpr1, $vgpr0
	; GCN-LABEL: name: ldexp_s64_vvs			; GCN-LABEL: name: ldexp_s64_vvs
	; GCN: liveins: $sgpr0_sgpr1, $vgpr0			; GCN: liveins: $sgpr0_sgpr1, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]			; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]
	%0:vgpr(s64) = COPY $vgpr0_vgpr1			%0:vgpr(s64) = COPY $vgpr0_vgpr1
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1			%2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir

	Show All 11 Lines
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: ldexp_s16_vsv			; GCN-LABEL: name: ldexp_s16_vsv
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:sgpr(s16) = G_TRUNC %0			%2:sgpr(s16) = G_TRUNC %0
	%3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1			%3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3
	...			...

	---			---
	name: ldexp_s16_vvs			name: ldexp_s16_vvs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: ldexp_s16_vvs			; GCN-LABEL: name: ldexp_s16_vvs
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s16) = G_TRUNC %0			%2:vgpr(s16) = G_TRUNC %0
	%3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1			%3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3
	...			...
	Show All 22 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir

	Show All 19 Lines
	name: mbcnt_lo_sv			name: mbcnt_lo_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: mbcnt_lo_sv			; GCN-LABEL: name: mbcnt_lo_sv
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1			%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: smin_s32_vs			name: smin_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: smin_s32_vs			; GCN-LABEL: name: smin_s32_vs
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1			%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir

	Show All 13 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: rcp_legacy_s32_vs			; CHECK-LABEL: name: rcp_legacy_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_RCP_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_RCP_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_RCP_LEGACY_F32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_RCP_LEGACY_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s

	---			---
	name: rcp_s32_vs			name: rcp_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: rcp_s32_vs			; CHECK-LABEL: name: rcp_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir

	Show All 10 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: rcp_s16_vs			; CHECK-LABEL: name: rcp_s16_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1			%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir

	Show All 13 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: rsq_clamp_s32_vs			; CHECK-LABEL: name: rsq_clamp_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_RSQ_CLAMP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_RSQ_CLAMP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_RSQ_CLAMP_F32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_RSQ_CLAMP_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir

	Show All 13 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: rsq_legacy_s32_vs			; CHECK-LABEL: name: rsq_legacy_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_RSQ_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_RSQ_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_RSQ_LEGACY_F32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_RSQ_LEGACY_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s

	---			---
	name: rsq_s32_vs			name: rsq_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: rsq_s32_vs			; CHECK-LABEL: name: rsq_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir

	Show All 10 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: rsq_s16_vs			; CHECK-LABEL: name: rsq_s16_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1			%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s -check-prefix=GCN			# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s -check-prefix=GCN

	---			---
	name: test_sendmsg			name: test_sendmsg
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; GCN-LABEL: name: test_sendmsg			; GCN-LABEL: name: test_sendmsg
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: $m0 = COPY [[COPY]]			; GCN: $m0 = COPY [[COPY]]
	; GCN: S_SENDMSG 1, implicit $exec, implicit $m0			; GCN: S_SENDMSG 1, implicit $exec, implicit $m0
	; GCN: S_ENDPGM 0			; GCN: S_ENDPGM 0
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.sendmsg), 1, %0(s32)			G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.sendmsg), 1, %0(s32)
	S_ENDPGM 0			S_ENDPGM 0

	...			...

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir

	Show All 27 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: sffbh_s32_vs			; CHECK-LABEL: name: sffbh_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_FFBH_I32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_I32_e64 [[COPY]], implicit $exec			; CHECK: [[V_FFBH_I32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_I32_e64 [[COPY]], implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_FFBH_I32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_FFBH_I32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sffbh), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sffbh), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s

	---			---
	name: sin_s32_vs			name: sin_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: sin_s32_vs			; CHECK-LABEL: name: sin_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0			%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir

	Show All 10 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: sin_s16_vs			; CHECK-LABEL: name: sin_s16_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1			%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir

	Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ffbh_u32_v_s			; CHECK-LABEL: name: ffbh_u32_v_s
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec			; CHECK: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0			%1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1

	...			...

test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir

Show All 22 Lines	bb.0:
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]		; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
; WAVE32-LABEL: name: and_s1_vcc_vcc_vcc		; WAVE32-LABEL: name: and_s1_vcc_vcc_vcc
; WAVE32: liveins: $vgpr0, $vgpr1		; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec		; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec		; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec		; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]		; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_CONSTANT i32 0		%2:vgpr(s32) = G_CONSTANT i32 0
%3:vcc(s1) = G_ICMP intpred(eq), %0, %2		%3:vcc(s1) = G_ICMP intpred(eq), %0, %2
%4:vcc(s1) = G_ICMP intpred(eq), %1, %2		%4:vcc(s1) = G_ICMP intpred(eq), %1, %2
%5:vcc(s1) = G_AND %3, %4		%5:vcc(s1) = G_AND %3, %4
S_ENDPGM 0, implicit %5		S_ENDPGM 0, implicit %5
...		...

---		---

name: and_s1_sgpr_sgpr_sgpr		name: and_s1_sgpr_sgpr_sgpr
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1		liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: and_s1_sgpr_sgpr_sgpr		; WAVE64-LABEL: name: and_s1_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1		; WAVE64: liveins: $sgpr0, $sgpr1
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]]		; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]		; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
; WAVE32-LABEL: name: and_s1_sgpr_sgpr_sgpr		; WAVE32-LABEL: name: and_s1_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1		; WAVE32: liveins: $sgpr0, $sgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]]		; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s1) = G_TRUNC %0		%2:sgpr(s1) = G_TRUNC %0
%3:sgpr(s1) = G_TRUNC %1		%3:sgpr(s1) = G_TRUNC %1
%4:sgpr(s1) = G_AND %2, %3		%4:sgpr(s1) = G_AND %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
Show All 40 Lines
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1		liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: and_s16_sgpr_sgpr_sgpr		; WAVE64-LABEL: name: and_s16_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1		; WAVE64: liveins: $sgpr0, $sgpr1
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]]		; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]		; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
; WAVE32-LABEL: name: and_s16_sgpr_sgpr_sgpr		; WAVE32-LABEL: name: and_s16_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1		; WAVE32: liveins: $sgpr0, $sgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]]		; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s16) = G_TRUNC %0		%2:sgpr(s16) = G_TRUNC %0
%3:sgpr(s16) = G_TRUNC %1		%3:sgpr(s16) = G_TRUNC %1
%4:sgpr(s16) = G_AND %2, %3		%4:sgpr(s16) = G_AND %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Lines

body: \|		body: \|
bb.0:		bb.0:
; WAVE64-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc		; WAVE64-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 undef %1:sreg_64, undef %2:sreg_64		; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 undef %1:sreg_64, undef %2:sreg_64
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
; WAVE32-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc		; WAVE32-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0		; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 undef %1:sreg_32, undef %2:sreg_32
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
%2:vcc(s1) = G_AND undef %0:vcc(s1), undef %1:vcc(s1)		%2:vcc(s1) = G_AND undef %0:vcc(s1), undef %1:vcc(s1)
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---

name: and_s1_sgpr_undef_sgpr_undef_sgpr		name: and_s1_sgpr_undef_sgpr_undef_sgpr
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines	bb.0:
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc		; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc
; WAVE32: liveins: $vgpr0, $vgpr1		; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s1) = G_TRUNC %0		%2:vgpr(s1) = G_TRUNC %0
%3:vgpr(s1) = G_TRUNC %1		%3:vgpr(s1) = G_TRUNC %1
%4:vcc(s1) = COPY %2		%4:vcc(s1) = COPY %2
%5:vcc(s1) = COPY %3		%5:vcc(s1) = COPY %3
%6:vcc(s1) = G_AND %4, %5		%6:vcc(s1) = G_AND %4, %5
Show All 11 Lines
tracksRegLiveness: true		tracksRegLiveness: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0

; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32		; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE64: liveins: $vgpr0		; WAVE64: liveins: $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; WAVE64: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]]		; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]]
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY2]]		; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_]]
; WAVE64: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_]]		; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY2]]
; WAVE64: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY3]]		; WAVE64: S_ENDPGM 0, implicit [[COPY3]]
; WAVE64: S_ENDPGM 0, implicit [[COPY4]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32		; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE32: liveins: $vgpr0		; WAVE32: liveins: $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
		; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)		%0:vgpr(s1) = G_TRUNC %1(s32)
%2:sgpr(s1) = G_CONSTANT i1 true		%2:sgpr(s1) = G_CONSTANT i1 true
%6:sgpr(s32) = G_CONSTANT i32 0		%6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF		%7:sgpr(p1) = G_IMPLICIT_DEF
%9:vcc(s1) = COPY %0(s1)		%9:vcc(s1) = COPY %0(s1)
%10:vcc(s1) = COPY %2(s1)		%10:vcc(s1) = COPY %2(s1)
%8:vcc(s1) = G_AND %9, %10		%8:vcc(s1) = G_AND %9, %10
Show All 10 Lines
tracksRegLiveness: true		tracksRegLiveness: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0

; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64		; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE64: liveins: $vgpr0		; WAVE64: liveins: $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B64_]]		; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]		; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64		; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE32: liveins: $vgpr0		; WAVE32: liveins: $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]]		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[COPY1]], [[COPY2]]		; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_]]		; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_]]
; WAVE32: S_ENDPGM 0, implicit [[COPY3]]		; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)		%0:vgpr(s1) = G_TRUNC %1(s32)
%2:sgpr(s1) = G_CONSTANT i1 true		%2:sgpr(s1) = G_CONSTANT i1 true
%6:sgpr(s32) = G_CONSTANT i32 0		%6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF		%7:sgpr(p1) = G_IMPLICIT_DEF
%9:vcc(s1) = COPY %0(s1)		%9:vcc(s1) = COPY %0(s1)
%10:vcc(s1) = COPY %2(s1)		%10:vcc(s1) = COPY %2(s1)
%8:vcc(s1) = G_AND %9, %10		%8:vcc(s1) = G_AND %9, %10
Show All 33 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir

Show All 9 Lines	body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: anyext_scc_s1_to_sgpr_s32		; GCN-LABEL: name: anyext_scc_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; GCN: $scc = COPY [[COPY1]]		; GCN: $scc = COPY [[COPY1]]
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 1, implicit $scc		; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]		; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:scc(s1) = G_ICMP intpred(eq), %0, %0		%1:scc(s1) = G_ICMP intpred(eq), %0, %0
%2:sgpr(s32) = G_ANYEXT %1		%2:sgpr(s32) = G_ANYEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---
Show All 23 Lines
name: anyext_sgpr_s1_to_sgpr_s32		name: anyext_sgpr_s1_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32		; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: $sgpr0 = COPY [[COPY]]		; GCN: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0		%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1		%2:sgpr(s32) = G_ANYEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---

name: anyext_sgpr_s1_to_sgpr_s64		name: anyext_sgpr_s1_to_sgpr_s64
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64		; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]		; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]		; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0		%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s64) = G_ANYEXT %1		%2:sgpr(s64) = G_ANYEXT %1
$sgpr0_sgpr1 = COPY %2		$sgpr0_sgpr1 = COPY %2
...		...

---		---

name: anyext_sgpr_s8_to_sgpr_s32		name: anyext_sgpr_s8_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: anyext_sgpr_s8_to_sgpr_s32		; GCN-LABEL: name: anyext_sgpr_s8_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: $sgpr0 = COPY [[COPY]]		; GCN: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s8) = G_TRUNC %0		%1:sgpr(s8) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1		%2:sgpr(s32) = G_ANYEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2

...		...

---		---

name: anyext_sgpr_s16_to_sgpr_s32		name: anyext_sgpr_s16_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32		; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: $sgpr0 = COPY [[COPY]]		; GCN: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1		%2:sgpr(s32) = G_ANYEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2

...		...

---		---

name: anyext_sgpr_s16_to_sgpr_s64		name: anyext_sgpr_s16_to_sgpr_s64
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64		; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]		; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]		; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_ANYEXT %1		%2:sgpr(s64) = G_ANYEXT %1
$sgpr0_sgpr1 = COPY %2		$sgpr0_sgpr1 = COPY %2

...		...
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir

	Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	name: ashr_s32_sv			name: ashr_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX6-LABEL: name: ashr_s32_sv			; GFX6-LABEL: name: ashr_s32_sv
	; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX6: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	; GFX7-LABEL: name: ashr_s32_sv			; GFX7-LABEL: name: ashr_s32_sv
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX7: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	; GFX8-LABEL: name: ashr_s32_sv			; GFX8-LABEL: name: ashr_s32_sv
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	; GFX9-LABEL: name: ashr_s32_sv			; GFX9-LABEL: name: ashr_s32_sv
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	; GFX10-LABEL: name: ashr_s32_sv			; GFX10-LABEL: name: ashr_s32_sv
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_ASHR %0, %1			%2:vgpr(s32) = G_ASHR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: ashr_s32_vs			name: ashr_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX6-LABEL: name: ashr_s32_vs			; GFX6-LABEL: name: ashr_s32_vs
	; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX6: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	; GFX7-LABEL: name: ashr_s32_vs			; GFX7-LABEL: name: ashr_s32_vs
	; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX7: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	; GFX8-LABEL: name: ashr_s32_vs			; GFX8-LABEL: name: ashr_s32_vs
	; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	; GFX9-LABEL: name: ashr_s32_vs			; GFX9-LABEL: name: ashr_s32_vs
	; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	; GFX10-LABEL: name: ashr_s32_vs			; GFX10-LABEL: name: ashr_s32_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_ASHR %0, %1			%2:vgpr(s32) = G_ASHR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0_vgpr1			liveins: $sgpr0, $vgpr0_vgpr1
	; GFX6-LABEL: name: ashr_s64_vs			; GFX6-LABEL: name: ashr_s64_vs
	; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec			; GFX6: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_ASHR_I64_]]			; GFX6: S_ENDPGM 0, implicit [[V_ASHR_I64_]]
	; GFX7-LABEL: name: ashr_s64_vs			; GFX7-LABEL: name: ashr_s64_vs
	; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec			; GFX7: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_ASHR_I64_]]			; GFX7: S_ENDPGM 0, implicit [[V_ASHR_I64_]]
	; GFX8-LABEL: name: ashr_s64_vs			; GFX8-LABEL: name: ashr_s64_vs
	; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]			; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
	; GFX9-LABEL: name: ashr_s64_vs			; GFX9-LABEL: name: ashr_s64_vs
	; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]			; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
	; GFX10-LABEL: name: ashr_s64_vs			; GFX10-LABEL: name: ashr_s64_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec			; GFX10: [[V_ASHR_I64_:%[0-9]+]]:vreg_64 = V_ASHR_I64 [[COPY]], [[COPY1]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_ASHR_I64_]]			; GFX10: S_ENDPGM 0, implicit [[V_ASHR_I64_]]
	%0:vgpr(s64) = COPY $vgpr0_vgpr1			%0:vgpr(s64) = COPY $vgpr0_vgpr1
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s64) = G_ASHR %0, %1			%2:vgpr(s64) = G_ASHR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 39 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir

	Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX8-LABEL: name: ashr_s16_s16_vs			; GFX8-LABEL: name: ashr_s16_s16_vs
	; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
	; GFX9-LABEL: name: ashr_s16_s16_vs			; GFX9-LABEL: name: ashr_s16_s16_vs
	; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
	; GFX10-LABEL: name: ashr_s16_s16_vs			; GFX10-LABEL: name: ashr_s16_s16_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s16) = G_TRUNC %0			%2:vgpr(s16) = G_TRUNC %0
	%3:sgpr(s16) = G_TRUNC %1			%3:sgpr(s16) = G_TRUNC %1
	%4:vgpr(s16) = G_ASHR %2, %3			%4:vgpr(s16) = G_ASHR %2, %3
	S_ENDPGM 0, implicit %4			S_ENDPGM 0, implicit %4
	▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
	name: ashr_s16_s16_sv			name: ashr_s16_s16_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX8-LABEL: name: ashr_s16_s16_sv			; GFX8-LABEL: name: ashr_s16_s16_sv
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
	; GFX9-LABEL: name: ashr_s16_s16_sv			; GFX9-LABEL: name: ashr_s16_s16_sv
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
	; GFX10-LABEL: name: ashr_s16_s16_sv			; GFX10-LABEL: name: ashr_s16_s16_sv
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:sgpr(s16) = G_TRUNC %0			%2:sgpr(s16) = G_TRUNC %0
	%3:vgpr(s16) = G_TRUNC %1			%3:vgpr(s16) = G_TRUNC %1
	%4:vgpr(s16) = G_ASHR %2, %3			%4:vgpr(s16) = G_ASHR %2, %3
	Show All 35 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir

	Show All 38 Lines
	name: bitreverse_i32_vs			name: bitreverse_i32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0
	; CHECK-LABEL: name: bitreverse_i32_vs			; CHECK-LABEL: name: bitreverse_i32_vs
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec			; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_BITREVERSE %0			%1:vgpr(s32) = G_BITREVERSE %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir

	Show All 14 Lines

	body: \|			body: \|
	; GCN-LABEL: name: brcond_scc			; GCN-LABEL: name: brcond_scc
	; GCN: bb.0:			; GCN: bb.0:
	; GCN: successors: %bb.1(0x80000000)			; GCN: successors: %bb.1(0x80000000)
	; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GCN: $scc = COPY [[COPY2]]			; GCN: $scc = COPY [[COPY2]]
	; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc			; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
	; GCN: bb.1:			; GCN: bb.1:
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1

	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = COPY $sgpr1			%1:sgpr(s32) = COPY $sgpr1
	Show All 9 Lines
	name: brcond_scc_impdef			name: brcond_scc_impdef
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	; GCN-LABEL: name: brcond_scc_impdef			; GCN-LABEL: name: brcond_scc_impdef
	; GCN: bb.0:			; GCN: bb.0:
	; GCN: successors: %bb.1(0x80000000)			; GCN: successors: %bb.1(0x80000000)
	; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF			; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
	; GCN: $scc = COPY [[DEF]]			; GCN: $scc = COPY [[DEF]]
	; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc			; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
	; GCN: bb.1:			; GCN: bb.1:
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1

	%0:scc(s1) = G_IMPLICIT_DEF			%0:scc(s1) = G_IMPLICIT_DEF
	G_BRCOND %0, %bb.1			G_BRCOND %0, %bb.1

	bb.1:			bb.1:

	...			...

	---			---

	name: brcond_scc_undef			name: brcond_scc_undef
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	; GCN-LABEL: name: brcond_scc_undef			; GCN-LABEL: name: brcond_scc_undef
	; GCN: bb.0:			; GCN: bb.0:
	; GCN: successors: %bb.1(0x80000000)			; GCN: successors: %bb.1(0x80000000)
	; GCN: $scc = COPY %0:sreg_32_xm0			; GCN: $scc = COPY %0:sgpr_32
	; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc			; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
	; GCN: bb.1:			; GCN: bb.1:
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1

	G_BRCOND undef %0:scc(s1), %bb.1			G_BRCOND undef %0:scc(s1), %bb.1

	bb.1:			bb.1:

	...			...

	---			---

	name: brcond_scc_br			name: brcond_scc_br
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	; GCN-LABEL: name: brcond_scc_br			; GCN-LABEL: name: brcond_scc_br
	; GCN: bb.0:			; GCN: bb.0:
	; GCN: successors: %bb.1(0x80000000)			; GCN: successors: %bb.1(0x80000000)
	; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GCN: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GCN: $scc = COPY [[COPY2]]			; GCN: $scc = COPY [[COPY2]]
	; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc			; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
	; GCN: S_BRANCH %bb.1			; GCN: S_BRANCH %bb.1
	; GCN: bb.1:			; GCN: bb.1:
	; GCN: successors: %bb.2(0x80000000)			; GCN: successors: %bb.2(0x80000000)
	; GCN: bb.2:			; GCN: bb.2:
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1
	▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir

	Show All 29 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: test_build_vector_v_v2s32_s_s32_v_s32			; GCN-LABEL: name: test_build_vector_v_v2s32_s_s32_v_s32
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1			%2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_build_vector_v_v2s32_v_s32_s_s32			name: test_build_vector_v_v2s32_v_s32_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_s_s32			; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_s_s32
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1			%2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_build_vector_s_v2s32_s_s32_s_s32			name: test_build_vector_s_v2s32_s_s32_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1

	; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_s_s32			; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_s_s32
	; GCN: liveins: $sgpr0, $sgpr1			; GCN: liveins: $sgpr0, $sgpr1
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = COPY $sgpr1			%1:sgpr(s32) = COPY $sgpr1
	%2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1			%2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_build_vector_s_v2s32_undef_s_s32_s_s32			name: test_build_vector_s_v2s32_undef_s_s32_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; GCN-LABEL: name: test_build_vector_s_v2s32_undef_s_s32_s_s32			; GCN-LABEL: name: test_build_vector_s_v2s32_undef_s_s32_s_s32
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE undef %2:sreg_32_xm0, %subreg.sub0, [[COPY]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE undef %2:sreg_32, %subreg.sub0, [[COPY]], %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:sgpr(<2 x s32>) = G_BUILD_VECTOR undef %0:sgpr(s32), %1			%2:sgpr(<2 x s32>) = G_BUILD_VECTOR undef %0:sgpr(s32), %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_build_vector_s_v2s32_s_s32_undef_s_s32			name: test_build_vector_s_v2s32_s_s32_undef_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_undef_s_s32			; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_undef_s_s32
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32_xm0, %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32, %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, undef %1:sgpr(s32),			%2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, undef %1:sgpr(s32),
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_build_vector_s_v2s64_s_s64_s_s64			name: test_build_vector_s_v2s64_s_s64_s_s64
	Show All 19 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir

	Show All 32 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: test_concat_vectors_v_v4s16_s_v2s16_v_v2s16			; GCN-LABEL: name: test_concat_vectors_v_v4s16_s_v2s16_v_v2s16
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]			; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
	%0:sgpr(<2 x s16>) = COPY $sgpr0			%0:sgpr(<2 x s16>) = COPY $sgpr0
	%1:vgpr(<2 x s16>) = COPY $vgpr1			%1:vgpr(<2 x s16>) = COPY $vgpr1
	%2:vgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1			%2:vgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1
	$vgpr0_vgpr1 = COPY %2			$vgpr0_vgpr1 = COPY %2
	...			...

	---			---
	name: test_concat_vectors_v_v4s16_v_v2s16_s_v2s16			name: test_concat_vectors_v_v4s16_v_v2s16_s_v2s16
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: test_concat_vectors_v_v4s16_v_v2s16_s_v2s16			; GCN-LABEL: name: test_concat_vectors_v_v4s16_v_v2s16_s_v2s16
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]			; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
	%0:vgpr(<2 x s16>) = COPY $vgpr0			%0:vgpr(<2 x s16>) = COPY $vgpr0
	%1:sgpr(<2 x s16>) = COPY $sgpr0			%1:sgpr(<2 x s16>) = COPY $sgpr0
	%2:vgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1			%2:vgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1
	$vgpr0_vgpr1 = COPY %2			$vgpr0_vgpr1 = COPY %2
	...			...

	---			---
	name: test_concat_vectors_s_v4s16_s_v2s16_s_v2s16			name: test_concat_vectors_s_v4s16_s_v2s16_s_v2s16
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1

	; GCN-LABEL: name: test_concat_vectors_s_v4s16_s_v2s16_s_v2s16			; GCN-LABEL: name: test_concat_vectors_s_v4s16_s_v2s16_s_v2s16
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]			; GCN: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
	%0:sgpr(<2 x s16>) = COPY $sgpr0			%0:sgpr(<2 x s16>) = COPY $sgpr0
	%1:sgpr(<2 x s16>) = COPY $sgpr1			%1:sgpr(<2 x s16>) = COPY $sgpr1
	%2:sgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1			%2:sgpr(<4 x s16>) = G_CONCAT_VECTORS %0, %1
	$sgpr0_sgpr1 = COPY %2			$sgpr0_sgpr1 = COPY %2
	...			...

	---			---
	name: test_concat_vectors_s_s96_s_v2s16_s_v2s16_s_v2s16			name: test_concat_vectors_s_s96_s_v2s16_s_v2s16_s_v2s16
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $sgpr2			liveins: $sgpr0, $sgpr1, $sgpr2

	; GCN-LABEL: name: test_concat_vectors_s_s96_s_v2s16_s_v2s16_s_v2s16			; GCN-LABEL: name: test_concat_vectors_s_s96_s_v2s16_s_v2s16_s_v2s16
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
	; GCN: $sgpr0_sgpr1_sgpr2 = COPY [[REG_SEQUENCE]]			; GCN: $sgpr0_sgpr1_sgpr2 = COPY [[REG_SEQUENCE]]
	%0:sgpr(<2 x s16>) = COPY $sgpr0			%0:sgpr(<2 x s16>) = COPY $sgpr0
	%1:sgpr(<2 x s16>) = COPY $sgpr1			%1:sgpr(<2 x s16>) = COPY $sgpr1
	%2:sgpr(<2 x s16>) = COPY $sgpr2			%2:sgpr(<2 x s16>) = COPY $sgpr2
	%3:sgpr(<6 x s16>) = G_CONCAT_VECTORS %0, %1, %2			%3:sgpr(<6 x s16>) = G_CONCAT_VECTORS %0, %1, %2
	$sgpr0_sgpr1_sgpr2 = COPY %3			$sgpr0_sgpr1_sgpr2 = COPY %3
	...			...
	Show All 25 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3			liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

	; GCN-LABEL: name: test_concat_vectors_s_v8s16_s_v2s16_s_v2s16_s_v2s16_s_v2s16			; GCN-LABEL: name: test_concat_vectors_s_v8s16_s_v2s16_s_v2s16_s_v2s16_s_v2s16
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
	; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3			; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
	; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]			; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
	%0:sgpr(<2 x s16>) = COPY $sgpr0			%0:sgpr(<2 x s16>) = COPY $sgpr0
	%1:sgpr(<2 x s16>) = COPY $sgpr1			%1:sgpr(<2 x s16>) = COPY $sgpr1
	%2:sgpr(<2 x s16>) = COPY $sgpr2			%2:sgpr(<2 x s16>) = COPY $sgpr2
	%3:sgpr(<2 x s16>) = COPY $sgpr3			%3:sgpr(<2 x s16>) = COPY $sgpr3
	%4:sgpr(<8 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3			%4:sgpr(<8 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3
	$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4			$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4			liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4

	; GCN-LABEL: name: test_concat_vectors_s_s160_s_v2s16_s_v2s16_s_v2s16_s_v2s16_s_v2s16			; GCN-LABEL: name: test_concat_vectors_s_s160_s_v2s16_s_v2s16_s_v2s16_s_v2s16_s_v2s16
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
	; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3			; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
	; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4			; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_160 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_160 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4
	; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY [[REG_SEQUENCE]]			; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY [[REG_SEQUENCE]]
	%0:sgpr(<2 x s16>) = COPY $sgpr0			%0:sgpr(<2 x s16>) = COPY $sgpr0
	%1:sgpr(<2 x s16>) = COPY $sgpr1			%1:sgpr(<2 x s16>) = COPY $sgpr1
	%2:sgpr(<2 x s16>) = COPY $sgpr2			%2:sgpr(<2 x s16>) = COPY $sgpr2
	%3:sgpr(<2 x s16>) = COPY $sgpr3			%3:sgpr(<2 x s16>) = COPY $sgpr3
	%4:sgpr(<2 x s16>) = COPY $sgpr4			%4:sgpr(<2 x s16>) = COPY $sgpr4
	%5:sgpr(<10 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3, %4			%5:sgpr(<10 x s16>) = G_CONCAT_VECTORS %0, %1, %2, %3, %4
	▲ Show 20 Lines • Show All 490 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

Show All 12 Lines	bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: constant		; GCN-LABEL: name: constant
%0:vgpr(p1) = COPY $vgpr0_vgpr1		%0:vgpr(p1) = COPY $vgpr0_vgpr1
%1:vgpr(p1) = COPY $vgpr2_vgpr3		%1:vgpr(p1) = COPY $vgpr2_vgpr3

; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1		; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1
%2:sreg_32(s32) = G_CONSTANT i32 1		%2:sreg_32(s32) = G_CONSTANT i32 1

; GCN: [[LO0:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0		; GCN: [[LO0:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: [[HI0:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; GCN: [[HI0:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1		; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1
%3:sgpr(s64) = G_CONSTANT i64 4294967296		%3:sgpr(s64) = G_CONSTANT i64 4294967296

; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1065353216		; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1065353216
%4:sgpr(s32) = G_FCONSTANT float 1.0		%4:sgpr(s32) = G_FCONSTANT float 1.0

; GCN: %5:sreg_64_xexec = S_MOV_B64 4607182418800017408		; GCN: %5:sreg_64_xexec = S_MOV_B64 4607182418800017408
%5:sgpr(s64) = G_FCONSTANT double 1.0		%5:sgpr(s64) = G_FCONSTANT double 1.0

; GCN: [[LO1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0		; GCN: [[LO1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: [[HI1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1076101120		; GCN: [[HI1:%[0-9]+]]:sreg_32 = S_MOV_B32 1076101120
; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO1]], %subreg.sub0, [[HI1]], %subreg.sub1		; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO1]], %subreg.sub0, [[HI1]], %subreg.sub1
%6:sgpr(s64) = G_FCONSTANT double 10.0		%6:sgpr(s64) = G_FCONSTANT double 10.0

; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1		; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1
%7:vgpr(s32) = G_CONSTANT i32 1		%7:vgpr(s32) = G_CONSTANT i32 1

; GCN: [[LO2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0		; GCN: [[LO2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
; GCN: [[HI2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1		; GCN: [[HI2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1
Show All 14 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

	Show All 37 Lines
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc			liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc

	; WAVE64-LABEL: name: copy_vcc_bank_scc_bank			; WAVE64-LABEL: name: copy_vcc_bank_scc_bank
	; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2			; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
	; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3			; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
	; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; WAVE64: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
	; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec			; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
	; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec			; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
	; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)			; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
	; WAVE32-LABEL: name: copy_vcc_bank_scc_bank			; WAVE32-LABEL: name: copy_vcc_bank_scc_bank
	; WAVE32: $vcc_hi = IMPLICIT_DEF			; WAVE32: $vcc_hi = IMPLICIT_DEF
	; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2			; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
	; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3			; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
	; WAVE32: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; WAVE32: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
	; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec			; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
	; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec			; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
	; WAVE32: GLOBAL_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)			; WAVE32: GLOBAL_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
	%0:vgpr(p1) = COPY $vgpr0_vgpr1			%0:vgpr(p1) = COPY $vgpr0_vgpr1
	%1:vgpr(s32) = COPY $vgpr2			%1:vgpr(s32) = COPY $vgpr2
	%2:vgpr(s32) = COPY $vgpr3			%2:vgpr(s32) = COPY $vgpr3
	%3:scc(s1) = COPY $scc			%3:scc(s1) = COPY $scc
	%4:vcc(s1) = COPY %3			%4:vcc(s1) = COPY %3
	Show All 9 Lines
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc			liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc

	; WAVE64-LABEL: name: copy_vcc_bank_scc_bank_2_uses			; WAVE64-LABEL: name: copy_vcc_bank_scc_bank_2_uses
	; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2			; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
	; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3			; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
	; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; WAVE64: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
	; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec			; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
	; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec			; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
	; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec			; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
	; WAVE64: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_1]], implicit $exec			; WAVE64: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_1]], implicit $exec
	; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)			; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
	; WAVE32-LABEL: name: copy_vcc_bank_scc_bank_2_uses			; WAVE32-LABEL: name: copy_vcc_bank_scc_bank_2_uses
	; WAVE32: $vcc_hi = IMPLICIT_DEF			; WAVE32: $vcc_hi = IMPLICIT_DEF
	; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2			; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
	; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3			; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
	; WAVE32: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; WAVE32: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
	; WAVE32: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY3]]			; WAVE32: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY3]]
	; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[COPY4]], implicit $exec			; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[COPY4]], implicit $exec
	; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec			; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
	; WAVE32: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec			; WAVE32: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
	; WAVE32: GLOBAL_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)			; WAVE32: GLOBAL_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
	%0:vgpr(p1) = COPY $vgpr0_vgpr1			%0:vgpr(p1) = COPY $vgpr0_vgpr1
	%1:vgpr(s32) = COPY $vgpr2			%1:vgpr(s32) = COPY $vgpr2
	%2:vgpr(s32) = COPY $vgpr3			%2:vgpr(s32) = COPY $vgpr3
	▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true


	body: \|			body: \|
	; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc			; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc
	; WAVE64: bb.0:			; WAVE64: bb.0:
	; WAVE64: successors: %bb.1(0x80000000)			; WAVE64: successors: %bb.1(0x80000000)
	; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec			; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
	; WAVE64: $vcc = COPY [[V_CMP_NE_U32_e64_]]			; WAVE64: $vcc = COPY [[V_CMP_NE_U32_e64_]]
	; WAVE64: S_CBRANCH_VCCNZ %bb.1, implicit $vcc			; WAVE64: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
	; WAVE64: bb.1:			; WAVE64: bb.1:
	; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc			; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc
	; WAVE32: bb.0:			; WAVE32: bb.0:
	; WAVE32: successors: %bb.1(0x80000000)			; WAVE32: successors: %bb.1(0x80000000)
	; WAVE32: $vcc_hi = IMPLICIT_DEF			; WAVE32: $vcc_hi = IMPLICIT_DEF
	; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec			; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
	; WAVE32: $vcc_lo = COPY [[V_CMP_NE_U32_e64_]]			; WAVE32: $vcc_lo = COPY [[V_CMP_NE_U32_e64_]]
	; WAVE32: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo			; WAVE32: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
	; WAVE32: bb.1:			; WAVE32: bb.1:
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s1) = G_TRUNC %0			%1:sgpr(s1) = G_TRUNC %0
	%2:vcc(s1) = COPY %1			%2:vcc(s1) = COPY %1
	Show All 9 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true


	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1
	; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc_constrain			; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc_constrain
	; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec			; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
	; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]			; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
	; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc_constrain			; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc_constrain
	; WAVE32: $vcc_hi = IMPLICIT_DEF			; WAVE32: $vcc_hi = IMPLICIT_DEF
	; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec			; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
	; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]			; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s1) = G_TRUNC %0			%1:sgpr(s1) = G_TRUNC %0
	%2:vcc(s1) = COPY %1			%2:vcc(s1) = COPY %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2

	...			...

	---			---

	name: copy_s1_vcc_to_vcc			name: copy_s1_vcc_to_vcc
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true


	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1

	; WAVE64-LABEL: name: copy_s1_vcc_to_vcc			; WAVE64-LABEL: name: copy_s1_vcc_to_vcc
	; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec			; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
	; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_NE_U32_e64_]]			; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_NE_U32_e64_]]
	; WAVE64: S_ENDPGM 0, implicit [[COPY1]]			; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
	; WAVE32-LABEL: name: copy_s1_vcc_to_vcc			; WAVE32-LABEL: name: copy_s1_vcc_to_vcc
	; WAVE32: $vcc_hi = IMPLICIT_DEF			; WAVE32: $vcc_hi = IMPLICIT_DEF
	; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec			; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
	; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]			; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
	; WAVE32: S_ENDPGM 0, implicit [[COPY1]]			; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s1) = G_TRUNC %0			%1:sgpr(s1) = G_TRUNC %0
	%2:vcc(s1) = COPY %1			%2:vcc(s1) = COPY %1
	%3:vcc(s1) = COPY %2			%3:vcc(s1) = COPY %2
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3

	Show All 22 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir

	Show All 27 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ctpop_s32_vs			; CHECK-LABEL: name: ctpop_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec			; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_CTPOP %0			%1:vgpr(s32) = G_CTPOP %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---
	▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $sgpr0			liveins: $vgpr0, $sgpr0

	; CHECK-LABEL: name: add_ctpop_s32_v_vs_commute0			; CHECK-LABEL: name: add_ctpop_s32_v_vs_commute0
	; CHECK: liveins: $vgpr0, $sgpr0			; CHECK: liveins: $vgpr0, $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec			; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_CTPOP %0			%2:vgpr(s32) = G_CTPOP %0
	%3:vgpr(s32) = G_ADD %2, %1			%3:vgpr(s32) = G_ADD %2, %1
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3
	...			...

	# SGPR->VGPR ctpop with VALU add			# SGPR->VGPR ctpop with VALU add
	---			---
	name: add_ctpop_s32_v_sv_commute0			name: add_ctpop_s32_v_sv_commute0
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $sgpr0			liveins: $vgpr0, $sgpr0

	; CHECK-LABEL: name: add_ctpop_s32_v_sv_commute0			; CHECK-LABEL: name: add_ctpop_s32_v_sv_commute0
	; CHECK: liveins: $vgpr0, $sgpr0			; CHECK: liveins: $vgpr0, $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_CTPOP %1			%2:vgpr(s32) = G_CTPOP %1
	%3:vgpr(s32) = G_ADD %2, %0			%3:vgpr(s32) = G_ADD %2, %0
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3
	...			...

	# Scalar ctpop with VALU add			# Scalar ctpop with VALU add
	---			---
	name: add_ctpop_s32_s_sv_commute0			name: add_ctpop_s32_s_sv_commute0
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; CHECK-LABEL: name: add_ctpop_s32_s_sv_commute0			; CHECK-LABEL: name: add_ctpop_s32_s_sv_commute0
	; CHECK: liveins: $sgpr0, $vgpr0			; CHECK: liveins: $sgpr0, $vgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec			; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:sgpr(s32) = G_CTPOP %0			%2:sgpr(s32) = G_CTPOP %0
	%3:vgpr(s32) = G_ADD %2, %1			%3:vgpr(s32) = G_ADD %2, %1
	S_ENDPGM 0, implicit %3			S_ENDPGM 0, implicit %3
	...			...

test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s			# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s
	---			---
	name: extract512			name: extract512
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	; CHECK-LABEL: name: extract512			; CHECK-LABEL: name: extract512
	; CHECK: [[DEF:%[0-9]+]]:sreg_512 = IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:sreg_512 = IMPLICIT_DEF
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
	; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1			; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
	; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub2			; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub2
	; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub3			; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub3
	; CHECK: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub4			; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub4
	; CHECK: [[COPY5:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub5			; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub5
	; CHECK: [[COPY6:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub6			; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub6
	; CHECK: [[COPY7:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub7			; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub7
	; CHECK: [[COPY8:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub8			; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub8
	; CHECK: [[COPY9:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub9			; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub9
	; CHECK: [[COPY10:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub10			; CHECK: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub10
	; CHECK: [[COPY11:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub11			; CHECK: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub11
	; CHECK: [[COPY12:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub12			; CHECK: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub12
	; CHECK: [[COPY13:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub13			; CHECK: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub13
	; CHECK: [[COPY14:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub14			; CHECK: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub14
	; CHECK: [[COPY15:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub15			; CHECK: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub15
	; CHECK: $sgpr0 = COPY [[COPY]]			; CHECK: $sgpr0 = COPY [[COPY]]
	; CHECK: $sgpr1 = COPY [[COPY1]]			; CHECK: $sgpr1 = COPY [[COPY1]]
	; CHECK: $sgpr2 = COPY [[COPY2]]			; CHECK: $sgpr2 = COPY [[COPY2]]
	; CHECK: $sgpr3 = COPY [[COPY3]]			; CHECK: $sgpr3 = COPY [[COPY3]]
	; CHECK: $sgpr4 = COPY [[COPY4]]			; CHECK: $sgpr4 = COPY [[COPY4]]
	; CHECK: $sgpr5 = COPY [[COPY5]]			; CHECK: $sgpr5 = COPY [[COPY5]]
	; CHECK: $sgpr6 = COPY [[COPY6]]			; CHECK: $sgpr6 = COPY [[COPY6]]
	; CHECK: $sgpr7 = COPY [[COPY7]]			; CHECK: $sgpr7 = COPY [[COPY7]]
	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	name: extract_s_s32_s1024			name: extract_s_s32_s1024
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	; CHECK-LABEL: name: extract_s_s32_s1024			; CHECK-LABEL: name: extract_s_s32_s1024
	; CHECK: [[DEF:%[0-9]+]]:sreg_1024 = IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:sreg_1024 = IMPLICIT_DEF
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
	; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1			; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
	; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub2			; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub2
	; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub3			; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub3
	; CHECK: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub4			; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub4
	; CHECK: [[COPY5:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub5			; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub5
	; CHECK: [[COPY6:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub6			; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub6
	; CHECK: [[COPY7:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub7			; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub7
	; CHECK: [[COPY8:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub8			; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub8
	; CHECK: [[COPY9:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub9			; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub9
	; CHECK: [[COPY10:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub10			; CHECK: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub10
	; CHECK: [[COPY11:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub11			; CHECK: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub11
	; CHECK: [[COPY12:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub12			; CHECK: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub12
	; CHECK: [[COPY13:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub13			; CHECK: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub13
	; CHECK: [[COPY14:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub14			; CHECK: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub14
	; CHECK: [[COPY15:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub15			; CHECK: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub15
	; CHECK: [[COPY16:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub16			; CHECK: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub16
	; CHECK: [[COPY17:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub17			; CHECK: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub17
	; CHECK: [[COPY18:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub18			; CHECK: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub18
	; CHECK: [[COPY19:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub19			; CHECK: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub19
	; CHECK: [[COPY20:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub20			; CHECK: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub20
	; CHECK: [[COPY21:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub21			; CHECK: [[COPY21:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub21
	; CHECK: [[COPY22:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub22			; CHECK: [[COPY22:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub22
	; CHECK: [[COPY23:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub23			; CHECK: [[COPY23:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub23
	; CHECK: [[COPY24:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub24			; CHECK: [[COPY24:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub24
	; CHECK: [[COPY25:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub25			; CHECK: [[COPY25:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub25
	; CHECK: [[COPY26:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub26			; CHECK: [[COPY26:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub26
	; CHECK: [[COPY27:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub27			; CHECK: [[COPY27:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub27
	; CHECK: [[COPY28:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub28			; CHECK: [[COPY28:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub28
	; CHECK: [[COPY29:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub29			; CHECK: [[COPY29:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub29
	; CHECK: [[COPY30:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub30			; CHECK: [[COPY30:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub30
	; CHECK: [[COPY31:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub31			; CHECK: [[COPY31:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub31
	; CHECK: S_ENDPGM 0, implicit [[DEF]], implicit [[COPY]], implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY6]], implicit [[COPY7]], implicit [[COPY8]], implicit [[COPY9]], implicit [[COPY10]], implicit [[COPY11]], implicit [[COPY12]], implicit [[COPY13]], implicit [[COPY14]], implicit [[COPY15]], implicit [[COPY16]], implicit [[COPY17]], implicit [[COPY18]], implicit [[COPY19]], implicit [[COPY20]], implicit [[COPY21]], implicit [[COPY22]], implicit [[COPY23]], implicit [[COPY24]], implicit [[COPY25]], implicit [[COPY26]], implicit [[COPY27]], implicit [[COPY28]], implicit [[COPY29]], implicit [[COPY30]], implicit [[COPY31]]			; CHECK: S_ENDPGM 0, implicit [[DEF]], implicit [[COPY]], implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY6]], implicit [[COPY7]], implicit [[COPY8]], implicit [[COPY9]], implicit [[COPY10]], implicit [[COPY11]], implicit [[COPY12]], implicit [[COPY13]], implicit [[COPY14]], implicit [[COPY15]], implicit [[COPY16]], implicit [[COPY17]], implicit [[COPY18]], implicit [[COPY19]], implicit [[COPY20]], implicit [[COPY21]], implicit [[COPY22]], implicit [[COPY23]], implicit [[COPY24]], implicit [[COPY25]], implicit [[COPY26]], implicit [[COPY27]], implicit [[COPY28]], implicit [[COPY29]], implicit [[COPY30]], implicit [[COPY31]]
	%0:sgpr(s1024) = G_IMPLICIT_DEF			%0:sgpr(s1024) = G_IMPLICIT_DEF
	%1:sgpr(s32) = G_EXTRACT %0:sgpr, 0			%1:sgpr(s32) = G_EXTRACT %0:sgpr, 0
	%2:sgpr(s32) = G_EXTRACT %0:sgpr, 32			%2:sgpr(s32) = G_EXTRACT %0:sgpr, 32
	%3:sgpr(s32) = G_EXTRACT %0:sgpr, 64			%3:sgpr(s32) = G_EXTRACT %0:sgpr, 64
	%4:sgpr(s32) = G_EXTRACT %0:sgpr, 96			%4:sgpr(s32) = G_EXTRACT %0:sgpr, 96
	%5:sgpr(s32) = G_EXTRACT %0:sgpr, 128			%5:sgpr(s32) = G_EXTRACT %0:sgpr, 128
	%6:sgpr(s32) = G_EXTRACT %0:sgpr, 160			%6:sgpr(s32) = G_EXTRACT %0:sgpr, 160
	Show All 30 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir

	Show All 10 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0
	; GCN-LABEL: name: fabs_s32_ss			; GCN-LABEL: name: fabs_s32_ss
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647			; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
	; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc			; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
	; GCN: $sgpr0 = COPY [[S_AND_B32_]]			; GCN: $sgpr0 = COPY [[S_AND_B32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = G_FABS %0			%1:sgpr(s32) = G_FABS %0
	$sgpr0 = COPY %1			$sgpr0 = COPY %1
	...			...

	---			---
	name: fabs_s32_vv			name: fabs_s32_vv
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1
	; GCN-LABEL: name: fabs_v2s16_ss			; GCN-LABEL: name: fabs_v2s16_ss
	; GCN: liveins: $sgpr0_sgpr1			; GCN: liveins: $sgpr0_sgpr1
	; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879			; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
	; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc			; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
	; GCN: $sgpr0 = COPY [[S_AND_B32_]]			; GCN: $sgpr0 = COPY [[S_AND_B32_]]
	%0:sgpr(<2 x s16>) = COPY $sgpr0			%0:sgpr(<2 x s16>) = COPY $sgpr0
	%1:sgpr(<2 x s16>) = G_FABS %0			%1:sgpr(<2 x s16>) = G_FABS %0
	$sgpr0 = COPY %1			$sgpr0 = COPY %1
	...			...

	---			---
	name: fabs_s16_ss			name: fabs_s16_ss
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0
	; GCN-LABEL: name: fabs_s16_ss			; GCN-LABEL: name: fabs_s16_ss
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767			; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
	; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc			; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
	; GCN: $sgpr0 = COPY [[S_AND_B32_]]			; GCN: $sgpr0 = COPY [[S_AND_B32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:sgpr(s16) = G_FABS %1			%2:sgpr(s16) = G_FABS %1
	%3:sgpr(s32) = G_ANYEXT %2			%3:sgpr(s32) = G_ANYEXT %2
	$sgpr0 = COPY %3			$sgpr0 = COPY %3
	...			...

	▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir

Show All 37 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
; WAVE32-LABEL: name: fcmp_oeq_s32_vv		; WAVE32-LABEL: name: fcmp_oeq_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1		%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ogt_s32_vv		name: fcmp_ogt_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ogt_s32_vv		; WAVE64-LABEL: name: fcmp_ogt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]
; WAVE32-LABEL: name: fcmp_ogt_s32_vv		; WAVE32-LABEL: name: fcmp_ogt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_oge_s32_vv		name: fcmp_oge_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oge_s32_vv		; WAVE64-LABEL: name: fcmp_oge_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]
; WAVE32-LABEL: name: fcmp_oge_s32_vv		; WAVE32-LABEL: name: fcmp_oge_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1		%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_olt_s32_vv		name: fcmp_olt_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_olt_s32_vv		; WAVE64-LABEL: name: fcmp_olt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]
; WAVE32-LABEL: name: fcmp_olt_s32_vv		; WAVE32-LABEL: name: fcmp_olt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1		%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ole_s32_vv		name: fcmp_ole_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ole_s32_vv		; WAVE64-LABEL: name: fcmp_ole_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]
; WAVE32-LABEL: name: fcmp_ole_s32_vv		; WAVE32-LABEL: name: fcmp_ole_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_one_s32_vv		name: fcmp_one_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_one_s32_vv		; WAVE64-LABEL: name: fcmp_one_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]
; WAVE32-LABEL: name: fcmp_one_s32_vv		; WAVE32-LABEL: name: fcmp_one_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1		%2:vcc(s1) = G_FCMP floatpred(one), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ord_s32_vv		name: fcmp_ord_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ord_s32_vv		; WAVE64-LABEL: name: fcmp_ord_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]
; WAVE32-LABEL: name: fcmp_ord_s32_vv		; WAVE32-LABEL: name: fcmp_ord_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_uno_s32_vv		name: fcmp_uno_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uno_s32_vv		; WAVE64-LABEL: name: fcmp_uno_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]
; WAVE32-LABEL: name: fcmp_uno_s32_vv		; WAVE32-LABEL: name: fcmp_uno_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1		%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ueq_s32_vv		name: fcmp_ueq_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ueq_s32_vv		; WAVE64-LABEL: name: fcmp_ueq_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]
; WAVE32-LABEL: name: fcmp_ueq_s32_vv		; WAVE32-LABEL: name: fcmp_ueq_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ugt_s32_vv		name: fcmp_ugt_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ugt_s32_vv		; WAVE64-LABEL: name: fcmp_ugt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]
; WAVE32-LABEL: name: fcmp_ugt_s32_vv		; WAVE32-LABEL: name: fcmp_ugt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_uge_s32_vv		name: fcmp_uge_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uge_s32_vv		; WAVE64-LABEL: name: fcmp_uge_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]
; WAVE32-LABEL: name: fcmp_uge_s32_vv		; WAVE32-LABEL: name: fcmp_uge_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1		%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ult_s32_vv		name: fcmp_ult_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ult_s32_vv		; WAVE64-LABEL: name: fcmp_ult_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]
; WAVE32-LABEL: name: fcmp_ult_s32_vv		; WAVE32-LABEL: name: fcmp_ult_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ule_s32_vv		name: fcmp_ule_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ule_s32_vv		; WAVE64-LABEL: name: fcmp_ule_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]
; WAVE32-LABEL: name: fcmp_ule_s32_vv		; WAVE32-LABEL: name: fcmp_ule_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_une_s32_vv		name: fcmp_une_s32_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_une_s32_vv		; WAVE64-LABEL: name: fcmp_une_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]
; WAVE32-LABEL: name: fcmp_une_s32_vv		; WAVE32-LABEL: name: fcmp_une_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1		%2:vcc(s1) = G_FCMP floatpred(une), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]
; WAVE32-LABEL: name: fcmp_oeq_s64_vv		; WAVE32-LABEL: name: fcmp_oeq_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1		%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ogt_s64_vv		name: fcmp_ogt_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ogt_s64_vv		; WAVE64-LABEL: name: fcmp_ogt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]
; WAVE32-LABEL: name: fcmp_ogt_s64_vv		; WAVE32-LABEL: name: fcmp_ogt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_oge_s64_vv		name: fcmp_oge_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_oge_s64_vv		; WAVE64-LABEL: name: fcmp_oge_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]
; WAVE32-LABEL: name: fcmp_oge_s64_vv		; WAVE32-LABEL: name: fcmp_oge_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1		%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_olt_s64_vv		name: fcmp_olt_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_olt_s64_vv		; WAVE64-LABEL: name: fcmp_olt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]
; WAVE32-LABEL: name: fcmp_olt_s64_vv		; WAVE32-LABEL: name: fcmp_olt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1		%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ole_s64_vv		name: fcmp_ole_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ole_s64_vv		; WAVE64-LABEL: name: fcmp_ole_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]
; WAVE32-LABEL: name: fcmp_ole_s64_vv		; WAVE32-LABEL: name: fcmp_ole_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_one_s64_vv		name: fcmp_one_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_one_s64_vv		; WAVE64-LABEL: name: fcmp_one_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]
; WAVE32-LABEL: name: fcmp_one_s64_vv		; WAVE32-LABEL: name: fcmp_one_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1		%2:vcc(s1) = G_FCMP floatpred(one), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ord_s64_vv		name: fcmp_ord_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ord_s64_vv		; WAVE64-LABEL: name: fcmp_ord_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]
; WAVE32-LABEL: name: fcmp_ord_s64_vv		; WAVE32-LABEL: name: fcmp_ord_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_uno_s64_vv		name: fcmp_uno_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_uno_s64_vv		; WAVE64-LABEL: name: fcmp_uno_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]
; WAVE32-LABEL: name: fcmp_uno_s64_vv		; WAVE32-LABEL: name: fcmp_uno_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1		%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ueq_s64_vv		name: fcmp_ueq_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ueq_s64_vv		; WAVE64-LABEL: name: fcmp_ueq_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]
; WAVE32-LABEL: name: fcmp_ueq_s64_vv		; WAVE32-LABEL: name: fcmp_ueq_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ugt_s64_vv		name: fcmp_ugt_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ugt_s64_vv		; WAVE64-LABEL: name: fcmp_ugt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]
; WAVE32-LABEL: name: fcmp_ugt_s64_vv		; WAVE32-LABEL: name: fcmp_ugt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_uge_s64_vv		name: fcmp_uge_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_uge_s64_vv		; WAVE64-LABEL: name: fcmp_uge_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]
; WAVE32-LABEL: name: fcmp_uge_s64_vv		; WAVE32-LABEL: name: fcmp_uge_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1		%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ult_s64_vv		name: fcmp_ult_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ult_s64_vv		; WAVE64-LABEL: name: fcmp_ult_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]
; WAVE32-LABEL: name: fcmp_ult_s64_vv		; WAVE32-LABEL: name: fcmp_ult_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_ule_s64_vv		name: fcmp_ule_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ule_s64_vv		; WAVE64-LABEL: name: fcmp_ule_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]
; WAVE32-LABEL: name: fcmp_ule_s64_vv		; WAVE32-LABEL: name: fcmp_ule_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1		%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
name: fcmp_une_s64_vv		name: fcmp_une_s64_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_une_s64_vv		; WAVE64-LABEL: name: fcmp_une_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]
; WAVE32-LABEL: name: fcmp_une_s64_vv		; WAVE32-LABEL: name: fcmp_une_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1		; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3		; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1		%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3		%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1		%2:vcc(s1) = G_FCMP floatpred(une), %0, %1
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---
Show All 22 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]
; WAVE32-LABEL: name: fcmp_oeq_s16_vv		; WAVE32-LABEL: name: fcmp_oeq_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3		%4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
Show All 10 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]
; WAVE32-LABEL: name: fcmp_ogt_s16_vv		; WAVE32-LABEL: name: fcmp_ogt_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3		%4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
Show All 10 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]
; WAVE32-LABEL: name: fcmp_oge_s16_vv		; WAVE32-LABEL: name: fcmp_oge_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(oge), %2, %3		%4:vcc(s1) = G_FCMP floatpred(oge), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]
; WAVE32-LABEL: name: fcmp_olt_s16_vv		; WAVE32-LABEL: name: fcmp_olt_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(olt), %2, %3		%4:vcc(s1) = G_FCMP floatpred(olt), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]
; WAVE32-LABEL: name: fcmp_ole_s16_vv		; WAVE32-LABEL: name: fcmp_ole_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ole), %2, %3		%4:vcc(s1) = G_FCMP floatpred(ole), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
; WAVE32-LABEL: name: fcmp_one_s16_vv		; WAVE32-LABEL: name: fcmp_one_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3		%4:vcc(s1) = G_FCMP floatpred(one), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
; WAVE32-LABEL: name: fcmp_ord_s16_vv		; WAVE32-LABEL: name: fcmp_ord_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3		%4:vcc(s1) = G_FCMP floatpred(one), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]
; WAVE32-LABEL: name: fcmp_uno_s16_vv		; WAVE32-LABEL: name: fcmp_uno_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(uno), %2, %3		%4:vcc(s1) = G_FCMP floatpred(uno), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]
; WAVE32-LABEL: name: fcmp_ueq_s16_vv		; WAVE32-LABEL: name: fcmp_ueq_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3		%4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]
; WAVE32-LABEL: name: fcmp_ugt_s16_vv		; WAVE32-LABEL: name: fcmp_ugt_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3		%4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
Show All 10 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]
; WAVE32-LABEL: name: fcmp_uge_s16_vv		; WAVE32-LABEL: name: fcmp_uge_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(uge), %2, %3		%4:vcc(s1) = G_FCMP floatpred(uge), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
Show All 10 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]
; WAVE32-LABEL: name: fcmp_ult_s16_vv		; WAVE32-LABEL: name: fcmp_ult_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ult), %2, %3		%4:vcc(s1) = G_FCMP floatpred(ult), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
Show All 10 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]
; WAVE32-LABEL: name: fcmp_ule_s16_vv		; WAVE32-LABEL: name: fcmp_ule_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ule), %2, %3		%4:vcc(s1) = G_FCMP floatpred(ule), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
Show All 10 Lines	bb.0:
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE64: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]		; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]
; WAVE32-LABEL: name: fcmp_une_s16_vv		; WAVE32-LABEL: name: fcmp_une_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec		; WAVE32: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]		; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0		%2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1		%3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(une), %2, %3		%4:vcc(s1) = G_FCMP floatpred(une), %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
...		...
Show All 31 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.mir

	Show All 27 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ffloor_s32_vs			; CHECK-LABEL: name: ffloor_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]			; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_FFLOOR %0			%1:vgpr(s32) = G_FFLOOR %0
	$vgpr0 = COPY %1			$vgpr0 = COPY %1
	...			...

	---			---
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ffloor_fneg_s32_vs			; CHECK-LABEL: name: ffloor_fneg_s32_vs
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $exec			; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $exec
	; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]			; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = G_FNEG %0			%1:sgpr(s32) = G_FNEG %0
	%2:vgpr(s32) = G_FFLOOR %1			%2:vgpr(s32) = G_FFLOOR %1
	$vgpr0 = COPY %2			$vgpr0 = COPY %2
	...			...

	▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir

	Show All 9 Lines
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; VI-LABEL: name: ffloor_s16_ss			; VI-LABEL: name: ffloor_s16_ss
	; VI: liveins: $sgpr0			; VI: liveins: $sgpr0
	; VI: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; VI: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; VI: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)			; VI: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
	; VI: [[FFLOOR:%[0-9]+]]:sreg_32_xm0(s16) = G_FFLOOR [[TRUNC]]			; VI: [[FFLOOR:%[0-9]+]]:sreg_32(s16) = G_FFLOOR [[TRUNC]]
	; VI: [[COPY1:%[0-9]+]]:sreg_32_xm0(s32) = COPY [[FFLOOR]](s16)			; VI: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FFLOOR]](s16)
	; VI: $sgpr0 = COPY [[COPY1]](s32)			; VI: $sgpr0 = COPY [[COPY1]](s32)
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:sgpr(s16) = G_FFLOOR %1			%2:sgpr(s16) = G_FFLOOR %1
	%3:sgpr(s32) = G_ANYEXT %2			%3:sgpr(s32) = G_ANYEXT %2
	$sgpr0 = COPY %3			$sgpr0 = COPY %3
	...			...

	Show All 26 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; VI-LABEL: name: ffloor_s16_vs			; VI-LABEL: name: ffloor_s16_vs
	; VI: liveins: $sgpr0			; VI: liveins: $sgpr0
	; VI: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $exec			; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $exec
	; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]]			; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:vgpr(s16) = G_FFLOOR %1			%2:vgpr(s16) = G_FFLOOR %1
	%3:vgpr(s32) = G_ANYEXT %2			%3:vgpr(s32) = G_ANYEXT %2
	$vgpr0 = COPY %3			$vgpr0 = COPY %3
	...			...
	Show All 31 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck -check-prefix=GFX7 %s			# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck -check-prefix=GFX7 %s

	---			---

	name: fmaxnum_ieee_f32_f64_ieee_mode_on			name: fmaxnum_ieee_f32_f64_ieee_mode_on
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	machineFunctionInfo:			machineFunctionInfo:
	mode:			mode:
	ieee: true			ieee: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
	; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_on			; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_on
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11			; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
	; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11			; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
	; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13			; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
	; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	machineFunctionInfo:			machineFunctionInfo:
	mode:			mode:
	ieee: false			ieee: false

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
	; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_off			; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_off
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11			; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
	; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11			; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
	; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13			; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
	; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir

	Show All 9 Lines
	machineFunctionInfo:			machineFunctionInfo:
	mode:			mode:
	ieee: true			ieee: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
	; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_on			; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_on
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11			; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
	; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11			; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
	; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13			; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
	; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
	machineFunctionInfo:			machineFunctionInfo:
	mode:			mode:
	ieee: false			ieee: false

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
	; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_off			; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_off
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11			; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
	; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11			; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
	; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13			; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
	; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck -check-prefix=GFX7 %s			# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck -check-prefix=GFX7 %s

	---			---

	name: fminnum_ieee_f32_f64_ieee_mode_on			name: fminnum_ieee_f32_f64_ieee_mode_on
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	machineFunctionInfo:			machineFunctionInfo:
	mode:			mode:
	ieee: true			ieee: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
	; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_on			; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_on
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11			; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
	; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11			; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
	; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13			; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
	; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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	machineFunctionInfo:			machineFunctionInfo:
	mode:			mode:
	ieee: false			ieee: false

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
	; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_off			; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_off
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11			; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
	; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11			; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
	; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13			; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
	; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir

	Show All 9 Lines
	machineFunctionInfo:			machineFunctionInfo:
	mode:			mode:
	ieee: true			ieee: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
	; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_on			; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_on
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11			; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
	; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11			; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
	; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13			; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
	; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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	machineFunctionInfo:			machineFunctionInfo:
	mode:			mode:
	ieee: false			ieee: false

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
	; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_off			; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_off
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11			; GFX7: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
	; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11			; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
	; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13			; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
	; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s -check-prefixes=GCN			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s -check-prefixes=GCN

	---			---

	name: fmul_f32			name: fmul_f32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
	; GCN-LABEL: name: fmul_f32			; GCN-LABEL: name: fmul_f32
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1			; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
	; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GCN: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec			; GCN: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
	; GCN: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: [[V_MUL_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec			; GCN: [[V_MUL_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
	; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr			; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
	; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr			; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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	name: fmul_f16			name: fmul_f16
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4			liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
	; GCN-LABEL: name: fmul_f16			; GCN-LABEL: name: fmul_f16
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec			; GCN: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
	; GCN: [[V_MUL_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec			; GCN: [[V_MUL_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
	; GCN: [[V_MUL_F16_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_MUL_F16_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]], implicit [[V_MUL_F16_e64_1]], implicit [[V_MUL_F16_e64_2]]			; GCN: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]], implicit [[V_MUL_F16_e64_1]], implicit [[V_MUL_F16_e64_2]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = COPY $vgpr1			%2:vgpr(s32) = COPY $vgpr1
	▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir

Show All 10 Lines

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0
; GCN-LABEL: name: fneg_s32_ss		; GCN-LABEL: name: fneg_s32_ss
; GCN: liveins: $sgpr0		; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GCN: $sgpr0 = COPY [[S_XOR_B32_]]		; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_FNEG %0		%1:sgpr(s32) = G_FNEG %0
$sgpr0 = COPY %1		$sgpr0 = COPY %1
...		...

---		---
name: fneg_s32_vv		name: fneg_s32_vv
Show All 40 Lines
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0
; GCN-LABEL: name: fneg_s16_ss		; GCN-LABEL: name: fneg_s16_ss
; GCN: liveins: $sgpr0		; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GCN: $sgpr0 = COPY [[S_XOR_B32_]]		; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s16) = G_FNEG %1		%2:sgpr(s16) = G_FNEG %1
%3:sgpr(s32) = G_ANYEXT %2		%3:sgpr(s32) = G_ANYEXT %2
$sgpr0 = COPY %3		$sgpr0 = COPY %3
...		...

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body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0_sgpr1		liveins: $sgpr0_sgpr1
; GCN-LABEL: name: fneg_v2s16_ss		; GCN-LABEL: name: fneg_v2s16_ss
; GCN: liveins: $sgpr0_sgpr1		; GCN: liveins: $sgpr0_sgpr1
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; GCN: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GCN: $sgpr0 = COPY [[S_XOR_B32_]]		; GCN: $sgpr0 = COPY [[S_XOR_B32_]]
%0:sgpr(<2 x s16>) = COPY $sgpr0		%0:sgpr(<2 x s16>) = COPY $sgpr0
%1:sgpr(<2 x s16>) = G_FNEG %0		%1:sgpr(<2 x s16>) = G_FNEG %0
$sgpr0 = COPY %1		$sgpr0 = COPY %1
...		...

---		---
name: fneg_v2s16_vv		name: fneg_v2s16_vv
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body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0_sgpr1		liveins: $sgpr0_sgpr1
; GCN-LABEL: name: fneg_fabs_s32_ss		; GCN-LABEL: name: fneg_fabs_s32_ss
; GCN: liveins: $sgpr0_sgpr1		; GCN: liveins: $sgpr0_sgpr1
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GCN: $sgpr0 = COPY [[S_OR_B32_]]		; GCN: $sgpr0 = COPY [[S_OR_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_FABS %0		%1:sgpr(s32) = G_FABS %0
%2:sgpr(s32) = G_FNEG %1		%2:sgpr(s32) = G_FNEG %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0
; GCN-LABEL: name: fneg_fabs_s16_ss		; GCN-LABEL: name: fneg_fabs_s16_ss
; GCN: liveins: $sgpr0		; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GCN: $sgpr0 = COPY [[S_OR_B32_]]		; GCN: $sgpr0 = COPY [[S_OR_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s16) = G_FABS %1		%2:sgpr(s16) = G_FABS %1
%3:sgpr(s16) = G_FNEG %2		%3:sgpr(s16) = G_FNEG %2
%4:sgpr(s32) = G_ANYEXT %3		%4:sgpr(s32) = G_ANYEXT %3
$sgpr0 = COPY %4		$sgpr0 = COPY %4
...		...

---		---
name: fneg_fabs_s16_vv		name: fneg_fabs_s16_vv
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0
; GCN-LABEL: name: fneg_fabs_s16_vv		; GCN-LABEL: name: fneg_fabs_s16_vv
; GCN: liveins: $vgpr0		; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec		; GCN: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[V_OR_B32_e32_]]		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_OR_B32_e32_]]
; GCN: $vgpr0 = COPY [[COPY1]]		; GCN: $vgpr0 = COPY [[COPY1]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0		%1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FABS %1		%2:vgpr(s16) = G_FABS %1
%3:vgpr(s16) = G_FNEG %2		%3:vgpr(s16) = G_FNEG %2
%4:sgpr(s32) = G_ANYEXT %3		%4:sgpr(s32) = G_ANYEXT %3
$vgpr0 = COPY %4		$vgpr0 = COPY %4
...		...
Show All 9 Lines	bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: fneg_fabs_s16_vs		; GCN-LABEL: name: fneg_fabs_s16_vs
; GCN: liveins: $sgpr0		; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)		; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; GCN: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]]		; GCN: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]]
; GCN: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]]		; GCN: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]]
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0(s32) = COPY [[FNEG1]](s16)		; GCN: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG1]](s16)
; GCN: $vgpr0 = COPY [[COPY1]](s32)		; GCN: $vgpr0 = COPY [[COPY1]](s32)
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s16) = G_FNEG %1		%2:sgpr(s16) = G_FNEG %1
%3:vgpr(s16) = G_FNEG %2		%3:vgpr(s16) = G_FNEG %2
%4:sgpr(s32) = G_ANYEXT %3		%4:sgpr(s32) = G_ANYEXT %3
$vgpr0 = COPY %4		$vgpr0 = COPY %4
...		...

---		---
name: fneg_fabs_v2s16_ss		name: fneg_fabs_v2s16_ss
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0_sgpr1		liveins: $sgpr0_sgpr1
; GCN-LABEL: name: fneg_fabs_v2s16_ss		; GCN-LABEL: name: fneg_fabs_v2s16_ss
; GCN: liveins: $sgpr0_sgpr1		; GCN: liveins: $sgpr0_sgpr1
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; GCN: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GCN: $sgpr0 = COPY [[S_OR_B32_]]		; GCN: $sgpr0 = COPY [[S_OR_B32_]]
%0:sgpr(<2 x s16>) = COPY $sgpr0		%0:sgpr(<2 x s16>) = COPY $sgpr0
%1:sgpr(<2 x s16>) = G_FABS %0		%1:sgpr(<2 x s16>) = G_FABS %0
%2:sgpr(<2 x s16>) = G_FNEG %1		%2:sgpr(<2 x s16>) = G_FNEG %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir

	Show All 27 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; GCN-LABEL: name: fptosi_s32_to_s32_vs			; GCN-LABEL: name: fptosi_s32_to_s32_vs
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]			; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = G_FPTOSI %0			%1:vgpr(s32) = G_FPTOSI %0
	$vgpr0 = COPY %1			$vgpr0 = COPY %1
	...			...

	---			---
	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; GCN-LABEL: name: fptosi_s16_to_s32_vs			; GCN-LABEL: name: fptosi_s16_to_s32_vs
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec			; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
	; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec			; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
	; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]			; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:vgpr(s32) = G_FPTOSI %1			%2:vgpr(s32) = G_FPTOSI %1
	$vgpr0 = COPY %2			$vgpr0 = COPY %2
	...			...
	Show All 25 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s -check-prefix=GCN			# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s -check-prefix=GCN

	---			---

	name: fptoui			name: fptoui
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4			liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4

	; GCN-LABEL: name: fptoui			; GCN-LABEL: name: fptoui
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4			; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
	; GCN: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $exec			; GCN: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
	; GCN: [[V_CVT_U32_F32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $exec			; GCN: [[V_CVT_U32_F32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $exec
	; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)			; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
	; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)			; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0

	Show All 40 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; GCN-LABEL: name: fptoui_s16_to_s32_vs			; GCN-LABEL: name: fptoui_s16_to_s32_vs
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec			; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
	; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec			; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
	; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]			; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	%2:vgpr(s32) = G_FPTOUI %1			%2:vgpr(s32) = G_FPTOUI %1
	$vgpr0 = COPY %2			$vgpr0 = COPY %2
	...			...
	Show All 25 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s -check-prefix=GCN			# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s -check-prefix=GCN

	---			---

	name: frame_index_s			name: frame_index_s
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	stack:			stack:
	- { id: 0, size: 4, alignment: 4 }			- { id: 0, size: 4, alignment: 4 }

	body: \|			body: \|
	bb.0:			bb.0:
	; GCN-LABEL: name: frame_index_s			; GCN-LABEL: name: frame_index_s
	; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0			; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 %stack.0
	; GCN: $sgpr0 = COPY [[S_MOV_B32_]]			; GCN: $sgpr0 = COPY [[S_MOV_B32_]]
	%0:sgpr(p5) = G_FRAME_INDEX %stack.0			%0:sgpr(p5) = G_FRAME_INDEX %stack.0
	$sgpr0 = COPY %0			$sgpr0 = COPY %0

	...			...

	---			---

	Show All 15 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir

	Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
	name: gep_p3_sgpr_vgpr			name: gep_p3_sgpr_vgpr
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX6-LABEL: name: gep_p3_sgpr_vgpr			; GFX6-LABEL: name: gep_p3_sgpr_vgpr
	; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX6: S_ENDPGM 0, implicit %2			; GFX6: S_ENDPGM 0, implicit %2
	; GFX8-LABEL: name: gep_p3_sgpr_vgpr			; GFX8-LABEL: name: gep_p3_sgpr_vgpr
	; GFX8: $vcc_hi = IMPLICIT_DEF			; GFX8: $vcc_hi = IMPLICIT_DEF
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: %2:vgpr_32, dead %3:sreg_32_xm0_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX8: %2:vgpr_32, dead %3:sreg_32_xm0_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX8: S_ENDPGM 0, implicit %2			; GFX8: S_ENDPGM 0, implicit %2
	; GFX9-LABEL: name: gep_p3_sgpr_vgpr			; GFX9-LABEL: name: gep_p3_sgpr_vgpr
	; GFX9: $vcc_hi = IMPLICIT_DEF			; GFX9: $vcc_hi = IMPLICIT_DEF
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
	; GFX10-WAVE64-LABEL: name: gep_p3_sgpr_vgpr			; GFX10-WAVE64-LABEL: name: gep_p3_sgpr_vgpr
	; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10-WAVE64: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX10-WAVE64: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX10-WAVE64: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]			; GFX10-WAVE64: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
	; GFX10-WAVE32-LABEL: name: gep_p3_sgpr_vgpr			; GFX10-WAVE32-LABEL: name: gep_p3_sgpr_vgpr
	; GFX10-WAVE32: $vcc_hi = IMPLICIT_DEF			; GFX10-WAVE32: $vcc_hi = IMPLICIT_DEF
	; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10-WAVE32: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX10-WAVE32: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX10-WAVE32: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]			; GFX10-WAVE32: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
	%0:sgpr(p3) = COPY $sgpr0			%0:sgpr(p3) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(p3) = G_GEP %0, %1			%2:vgpr(p3) = G_GEP %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2

	▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir

	Show All 11 Lines
	# GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1			# GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	# GCN: [[SGPR2:%[0-9]+]]:sreg_32 = COPY $sgpr2			# GCN: [[SGPR2:%[0-9]+]]:sreg_32 = COPY $sgpr2
	# GCN: [[SGPR3:%[0-9]+]]:sreg_32 = COPY $sgpr3			# GCN: [[SGPR3:%[0-9]+]]:sreg_32 = COPY $sgpr3
	# GCN: [[SGPR4:%[0-9]+]]:sreg_32 = COPY $sgpr4			# GCN: [[SGPR4:%[0-9]+]]:sreg_32 = COPY $sgpr4
	# GCN: [[SGPR5:%[0-9]+]]:sreg_32 = COPY $sgpr5			# GCN: [[SGPR5:%[0-9]+]]:sreg_32 = COPY $sgpr5
	# GCN: [[SGPR6:%[0-9]+]]:sreg_32 = COPY $sgpr6			# GCN: [[SGPR6:%[0-9]+]]:sreg_32 = COPY $sgpr6
	# GCN: [[SGPR7:%[0-9]+]]:sreg_32 = COPY $sgpr7			# GCN: [[SGPR7:%[0-9]+]]:sreg_32 = COPY $sgpr7
	# GCN: S_CMP_LG_U32 [[SGPR0]], [[SGPR1]], implicit-def $scc			# GCN: S_CMP_LG_U32 [[SGPR0]], [[SGPR1]], implicit-def $scc
	# GCN-NEXT: [[COND0:%[0-9]+]]:sreg_32_xm0 = COPY $scc			# GCN-NEXT: [[COND0:%[0-9]+]]:sgpr_32 = COPY $scc
	# GCN: S_CMP_LG_U32 [[SGPR4]], [[SGPR5]], implicit-def $scc			# GCN: S_CMP_LG_U32 [[SGPR4]], [[SGPR5]], implicit-def $scc
	# GCN-NEXT: [[COND1:%[0-9]+]]:sreg_32_xm0 = COPY $scc			# GCN-NEXT: [[COND1:%[0-9]+]]:sgpr_32 = COPY $scc
	# GCN: $scc = COPY [[COND0]]			# GCN: $scc = COPY [[COND0]]
	# GCN-NEXT: S_CSELECT_B32 [[SGPR6]], [[SGPR7]], implicit $scc			# GCN-NEXT: S_CSELECT_B32 [[SGPR6]], [[SGPR7]], implicit $scc
	# GCN: $scc = COPY [[COND1]]			# GCN: $scc = COPY [[COND1]]
	# GCN-NEXT: S_CSELECT_B32 [[SGPR2]], [[SGPR3]], implicit $scc			# GCN-NEXT: S_CSELECT_B32 [[SGPR2]], [[SGPR3]], implicit $scc

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7			liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7
	▲ Show 20 Lines • Show All 208 Lines • ▼ Show 20 Lines
	---			---

	name: icmp_s32_vs			name: icmp_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	# GCN-LABEL: name: icmp_s32_vs			# GCN-LABEL: name: icmp_s32_vs
	# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2			# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
	# GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
	# GCN: V_CMP_NE_U32_e64 [[VGPR2]], [[SGPR0]]			# GCN: V_CMP_NE_U32_e64 [[VGPR2]], [[SGPR0]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0			liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0

	%0:vgpr(p1) = COPY $vgpr0_vgpr1			%0:vgpr(p1) = COPY $vgpr0_vgpr1
	%1:vgpr(s32) = COPY $vgpr2			%1:vgpr(s32) = COPY $vgpr2
	%2:vgpr(s32) = COPY $vgpr3			%2:vgpr(s32) = COPY $vgpr3
	%3:vgpr(s32) = COPY $vgpr4			%3:vgpr(s32) = COPY $vgpr4
	%4:sgpr(s32) = COPY $sgpr0			%4:sgpr(s32) = COPY $sgpr0
	%5:vcc(s1) = G_ICMP intpred(ne), %1, %4			%5:vcc(s1) = G_ICMP intpred(ne), %1, %4
	%6:vgpr(s32) = G_SELECT %5, %2, %3			%6:vgpr(s32) = G_SELECT %5, %2, %3
	G_STORE %6, %0 :: (store 4, addrspace 1)			G_STORE %6, %0 :: (store 4, addrspace 1)
	...			...
	---			---

	name: icmp_s32_sv			name: icmp_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	# GCN-LABEL: name: icmp_s32_sv			# GCN-LABEL: name: icmp_s32_sv
	# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2			# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
	# GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
	# GCN: V_CMP_NE_U32_e64 [[SGPR0]], [[VGPR2]]			# GCN: V_CMP_NE_U32_e64 [[SGPR0]], [[VGPR2]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0			liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0

	%0:vgpr(p1) = COPY $vgpr0_vgpr1			%0:vgpr(p1) = COPY $vgpr0_vgpr1
	%1:vgpr(s32) = COPY $vgpr2			%1:vgpr(s32) = COPY $vgpr2
	%2:vgpr(s32) = COPY $vgpr3			%2:vgpr(s32) = COPY $vgpr3
	%3:vgpr(s32) = COPY $vgpr4			%3:vgpr(s32) = COPY $vgpr4
	%4:sgpr(s32) = COPY $sgpr0			%4:sgpr(s32) = COPY $sgpr0
	%5:vcc(s1) = G_ICMP intpred(ne), %4, %1			%5:vcc(s1) = G_ICMP intpred(ne), %4, %1
	%6:vgpr(s32) = G_SELECT %5, %2, %3			%6:vgpr(s32) = G_SELECT %5, %2, %3
	G_STORE %6, %0 :: (store 4, addrspace 1)			G_STORE %6, %0 :: (store 4, addrspace 1)
	...			...
	---			---

	name: icmp_s32_or_vcc			name: icmp_s32_or_vcc
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	# GCN-LABEL: name: icmp_s32_or_vcc			# GCN-LABEL: name: icmp_s32_or_vcc
	# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2			# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
	# GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			# GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
	# GCN: V_CMP_NE_U32_e64 [[SGPR0]], [[VGPR2]]			# GCN: V_CMP_NE_U32_e64 [[SGPR0]], [[VGPR2]]

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0			liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0

	%0:vgpr(p1) = COPY $vgpr0_vgpr1			%0:vgpr(p1) = COPY $vgpr0_vgpr1
	%1:vgpr(s32) = COPY $vgpr2			%1:vgpr(s32) = COPY $vgpr2
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test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir

	Show All 9 Lines

	name: implicit_def_s32_sgpr			name: implicit_def_s32_sgpr
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	; GCN-LABEL: name: implicit_def_s32_sgpr			; GCN-LABEL: name: implicit_def_s32_sgpr
	; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF			; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
	; GCN: S_ENDPGM 0, implicit [[DEF]]			; GCN: S_ENDPGM 0, implicit [[DEF]]
	%0:sgpr(s32) = G_IMPLICIT_DEF			%0:sgpr(s32) = G_IMPLICIT_DEF
	S_ENDPGM 0, implicit %0			S_ENDPGM 0, implicit %0
	...			...
	---			---

	name: implicit_def_s32_vgpr			name: implicit_def_s32_vgpr
	legalized: true			legalized: true
	▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines

	name: implicit_def_s1_sgpr			name: implicit_def_s1_sgpr
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	; GCN-LABEL: name: implicit_def_s1_sgpr			; GCN-LABEL: name: implicit_def_s1_sgpr
	; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF			; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
	; GCN: S_ENDPGM 0, implicit [[DEF]]			; GCN: S_ENDPGM 0, implicit [[DEF]]
	%0:sgpr(s1) = G_IMPLICIT_DEF			%0:sgpr(s1) = G_IMPLICIT_DEF
	S_ENDPGM 0, implicit %0			S_ENDPGM 0, implicit %0
	...			...

	---			---

	name: implicit_def_s1_scc			name: implicit_def_s1_scc
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	; GCN-LABEL: name: implicit_def_s1_scc			; GCN-LABEL: name: implicit_def_s1_scc
	; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF			; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
	; GCN: S_ENDPGM 0, implicit [[DEF]]			; GCN: S_ENDPGM 0, implicit [[DEF]]
	%0:scc(s1) = G_IMPLICIT_DEF			%0:scc(s1) = G_IMPLICIT_DEF
	S_ENDPGM 0, implicit %0			S_ENDPGM 0, implicit %0
	...			...

	---			---

	name: implicit_def_s1_vcc			name: implicit_def_s1_vcc
	Show All 40 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s

	---			---

	name: insert_s512_s32			name: insert_s512_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	; CHECK-LABEL: name: insert_s512_s32			; CHECK-LABEL: name: insert_s512_s32
	; CHECK: [[DEF:%[0-9]+]]:sreg_512 = IMPLICIT_DEF			; CHECK: [[DEF:%[0-9]+]]:sreg_512 = IMPLICIT_DEF
	; CHECK: [[DEF1:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF			; CHECK: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
	; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub0			; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub0
	; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG]], [[DEF1]], %subreg.sub1			; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG]], [[DEF1]], %subreg.sub1
	; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG1]], [[DEF1]], %subreg.sub2			; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG1]], [[DEF1]], %subreg.sub2
	; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG2]], [[DEF1]], %subreg.sub3			; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG2]], [[DEF1]], %subreg.sub3
	; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG3]], [[DEF1]], %subreg.sub4			; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG3]], [[DEF1]], %subreg.sub4
	; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG4]], [[DEF1]], %subreg.sub5			; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG4]], [[DEF1]], %subreg.sub5
	; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG5]], [[DEF1]], %subreg.sub6			; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG5]], [[DEF1]], %subreg.sub6
	; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG6]], [[DEF1]], %subreg.sub7			; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:sreg_512 = INSERT_SUBREG [[INSERT_SUBREG6]], [[DEF1]], %subreg.sub7
	▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $sgpr2			liveins: $sgpr0_sgpr1, $sgpr2
	; CHECK-LABEL: name: insert_s_s64_s_s32_0			; CHECK-LABEL: name: insert_s_s64_s_s32_0
	; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1			; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
	; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2			; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
	; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64_xexec = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0			; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64_xexec = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
	; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]			; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
	%0:sgpr(s64) = COPY $sgpr0_sgpr1			%0:sgpr(s64) = COPY $sgpr0_sgpr1
	%1:sgpr(s32) = COPY $sgpr2			%1:sgpr(s32) = COPY $sgpr2
	%2:sgpr(s64) = G_INSERT %0, %1, 0			%2:sgpr(s64) = G_INSERT %0, %1, 0
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---

	name: insert_s_s64_s_s32_32			name: insert_s_s64_s_s32_32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $sgpr2			liveins: $sgpr0_sgpr1, $sgpr2
	; CHECK-LABEL: name: insert_s_s64_s_s32_32			; CHECK-LABEL: name: insert_s_s64_s_s32_32
	; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1			; CHECK: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
	; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2			; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
	; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64_xexec = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1			; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64_xexec = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
	; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]			; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
	%0:sgpr(s64) = COPY $sgpr0_sgpr1			%0:sgpr(s64) = COPY $sgpr0_sgpr1
	%1:sgpr(s32) = COPY $sgpr2			%1:sgpr(s32) = COPY $sgpr2
	%2:sgpr(s64) = G_INSERT %0, %1, 32			%2:sgpr(s64) = G_INSERT %0, %1, 32
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 23 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $sgpr0			liveins: $vgpr0_vgpr1, $sgpr0
	; CHECK-LABEL: name: insert_v_s64_s_s32_32			; CHECK-LABEL: name: insert_v_s64_s_s32_32
	; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1			; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
	; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]			; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
	%0:vgpr(s64) = COPY $vgpr0_vgpr1			%0:vgpr(s64) = COPY $vgpr0_vgpr1
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s64) = G_INSERT %0, %1, 32			%2:vgpr(s64) = G_INSERT %0, %1, 32
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	▲ Show 20 Lines • Show All 394 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir

	Show First 20 Lines • Show All 735 Lines • ▼ Show 20 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1

	; GFX6-LABEL: name: load_constant_s32_from_4_gep_1024			; GFX6-LABEL: name: load_constant_s32_from_4_gep_1024
	; GFX6: liveins: $sgpr0_sgpr1			; GFX6: liveins: $sgpr0_sgpr1
	; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1024			; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
	; GFX6: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)			; GFX6: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
	; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]			; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
	; GFX7-LABEL: name: load_constant_s32_from_4_gep_1024			; GFX7-LABEL: name: load_constant_s32_from_4_gep_1024
	; GFX7: liveins: $sgpr0_sgpr1			; GFX7: liveins: $sgpr0_sgpr1
	; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 256, 0, 0 :: (load 4, addrspace 4)			; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 256, 0, 0 :: (load 4, addrspace 4)
	; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]			; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]
	; GFX8-LABEL: name: load_constant_s32_from_4_gep_1024			; GFX8-LABEL: name: load_constant_s32_from_4_gep_1024
	Show All 24 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1

	; GFX6-LABEL: name: load_constant_s32_from_4_gep_1048575			; GFX6-LABEL: name: load_constant_s32_from_4_gep_1048575
	; GFX6: liveins: $sgpr0_sgpr1			; GFX6: liveins: $sgpr0_sgpr1
	; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048575			; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048575
	; GFX6: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)			; GFX6: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
	; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]			; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
	; GFX7-LABEL: name: load_constant_s32_from_4_gep_1048575			; GFX7-LABEL: name: load_constant_s32_from_4_gep_1048575
	; GFX7: liveins: $sgpr0_sgpr1			; GFX7: liveins: $sgpr0_sgpr1
	; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 262143, 0, 0 :: (load 4, addrspace 4)			; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 262143, 0, 0 :: (load 4, addrspace 4)
	; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]			; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]
	; GFX8-LABEL: name: load_constant_s32_from_4_gep_1048575			; GFX8-LABEL: name: load_constant_s32_from_4_gep_1048575
	Show All 24 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1

	; GFX6-LABEL: name: load_constant_s32_from_4_gep_1048576			; GFX6-LABEL: name: load_constant_s32_from_4_gep_1048576
	; GFX6: liveins: $sgpr0_sgpr1			; GFX6: liveins: $sgpr0_sgpr1
	; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576			; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576
	; GFX6: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)			; GFX6: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
	; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]			; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
	; GFX7-LABEL: name: load_constant_s32_from_4_gep_1048576			; GFX7-LABEL: name: load_constant_s32_from_4_gep_1048576
	; GFX7: liveins: $sgpr0_sgpr1			; GFX7: liveins: $sgpr0_sgpr1
	; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 262144, 0, 0 :: (load 4, addrspace 4)			; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 262144, 0, 0 :: (load 4, addrspace 4)
	; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]			; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]
	; GFX8-LABEL: name: load_constant_s32_from_4_gep_1048576			; GFX8-LABEL: name: load_constant_s32_from_4_gep_1048576
	; GFX8: liveins: $sgpr0_sgpr1			; GFX8: liveins: $sgpr0_sgpr1
	; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576			; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576
	; GFX8: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)			; GFX8: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
	; GFX8: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]			; GFX8: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
	; GFX10-LABEL: name: load_constant_s32_from_4_gep_1048576			; GFX10-LABEL: name: load_constant_s32_from_4_gep_1048576
	; GFX10: liveins: $sgpr0_sgpr1			; GFX10: liveins: $sgpr0_sgpr1
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576			; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576
	; GFX10: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)			; GFX10: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
	; GFX10: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]			; GFX10: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
	%0:sgpr(p4) = COPY $sgpr0_sgpr1			%0:sgpr(p4) = COPY $sgpr0_sgpr1
	%1:sgpr(s64) = G_CONSTANT i64 1048576			%1:sgpr(s64) = G_CONSTANT i64 1048576
	%2:sgpr(p4) = G_GEP %0, %1			%2:sgpr(p4) = G_GEP %0, %1
	%3:sgpr(s32) = G_LOAD %2 :: (load 4, align 4, addrspace 4)			%3:sgpr(s32) = G_LOAD %2 :: (load 4, align 4, addrspace 4)
	$sgpr0 = COPY %3			$sgpr0 = COPY %3

	...			...

	---			---

	name: load_constant_s32_from_4_gep_1073741823			name: load_constant_s32_from_4_gep_1073741823
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1

	; GFX6-LABEL: name: load_constant_s32_from_4_gep_1073741823			; GFX6-LABEL: name: load_constant_s32_from_4_gep_1073741823
	; GFX6: liveins: $sgpr0_sgpr1			; GFX6: liveins: $sgpr0_sgpr1
	; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1073741823			; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741823
	; GFX6: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)			; GFX6: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
	; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]			; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
	; GFX7-LABEL: name: load_constant_s32_from_4_gep_1073741823			; GFX7-LABEL: name: load_constant_s32_from_4_gep_1073741823
	; GFX7: liveins: $sgpr0_sgpr1			; GFX7: liveins: $sgpr0_sgpr1
	; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 268435455, 0, 0 :: (load 4, addrspace 4)			; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 268435455, 0, 0 :: (load 4, addrspace 4)
	; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]			; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]
	; GFX8-LABEL: name: load_constant_s32_from_4_gep_1073741823			; GFX8-LABEL: name: load_constant_s32_from_4_gep_1073741823
	; GFX8: liveins: $sgpr0_sgpr1			; GFX8: liveins: $sgpr0_sgpr1
	; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1073741823			; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741823
	; GFX8: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)			; GFX8: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
	; GFX8: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]			; GFX8: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
	; GFX10-LABEL: name: load_constant_s32_from_4_gep_1073741823			; GFX10-LABEL: name: load_constant_s32_from_4_gep_1073741823
	; GFX10: liveins: $sgpr0_sgpr1			; GFX10: liveins: $sgpr0_sgpr1
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1			; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
	; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1073741823			; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741823
	; GFX10: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)			; GFX10: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
	; GFX10: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]			; GFX10: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
	%0:sgpr(p4) = COPY $sgpr0_sgpr1			%0:sgpr(p4) = COPY $sgpr0_sgpr1
	%1:sgpr(s64) = G_CONSTANT i64 1073741823			%1:sgpr(s64) = G_CONSTANT i64 1073741823
	%2:sgpr(p4) = G_GEP %0, %1			%2:sgpr(p4) = G_GEP %0, %1
	%3:sgpr(s32) = G_LOAD %2 :: (load 4, align 4, addrspace 4)			%3:sgpr(s32) = G_LOAD %2 :: (load 4, align 4, addrspace 4)
	$sgpr0 = COPY %3			$sgpr0 = COPY %3

	...			...

test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir

	Show All 19 Lines
	# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0, 0			# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0, 0
	# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0, 0			# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0, 0

	# Max immediate offset for SI			# Max immediate offset for SI
	# SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0, 0			# SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0, 0
	# VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0, 0			# VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0, 0

	# Immediate overflow for SI			# Immediate overflow for SI
	# SI: [[K1024:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1024			# SI: [[K1024:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
	# SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0			# SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0
	# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0			# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0
	# VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0			# VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0

	# Max immediate offset for VI			# Max immediate offset for VI
	# SI: [[K1048572:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048572			# SI: [[K1048572:%[0-9]+]]:sreg_32 = S_MOV_B32 1048572
	# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143			# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143
	# VI: S_LOAD_DWORD_IMM [[PTR]], 1048572			# VI: S_LOAD_DWORD_IMM [[PTR]], 1048572

	#			#
	# Immediate overflow for VI			# Immediate overflow for VI
	# SIVI: [[K1048576:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576			# SIVI: [[K1048576:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576
	# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0			# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0
	# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0			# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0

	# Max immediate for CI			# Max immediate for CI
	# SIVI: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4294967292			# SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292
	# SIVI: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 3			# SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 3
	# SIVI: [[K:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1			# SIVI: [[K:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
	# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub0			# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub0
	# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub0			# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub0
	# SIVI-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]			# SIVI-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
	# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub1			# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub1
	# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub1			# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub1
	# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]			# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
	# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1			# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
	# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0			# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0
	# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0, 0			# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0, 0

	# Immediate overflow for CI			# Immediate overflow for CI
	# GCN: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0			# GCN: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0
	# GCN: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4			# GCN: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 4
	# GCN: [[K:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1			# GCN: [[K:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
	# GCN-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub0			# GCN-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub0
	# GCN-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub0			# GCN-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub0
	# GCN-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]			# GCN-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
	# GCN-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub1			# GCN-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub1
	# GCN-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub1			# GCN-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub1
	# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]			# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
	# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1			# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
	# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0			# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0

	# Max 32-bit byte offset			# Max 32-bit byte offset
	# SIVI: [[K4294967292:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4294967292			# SIVI: [[K4294967292:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292
	# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0			# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0
	# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0			# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0

	# Overflow 32-bit byte offset			# Overflow 32-bit byte offset
	# SIVI: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0			# SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0
	# SIVI: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1			# SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 1
	# SIVI: [[K:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1			# SIVI: [[K:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
	# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub0			# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub0
	# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub0			# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub0
	# SIVI-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]			# SIVI-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
	# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub1			# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub1
	# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub1			# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub1
	# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]			# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
	# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1			# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
	▲ Show 20 Lines • Show All 126 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir

	Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	name: lshr_s32_sv			name: lshr_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX6-LABEL: name: lshr_s32_sv			; GFX6-LABEL: name: lshr_s32_sv
	; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX6: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	; GFX7-LABEL: name: lshr_s32_sv			; GFX7-LABEL: name: lshr_s32_sv
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX7: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX7: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	; GFX8-LABEL: name: lshr_s32_sv			; GFX8-LABEL: name: lshr_s32_sv
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	; GFX9-LABEL: name: lshr_s32_sv			; GFX9-LABEL: name: lshr_s32_sv
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	; GFX10-LABEL: name: lshr_s32_sv			; GFX10-LABEL: name: lshr_s32_sv
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_LSHR %0, %1			%2:vgpr(s32) = G_LSHR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: lshr_s32_vs			name: lshr_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX6-LABEL: name: lshr_s32_vs			; GFX6-LABEL: name: lshr_s32_vs
	; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX6: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	; GFX7-LABEL: name: lshr_s32_vs			; GFX7-LABEL: name: lshr_s32_vs
	; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX7: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX7: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	; GFX8-LABEL: name: lshr_s32_vs			; GFX8-LABEL: name: lshr_s32_vs
	; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	; GFX9-LABEL: name: lshr_s32_vs			; GFX9-LABEL: name: lshr_s32_vs
	; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	; GFX10-LABEL: name: lshr_s32_vs			; GFX10-LABEL: name: lshr_s32_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_LSHR %0, %1			%2:vgpr(s32) = G_LSHR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0_vgpr1			liveins: $sgpr0, $vgpr0_vgpr1
	; GFX6-LABEL: name: lshr_s64_vs			; GFX6-LABEL: name: lshr_s64_vs
	; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec			; GFX6: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_LSHR_B64_]]			; GFX6: S_ENDPGM 0, implicit [[V_LSHR_B64_]]
	; GFX7-LABEL: name: lshr_s64_vs			; GFX7-LABEL: name: lshr_s64_vs
	; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec			; GFX7: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_LSHR_B64_]]			; GFX7: S_ENDPGM 0, implicit [[V_LSHR_B64_]]
	; GFX8-LABEL: name: lshr_s64_vs			; GFX8-LABEL: name: lshr_s64_vs
	; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]
	; GFX9-LABEL: name: lshr_s64_vs			; GFX9-LABEL: name: lshr_s64_vs
	; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHRREV_B64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B64_]]
	; GFX10-LABEL: name: lshr_s64_vs			; GFX10-LABEL: name: lshr_s64_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec			; GFX10: [[V_LSHR_B64_:%[0-9]+]]:vreg_64 = V_LSHR_B64 [[COPY]], [[COPY1]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHR_B64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHR_B64_]]
	%0:vgpr(s64) = COPY $vgpr0_vgpr1			%0:vgpr(s64) = COPY $vgpr0_vgpr1
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s64) = G_LSHR %0, %1			%2:vgpr(s64) = G_LSHR %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 40 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir

	Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX8-LABEL: name: lshr_s16_s16_vs			; GFX8-LABEL: name: lshr_s16_s16_vs
	; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
	; GFX9-LABEL: name: lshr_s16_s16_vs			; GFX9-LABEL: name: lshr_s16_s16_vs
	; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
	; GFX10-LABEL: name: lshr_s16_s16_vs			; GFX10-LABEL: name: lshr_s16_s16_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s16) = G_TRUNC %0			%2:vgpr(s16) = G_TRUNC %0
	%3:sgpr(s16) = G_TRUNC %1			%3:sgpr(s16) = G_TRUNC %1
	%4:vgpr(s16) = G_LSHR %2, %3			%4:vgpr(s16) = G_LSHR %2, %3
	S_ENDPGM 0, implicit %4			S_ENDPGM 0, implicit %4
	▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
	name: lshr_s16_s16_sv			name: lshr_s16_s16_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX8-LABEL: name: lshr_s16_s16_sv			; GFX8-LABEL: name: lshr_s16_s16_sv
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
	; GFX9-LABEL: name: lshr_s16_s16_sv			; GFX9-LABEL: name: lshr_s16_s16_sv
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
	; GFX10-LABEL: name: lshr_s16_s16_sv			; GFX10-LABEL: name: lshr_s16_s16_sv
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:sgpr(s16) = G_TRUNC %0			%2:sgpr(s16) = G_TRUNC %0
	%3:vgpr(s16) = G_TRUNC %1			%3:vgpr(s16) = G_TRUNC %1
	%4:vgpr(s16) = G_LSHR %2, %3			%4:vgpr(s16) = G_LSHR %2, %3
	Show All 35 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir

	Show All 36 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: test_merge_values_v_s64_s_s32_v_s32			; GCN-LABEL: name: test_merge_values_v_s64_s_s32_v_s32
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s64) = G_MERGE_VALUES %0, %1			%2:vgpr(s64) = G_MERGE_VALUES %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_merge_values_v_s64_v_s32_s_s32			name: test_merge_values_v_s64_v_s32_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GCN-LABEL: name: test_merge_values_v_s64_v_s32_s_s32			; GCN-LABEL: name: test_merge_values_v_s64_v_s32_s_s32
	; GCN: liveins: $sgpr0, $vgpr0			; GCN: liveins: $sgpr0, $vgpr0
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s64) = G_MERGE_VALUES %0, %1			%2:vgpr(s64) = G_MERGE_VALUES %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_merge_values_s_s64_s_s32_s_s32			name: test_merge_values_s_s64_s_s32_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1

	; GCN-LABEL: name: test_merge_values_s_s64_s_s32_s_s32			; GCN-LABEL: name: test_merge_values_s_s64_s_s32_s_s32
	; GCN: liveins: $sgpr0, $sgpr1			; GCN: liveins: $sgpr0, $sgpr1
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = COPY $sgpr1			%1:sgpr(s32) = COPY $sgpr1
	%2:sgpr(s64) = G_MERGE_VALUES %0, %1			%2:sgpr(s64) = G_MERGE_VALUES %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_merge_values_s_s64_undef_s_s32_s_s32			name: test_merge_values_s_s64_undef_s_s32_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; GCN-LABEL: name: test_merge_values_s_s64_undef_s_s32_s_s32			; GCN-LABEL: name: test_merge_values_s_s64_undef_s_s32_s_s32
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE undef %2:sreg_32_xm0, %subreg.sub0, [[COPY]], %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE undef %2:sreg_32, %subreg.sub0, [[COPY]], %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:sgpr(s64) = G_MERGE_VALUES undef %0:sgpr(s32), %1			%2:sgpr(s64) = G_MERGE_VALUES undef %0:sgpr(s32), %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_merge_values_s_s64_s_s32_undef_s_s32			name: test_merge_values_s_s64_s_s32_undef_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; GCN-LABEL: name: test_merge_values_s_s64_s_s32_undef_s_s32			; GCN-LABEL: name: test_merge_values_s_s64_s_s32_undef_s_s32
	; GCN: liveins: $sgpr0			; GCN: liveins: $sgpr0
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32_xm0, %subreg.sub1			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32, %subreg.sub1
	; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]			; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%2:sgpr(s64) = G_MERGE_VALUES %0, undef %1:sgpr(s32),			%2:sgpr(s64) = G_MERGE_VALUES %0, undef %1:sgpr(s32),
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: test_merge_values_s_s96_s_s32_s_s32_s_s32			name: test_merge_values_s_s96_s_s32_s_s32_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $sgpr2			liveins: $sgpr0, $sgpr1, $sgpr2

	; GCN-LABEL: name: test_merge_values_s_s96_s_s32_s_s32_s_s32			; GCN-LABEL: name: test_merge_values_s_s96_s_s32_s_s32_s_s32
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2
	; GCN: $sgpr0_sgpr1_sgpr2 = COPY [[REG_SEQUENCE]]			; GCN: $sgpr0_sgpr1_sgpr2 = COPY [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = COPY $sgpr1			%1:sgpr(s32) = COPY $sgpr1
	%2:sgpr(s32) = COPY $sgpr2			%2:sgpr(s32) = COPY $sgpr2
	%3:sgpr(s96) = G_MERGE_VALUES %0, %1, %2			%3:sgpr(s96) = G_MERGE_VALUES %0, %1, %2
	$sgpr0_sgpr1_sgpr2 = COPY %3			$sgpr0_sgpr1_sgpr2 = COPY %3
	...			...
	Show All 29 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3			liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

	; GCN-LABEL: name: test_merge_values_s_s128_s_s32_s_s32_s_s32_s_s32			; GCN-LABEL: name: test_merge_values_s_s128_s_s32_s_s32_s_s32_s_s32
	; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3			; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
	; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3			; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
	; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]			; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = COPY $sgpr1			%1:sgpr(s32) = COPY $sgpr1
	%2:sgpr(s32) = COPY $sgpr2			%2:sgpr(s32) = COPY $sgpr2
	%3:sgpr(s32) = COPY $sgpr3			%3:sgpr(s32) = COPY $sgpr3
	%4:sgpr(s128) = G_MERGE_VALUES %0, %1, %2, %3			%4:sgpr(s128) = G_MERGE_VALUES %0, %1, %2, %3
	$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4			$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
	▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4			liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4

	; GCN-LABEL: name: test_merge_values_s_s160_s_s32_s_s32_s_s32_s_s32_s_s32			; GCN-LABEL: name: test_merge_values_s_s160_s_s32_s_s32_s_s32_s_s32_s_s32
	; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4			; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
	; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3			; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
	; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4			; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_160 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_160 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3, [[COPY4]], %subreg.sub4
	; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY [[REG_SEQUENCE]]			; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4 = COPY [[REG_SEQUENCE]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = COPY $sgpr1			%1:sgpr(s32) = COPY $sgpr1
	%2:sgpr(s32) = COPY $sgpr2			%2:sgpr(s32) = COPY $sgpr2
	%3:sgpr(s32) = COPY $sgpr3			%3:sgpr(s32) = COPY $sgpr3
	%4:sgpr(s32) = COPY $sgpr4			%4:sgpr(s32) = COPY $sgpr4
	%5:sgpr(s160) = G_MERGE_VALUES %0, %1, %2, %3, %4			%5:sgpr(s160) = G_MERGE_VALUES %0, %1, %2, %3, %4
	▲ Show 20 Lines • Show All 286 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir

	Show All 23 Lines
	name: mul_s32_sv			name: mul_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: mul_s32_sv			; GCN-LABEL: name: mul_s32_sv
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MUL_LO_U32_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MUL_LO_U32_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MUL_LO_U32_]]			; GCN: S_ENDPGM 0, implicit [[V_MUL_LO_U32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_MUL %0, %1			%2:vgpr(s32) = G_MUL %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: mul_s32_vs			name: mul_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: mul_s32_vs			; GCN-LABEL: name: mul_s32_vs
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MUL_LO_U32_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MUL_LO_U32_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MUL_LO_U32_]]			; GCN: S_ENDPGM 0, implicit [[V_MUL_LO_U32_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_MUL %0, %1			%2:vgpr(s32) = G_MUL %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

Show All 22 Lines	bb.0:
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]		; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc		; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc
; WAVE32: liveins: $vgpr0, $vgpr1		; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec		; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec		; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec		; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]		; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_CONSTANT i32 0		%2:vgpr(s32) = G_CONSTANT i32 0
%3:vcc(s1) = G_ICMP intpred(eq), %0, %2		%3:vcc(s1) = G_ICMP intpred(eq), %0, %2
%4:vcc(s1) = G_ICMP intpred(eq), %1, %2		%4:vcc(s1) = G_ICMP intpred(eq), %1, %2
%5:vcc(s1) = G_OR %3, %4		%5:vcc(s1) = G_OR %3, %4
S_ENDPGM 0, implicit %5		S_ENDPGM 0, implicit %5
...		...

---		---

name: or_s1_sgpr_sgpr_sgpr		name: or_s1_sgpr_sgpr_sgpr
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1		liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: or_s1_sgpr_sgpr_sgpr		; WAVE64-LABEL: name: or_s1_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1		; WAVE64: liveins: $sgpr0, $sgpr1
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]		; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]		; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
; WAVE32-LABEL: name: or_s1_sgpr_sgpr_sgpr		; WAVE32-LABEL: name: or_s1_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1		; WAVE32: liveins: $sgpr0, $sgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]		; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s1) = G_TRUNC %0		%2:sgpr(s1) = G_TRUNC %0
%3:sgpr(s1) = G_TRUNC %1		%3:sgpr(s1) = G_TRUNC %1
%4:sgpr(s1) = G_OR %2, %3		%4:sgpr(s1) = G_OR %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
Show All 40 Lines
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1		liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: or_s16_sgpr_sgpr_sgpr		; WAVE64-LABEL: name: or_s16_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1		; WAVE64: liveins: $sgpr0, $sgpr1
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]		; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]		; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
; WAVE32-LABEL: name: or_s16_sgpr_sgpr_sgpr		; WAVE32-LABEL: name: or_s16_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1		; WAVE32: liveins: $sgpr0, $sgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]		; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s16) = G_TRUNC %0		%2:sgpr(s16) = G_TRUNC %0
%3:sgpr(s16) = G_TRUNC %1		%3:sgpr(s16) = G_TRUNC %1
%4:sgpr(s16) = G_OR %2, %3		%4:sgpr(s16) = G_OR %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Lines

body: \|		body: \|
bb.0:		bb.0:
; WAVE64-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc		; WAVE64-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 undef %1:sreg_64, undef %2:sreg_64		; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 undef %1:sreg_64, undef %2:sreg_64
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
; WAVE32-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc		; WAVE32-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0		; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 undef %1:sreg_32, undef %2:sreg_32
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
%2:vcc(s1) = G_OR undef %0:vcc(s1), undef %1:vcc(s1)		%2:vcc(s1) = G_OR undef %0:vcc(s1), undef %1:vcc(s1)
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---

name: or_s1_sgpr_undef_sgpr_undef_sgpr		name: or_s1_sgpr_undef_sgpr_undef_sgpr
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines	bb.0:
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc		; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc
; WAVE32: liveins: $vgpr0, $vgpr1		; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s1) = G_TRUNC %0		%2:vgpr(s1) = G_TRUNC %0
%3:vgpr(s1) = G_TRUNC %1		%3:vgpr(s1) = G_TRUNC %1
%4:vcc(s1) = COPY %2		%4:vcc(s1) = COPY %2
%5:vcc(s1) = COPY %3		%5:vcc(s1) = COPY %3
%6:vcc(s1) = G_OR %4, %5		%6:vcc(s1) = G_OR %4, %5
Show All 11 Lines
tracksRegLiveness: true		tracksRegLiveness: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0

; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32		; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE64: liveins: $vgpr0		; WAVE64: liveins: $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; WAVE64: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]]		; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]]
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY1]], [[COPY2]]		; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
; WAVE64: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]		; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY2]]
; WAVE64: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY3]]		; WAVE64: S_ENDPGM 0, implicit [[COPY3]]
; WAVE64: S_ENDPGM 0, implicit [[COPY4]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32		; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE32: liveins: $vgpr0		; WAVE32: liveins: $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
		; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)		%0:vgpr(s1) = G_TRUNC %1(s32)
%2:sgpr(s1) = G_CONSTANT i1 true		%2:sgpr(s1) = G_CONSTANT i1 true
%6:sgpr(s32) = G_CONSTANT i32 0		%6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF		%7:sgpr(p1) = G_IMPLICIT_DEF
%9:vcc(s1) = COPY %0(s1)		%9:vcc(s1) = COPY %0(s1)
%10:vcc(s1) = COPY %2(s1)		%10:vcc(s1) = COPY %2(s1)
%8:vcc(s1) = G_OR %9, %10		%8:vcc(s1) = G_OR %9, %10
Show All 10 Lines
tracksRegLiveness: true		tracksRegLiveness: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0

; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64		; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE64: liveins: $vgpr0		; WAVE64: liveins: $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B64_]]		; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]		; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64		; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE32: liveins: $vgpr0		; WAVE32: liveins: $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]]		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[COPY1]], [[COPY2]]		; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]		; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
; WAVE32: S_ENDPGM 0, implicit [[COPY3]]		; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)		%0:vgpr(s1) = G_TRUNC %1(s32)
%2:sgpr(s1) = G_CONSTANT i1 true		%2:sgpr(s1) = G_CONSTANT i1 true
%6:sgpr(s32) = G_CONSTANT i32 0		%6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF		%7:sgpr(p1) = G_IMPLICIT_DEF
%9:vcc(s1) = COPY %0(s1)		%9:vcc(s1) = COPY %0(s1)
%10:vcc(s1) = COPY %2(s1)		%10:vcc(s1) = COPY %2(s1)
%8:vcc(s1) = G_OR %9, %10		%8:vcc(s1) = G_OR %9, %10
%3:sreg_64_xexec(s1) = COPY %8(s1)		%3:sreg_64_xexec(s1) = COPY %8(s1)
S_ENDPGM 0, implicit %3		S_ENDPGM 0, implicit %3

...		...

test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s -check-prefix=GCN		# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s -check-prefix=GCN

---		---
name: g_phi_s32_ss_sbranch		name: g_phi_s32_ss_sbranch
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true
machineFunctionInfo: {}		machineFunctionInfo: {}
body: \|		body: \|
; GCN-LABEL: name: g_phi_s32_ss_sbranch		; GCN-LABEL: name: g_phi_s32_ss_sbranch
; GCN: bb.0:		; GCN: bb.0:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2		; GCN: liveins: $sgpr0, $sgpr1, $sgpr2
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY3]]		; GCN: $scc = COPY [[COPY3]]
; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.1:		; GCN: bb.1:
; GCN: successors: %bb.2(0x80000000)		; GCN: successors: %bb.2(0x80000000)
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.2:		; GCN: bb.2:
; GCN: [[PHI:%[0-9]+]]:sreg_32_xm0 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1		; GCN: [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; GCN: $sgpr0 = COPY [[PHI]]		; GCN: $sgpr0 = COPY [[PHI]]
; GCN: S_SETPC_B64 undef $sgpr30_sgpr31		; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2		liveins: $sgpr0, $sgpr1, $sgpr2

%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2		%2:sgpr(s32) = COPY $sgpr2
Show All 24 Lines	body: \|
; GCN: bb.0:		; GCN: bb.0:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: liveins: $vgpr0, $vgpr1, $sgpr2		; GCN: liveins: $vgpr0, $vgpr1, $sgpr2
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY3]]		; GCN: $scc = COPY [[COPY3]]
; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.1:		; GCN: bb.1:
; GCN: successors: %bb.2(0x80000000)		; GCN: successors: %bb.2(0x80000000)
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY1]]		; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.2:		; GCN: bb.2:
; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1		; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
; GCN: $vgpr0 = COPY [[PHI]]		; GCN: $vgpr0 = COPY [[PHI]]
; GCN: S_SETPC_B64 undef $sgpr30_sgpr31		; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr2		liveins: $vgpr0, $vgpr1, $sgpr2

Show All 18 Lines

---		---
name: g_phi_s32_sv_sbranch		name: g_phi_s32_sv_sbranch
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true
machineFunctionInfo: {}		machineFunctionInfo: {}
body: \|		body: \|
		; GCN-LABEL: name: g_phi_s32_sv_sbranch
		; GCN: bb.0:
		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
		; GCN: liveins: $sgpr0, $vgpr0, $sgpr1, $sgpr2
		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
		; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
		; GCN: $scc = COPY [[COPY3]]
		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
		; GCN: S_BRANCH %bb.2
		; GCN: bb.1:
		; GCN: successors: %bb.2(0x80000000)
		; GCN: S_BRANCH %bb.2
		; GCN: bb.2:
		; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
		; GCN: $vgpr0 = COPY [[PHI]]
		; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
liveins: $sgpr0, $vgpr0, $sgpr1, $sgpr2		liveins: $sgpr0, $vgpr0, $sgpr1, $sgpr2

%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%2:sgpr(s32) = COPY $sgpr2		%2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = G_CONSTANT i32 0		%3:sgpr(s32) = G_CONSTANT i32 0
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3		%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
Show All 13 Lines

---		---
name: g_phi_s32_vs_sbranch		name: g_phi_s32_vs_sbranch
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true
machineFunctionInfo: {}		machineFunctionInfo: {}
body: \|		body: \|
		; GCN-LABEL: name: g_phi_s32_vs_sbranch
		; GCN: bb.0:
		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
		; GCN: liveins: $sgpr0, $vgpr0, $sgpr1
		; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1
		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
		; GCN: $scc = COPY [[COPY3]]
		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
		; GCN: S_BRANCH %bb.2
		; GCN: bb.1:
		; GCN: successors: %bb.2(0x80000000)
		; GCN: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
		; GCN: S_BRANCH %bb.2
		; GCN: bb.2:
		; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
		; GCN: $vgpr0 = COPY [[PHI]]
		; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
liveins: $sgpr0, $vgpr0, $sgpr1		liveins: $sgpr0, $vgpr0, $sgpr1

%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0		%1:sgpr(s32) = COPY $sgpr0
%2:sgpr(s32) = COPY $sgpr1		%2:sgpr(s32) = COPY $sgpr1
%3:sgpr(s32) = G_CONSTANT i32 0		%3:sgpr(s32) = G_CONSTANT i32 0
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3		%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
Show All 22 Lines	body: \|
; GCN: bb.0:		; GCN: bb.0:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4		; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1		; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3		; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY3]]		; GCN: $scc = COPY [[COPY3]]
; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.1:		; GCN: bb.1:
; GCN: successors: %bb.2(0x80000000)		; GCN: successors: %bb.2(0x80000000)
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.2:		; GCN: bb.2:
; GCN: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1		; GCN: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
Show All 31 Lines	body: \|
; GCN: bb.0:		; GCN: bb.0:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: liveins: $vgpr0, $vgpr1, $sgpr2		; GCN: liveins: $vgpr0, $vgpr1, $sgpr2
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY3]]		; GCN: $scc = COPY [[COPY3]]
; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.1:		; GCN: bb.1:
; GCN: successors: %bb.2(0x80000000)		; GCN: successors: %bb.2(0x80000000)
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY1]]		; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.2:		; GCN: bb.2:
; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1		; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
; GCN: $vgpr0 = COPY [[PHI]]		; GCN: $vgpr0 = COPY [[PHI]]
; GCN: S_SETPC_B64 undef $sgpr30_sgpr31		; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr2		liveins: $vgpr0, $vgpr1, $sgpr2

Show All 18 Lines

---		---
name: g_phi_vcc_s1_sbranch		name: g_phi_vcc_s1_sbranch
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true
machineFunctionInfo: {}		machineFunctionInfo: {}
body: \|		body: \|
		; GCN-LABEL: name: g_phi_vcc_s1_sbranch
		; GCN: bb.0:
		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
		; GCN: liveins: $vgpr0, $vgpr1, $sgpr2
		; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
		; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
		; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
		; GCN: $scc = COPY [[COPY3]]
		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
		; GCN: S_BRANCH %bb.2
		; GCN: bb.1:
		; GCN: successors: %bb.2(0x80000000)
		; GCN: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
		; GCN: S_BRANCH %bb.2
		; GCN: bb.2:
		; GCN: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[V_CMP_EQ_U32_e64_]], %bb.0, [[V_CMP_EQ_U32_e64_1]], %bb.1
		; GCN: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[PHI]]
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr2		liveins: $vgpr0, $vgpr1, $sgpr2

%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:sgpr(s32) = COPY $sgpr2		%2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = G_CONSTANT i32 0		%3:sgpr(s32) = G_CONSTANT i32 0
%4:vcc(s1) = G_ICMP intpred(eq), %0, %3		%4:vcc(s1) = G_ICMP intpred(eq), %0, %3
Show All 17 Lines
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true
machineFunctionInfo: {}		machineFunctionInfo: {}
body: \|		body: \|
; GCN-LABEL: name: phi_s32_ss_sbranch		; GCN-LABEL: name: phi_s32_ss_sbranch
; GCN: bb.0:		; GCN: bb.0:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2		; GCN: liveins: $sgpr0, $sgpr1, $sgpr2
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY3]]		; GCN: $scc = COPY [[COPY3]]
; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.1:		; GCN: bb.1:
; GCN: successors: %bb.2(0x80000000)		; GCN: successors: %bb.2(0x80000000)
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.2:		; GCN: bb.2:
; GCN: [[PHI:%[0-9]+]]:sreg_32_xm0 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1		; GCN: [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
; GCN: $sgpr0 = COPY [[PHI]]		; GCN: $sgpr0 = COPY [[PHI]]
; GCN: S_SETPC_B64 undef $sgpr30_sgpr31		; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2		liveins: $sgpr0, $sgpr1, $sgpr2

%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2		%2:sgpr(s32) = COPY $sgpr2
Show All 24 Lines	body: \|
; GCN: bb.0:		; GCN: bb.0:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: liveins: $vgpr0, $vgpr1, $sgpr2		; GCN: liveins: $vgpr0, $vgpr1, $sgpr2
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY3]]		; GCN: $scc = COPY [[COPY3]]
; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc		; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.1:		; GCN: bb.1:
; GCN: successors: %bb.2(0x80000000)		; GCN: successors: %bb.2(0x80000000)
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY1]]		; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
; GCN: S_BRANCH %bb.2		; GCN: S_BRANCH %bb.2
; GCN: bb.2:		; GCN: bb.2:
; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1		; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
; GCN: $vgpr0 = COPY [[PHI]]		; GCN: $vgpr0 = COPY [[PHI]]
; GCN: S_SETPC_B64 undef $sgpr30_sgpr31		; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr2		liveins: $vgpr0, $vgpr1, $sgpr2

Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s

	---			---
	name: ptr_mask_p3_sgpr_sgpr_1			name: ptr_mask_p3_sgpr_sgpr_1
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_1			; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_1
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2			; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2
	; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc			; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
	; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]			; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
	%0:sgpr(p3) = COPY $sgpr0			%0:sgpr(p3) = COPY $sgpr0
	%1:sgpr(p3) = G_PTR_MASK %0, 1			%1:sgpr(p3) = G_PTR_MASK %0, 1
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1

	...			...

	---			---
	name: ptr_mask_p3_sgpr_sgpr_2			name: ptr_mask_p3_sgpr_sgpr_2
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_2			; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_2
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4			; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4
	; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc			; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
	; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]			; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
	%0:sgpr(p3) = COPY $sgpr0			%0:sgpr(p3) = COPY $sgpr0
	%1:sgpr(p3) = G_PTR_MASK %0, 2			%1:sgpr(p3) = G_PTR_MASK %0, 2
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1

	...			...

	---			---
	name: ptr_mask_p3_sgpr_sgpr_3			name: ptr_mask_p3_sgpr_sgpr_3
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_3			; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_3
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8			; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8
	; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc			; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
	; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]			; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
	%0:sgpr(p3) = COPY $sgpr0			%0:sgpr(p3) = COPY $sgpr0
	%1:sgpr(p3) = G_PTR_MASK %0, 3			%1:sgpr(p3) = G_PTR_MASK %0, 3
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1

	...			...

	---			---
	name: ptr_mask_p3_sgpr_sgpr_4			name: ptr_mask_p3_sgpr_sgpr_4
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_4			; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_4
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16			; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
	; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc			; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
	; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]			; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
	%0:sgpr(p3) = COPY $sgpr0			%0:sgpr(p3) = COPY $sgpr0
	%1:sgpr(p3) = G_PTR_MASK %0, 4			%1:sgpr(p3) = G_PTR_MASK %0, 4
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1

	...			...

	---			---
	name: ptr_mask_p3_sgpr_sgpr_29			name: ptr_mask_p3_sgpr_sgpr_29
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_29			; CHECK-LABEL: name: ptr_mask_p3_sgpr_sgpr_29
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16			; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16
	; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc			; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
	; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]			; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
	%0:sgpr(p3) = COPY $sgpr0			%0:sgpr(p3) = COPY $sgpr0
	%1:sgpr(p3) = G_PTR_MASK %0, 4			%1:sgpr(p3) = G_PTR_MASK %0, 4
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1

	...			...

	---			---
	▲ Show 20 Lines • Show All 331 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ptr_mask_p3_vgpr_sgpr_2			; CHECK-LABEL: name: ptr_mask_p3_vgpr_sgpr_2
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec			; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec
	; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec			; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
	; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]			; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
	%0:sgpr(p3) = COPY $sgpr0			%0:sgpr(p3) = COPY $sgpr0
	%1:vgpr(p3) = G_PTR_MASK %0, 2			%1:vgpr(p3) = G_PTR_MASK %0, 2
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1

	...			...
	Show All 23 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s			# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s
	---			---

	name: ptrtoint_s_p3_to_s_s32			name: ptrtoint_s_p3_to_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ptrtoint_s_p3_to_s_s32			; CHECK-LABEL: name: ptrtoint_s_p3_to_s_s32
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: S_ENDPGM 0, implicit [[COPY]]			; CHECK: S_ENDPGM 0, implicit [[COPY]]
	%0:sgpr(p3) = COPY $sgpr0			%0:sgpr(p3) = COPY $sgpr0
	%1:sgpr(s32) = G_PTRTOINT %0			%1:sgpr(s32) = G_PTRTOINT %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---

	name: ptrtoint_s_p5_to_s_s32			name: ptrtoint_s_p5_to_s_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0

	; CHECK-LABEL: name: ptrtoint_s_p5_to_s_s32			; CHECK-LABEL: name: ptrtoint_s_p5_to_s_s32
	; CHECK: liveins: $sgpr0			; CHECK: liveins: $sgpr0
	; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; CHECK: S_ENDPGM 0, implicit [[COPY]]			; CHECK: S_ENDPGM 0, implicit [[COPY]]
	%0:sgpr(p5) = COPY $sgpr0			%0:sgpr(p5) = COPY $sgpr0
	%1:sgpr(s32) = G_PTRTOINT %0			%1:sgpr(s32) = G_PTRTOINT %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...

	---			---

	▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir

Show All 10 Lines	bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5		liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5

; GCN-LABEL: name: select_s64_scc		; GCN-LABEL: name: select_s64_scc
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3		; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5		; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY4]]		; GCN: $scc = COPY [[COPY4]]
; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc		; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]		; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s64) = COPY $sgpr2_sgpr3		%2:sgpr(s64) = COPY $sgpr2_sgpr3
%3:sgpr(s64) = COPY $sgpr4_sgpr5		%3:sgpr(s64) = COPY $sgpr4_sgpr5
%4:scc(s1) = G_ICMP intpred(eq), %0, %1		%4:scc(s1) = G_ICMP intpred(eq), %0, %1
Show All 12 Lines	bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5		liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5

; GCN-LABEL: name: select_v4s16_scc		; GCN-LABEL: name: select_v4s16_scc
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3		; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5		; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY4]]		; GCN: $scc = COPY [[COPY4]]
; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc		; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]		; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3		%2:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
%3:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5		%3:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
%4:scc(s1) = G_ICMP intpred(eq), %0, %1		%4:scc(s1) = G_ICMP intpred(eq), %0, %1
%5:sgpr(<4 x s16>) = G_SELECT %4, %2, %3		%5:sgpr(<4 x s16>) = G_SELECT %4, %2, %3
S_ENDPGM 0, implicit %5		S_ENDPGM 0, implicit %5

...		...

---		---
name: select_s16_scc		name: select_s16_scc
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3		liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

; GCN-LABEL: name: select_s16_scc		; GCN-LABEL: name: select_s16_scc
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3		; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GCN: S_CMP_EQ_U32 [[COPY2]], [[COPY3]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY2]], [[COPY3]], implicit-def $scc
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY4]]		; GCN: $scc = COPY [[COPY4]]
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc		; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]		; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2		%2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = COPY $sgpr3		%3:sgpr(s32) = COPY $sgpr3
%4:sgpr(s16) = G_TRUNC %0		%4:sgpr(s16) = G_TRUNC %0
Show All 14 Lines	bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3		liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

; GCN-LABEL: name: select_v2s16_scc		; GCN-LABEL: name: select_v2s16_scc
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3		; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $scc		; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
; GCN: $scc = COPY [[COPY4]]		; GCN: $scc = COPY [[COPY4]]
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc		; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc
; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]		; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<2 x s16>) = COPY $sgpr2		%2:sgpr(<2 x s16>) = COPY $sgpr2
%3:sgpr(<2 x s16>) = COPY $sgpr3		%3:sgpr(<2 x s16>) = COPY $sgpr3
%4:scc(s1) = G_ICMP intpred(eq), %0, %1		%4:scc(s1) = G_ICMP intpred(eq), %0, %1
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir

Show All 9 Lines	body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: sext_scc_s1_to_sgpr_s32		; GCN-LABEL: name: sext_scc_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; GCN: $scc = COPY [[COPY1]]		; GCN: $scc = COPY [[COPY1]]
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, -1, implicit $scc		; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, -1, implicit $scc
; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]		; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:scc(s1) = G_ICMP intpred(eq), %0, %0		%1:scc(s1) = G_ICMP intpred(eq), %0, %0
%2:sgpr(s32) = G_SEXT %1		%2:sgpr(s32) = G_SEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---
Show All 23 Lines
name: sext_sgpr_s1_to_sgpr_s32		name: sext_sgpr_s1_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s32		; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_BFE_I32_:%[0-9]+]]:sreg_32_xm0 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc		; GCN: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
; GCN: $sgpr0 = COPY [[S_BFE_I32_]]		; GCN: $sgpr0 = COPY [[S_BFE_I32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0		%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_SEXT %1		%2:sgpr(s32) = G_SEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---

name: sext_sgpr_s1_to_sgpr_s64		name: sext_sgpr_s1_to_sgpr_s64
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s64		; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF		; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1		; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN: [[S_BFE_I64_:%[0-9]+]]:sreg_64_xexec = S_BFE_I64 [[REG_SEQUENCE]], 65536, implicit-def $scc		; GCN: [[S_BFE_I64_:%[0-9]+]]:sreg_64_xexec = S_BFE_I64 [[REG_SEQUENCE]], 65536, implicit-def $scc
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]		; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0		%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s64) = G_SEXT %1		%2:sgpr(s64) = G_SEXT %1
$sgpr0_sgpr1 = COPY %2		$sgpr0_sgpr1 = COPY %2
...		...

---		---

name: sext_sgpr_s8_to_sgpr_s32		name: sext_sgpr_s8_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: sext_sgpr_s8_to_sgpr_s32		; GCN-LABEL: name: sext_sgpr_s8_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_SEXT_I32_I8_:%[0-9]+]]:sreg_32_xm0 = S_SEXT_I32_I8 [[COPY]]		; GCN: [[S_SEXT_I32_I8_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I8 [[COPY]]
; GCN: $sgpr0 = COPY [[S_SEXT_I32_I8_]]		; GCN: $sgpr0 = COPY [[S_SEXT_I32_I8_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s8) = G_TRUNC %0		%1:sgpr(s8) = G_TRUNC %0
%2:sgpr(s32) = G_SEXT %1		%2:sgpr(s32) = G_SEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---

name: sext_sgpr_s16_to_sgpr_s32		name: sext_sgpr_s16_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s32		; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32_xm0 = S_SEXT_I32_I16 [[COPY]]		; GCN: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[COPY]]
; GCN: $sgpr0 = COPY [[S_SEXT_I32_I16_]]		; GCN: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s32) = G_SEXT %1		%2:sgpr(s32) = G_SEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2

...		...

---		---

name: sext_sgpr_s16_to_sgpr_s64		name: sext_sgpr_s16_to_sgpr_s64
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s64		; GCN-LABEL: name: sext_sgpr_s16_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF		; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1		; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN: [[S_BFE_I64_:%[0-9]+]]:sreg_64_xexec = S_BFE_I64 [[REG_SEQUENCE]], 1048576, implicit-def $scc		; GCN: [[S_BFE_I64_:%[0-9]+]]:sreg_64_xexec = S_BFE_I64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]		; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_SEXT %1		%2:sgpr(s64) = G_SEXT %1
$sgpr0_sgpr1 = COPY %2		$sgpr0_sgpr1 = COPY %2
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir

	Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	name: shl_s32_sv			name: shl_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX6-LABEL: name: shl_s32_sv			; GFX6-LABEL: name: shl_s32_sv
	; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	; GFX7-LABEL: name: shl_s32_sv			; GFX7-LABEL: name: shl_s32_sv
	; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX7: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	; GFX8-LABEL: name: shl_s32_sv			; GFX8-LABEL: name: shl_s32_sv
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	; GFX9-LABEL: name: shl_s32_sv			; GFX9-LABEL: name: shl_s32_sv
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	; GFX10-LABEL: name: shl_s32_sv			; GFX10-LABEL: name: shl_s32_sv
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_SHL %0, %1			%2:vgpr(s32) = G_SHL %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: shl_s32_vs			name: shl_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX6-LABEL: name: shl_s32_vs			; GFX6-LABEL: name: shl_s32_vs
	; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	; GFX7-LABEL: name: shl_s32_vs			; GFX7-LABEL: name: shl_s32_vs
	; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX7: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	; GFX8-LABEL: name: shl_s32_vs			; GFX8-LABEL: name: shl_s32_vs
	; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	; GFX9-LABEL: name: shl_s32_vs			; GFX9-LABEL: name: shl_s32_vs
	; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	; GFX10-LABEL: name: shl_s32_vs			; GFX10-LABEL: name: shl_s32_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_SHL %0, %1			%2:vgpr(s32) = G_SHL %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0_vgpr1			liveins: $sgpr0, $vgpr0_vgpr1
	; GFX6-LABEL: name: shl_s64_vs			; GFX6-LABEL: name: shl_s64_vs
	; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec			; GFX6: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_LSHL_B64_]]			; GFX6: S_ENDPGM 0, implicit [[V_LSHL_B64_]]
	; GFX7-LABEL: name: shl_s64_vs			; GFX7-LABEL: name: shl_s64_vs
	; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX7: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec			; GFX7: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec
	; GFX7: S_ENDPGM 0, implicit [[V_LSHL_B64_]]			; GFX7: S_ENDPGM 0, implicit [[V_LSHL_B64_]]
	; GFX8-LABEL: name: shl_s64_vs			; GFX8-LABEL: name: shl_s64_vs
	; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
	; GFX9-LABEL: name: shl_s64_vs			; GFX9-LABEL: name: shl_s64_vs
	; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
	; GFX10-LABEL: name: shl_s64_vs			; GFX10-LABEL: name: shl_s64_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1			; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec			; GFX10: [[V_LSHL_B64_:%[0-9]+]]:vreg_64 = V_LSHL_B64 [[COPY]], [[COPY1]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHL_B64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHL_B64_]]
	%0:vgpr(s64) = COPY $vgpr0_vgpr1			%0:vgpr(s64) = COPY $vgpr0_vgpr1
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s64) = G_SHL %0, %1			%2:vgpr(s64) = G_SHL %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 40 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir

	Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX8-LABEL: name: shl_s16_s16_vs			; GFX8-LABEL: name: shl_s16_s16_vs
	; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]
	; GFX9-LABEL: name: shl_s16_s16_vs			; GFX9-LABEL: name: shl_s16_s16_vs
	; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]
	; GFX10-LABEL: name: shl_s16_s16_vs			; GFX10-LABEL: name: shl_s16_s16_vs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s16) = G_TRUNC %0			%2:vgpr(s16) = G_TRUNC %0
	%3:sgpr(s16) = G_TRUNC %1			%3:sgpr(s16) = G_TRUNC %1
	%4:vgpr(s16) = G_SHL %2, %3			%4:vgpr(s16) = G_SHL %2, %3
	S_ENDPGM 0, implicit %4			S_ENDPGM 0, implicit %4
	▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
	name: shl_s16_s16_sv			name: shl_s16_s16_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX8-LABEL: name: shl_s16_s16_sv			; GFX8-LABEL: name: shl_s16_s16_sv
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX8: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]
	; GFX9-LABEL: name: shl_s16_s16_sv			; GFX9-LABEL: name: shl_s16_s16_sv
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX9: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]
	; GFX10-LABEL: name: shl_s16_s16_sv			; GFX10-LABEL: name: shl_s16_s16_sv
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec			; GFX10: [[V_LSHLREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_e64 [[COPY1]], [[COPY]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B16_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:sgpr(s16) = G_TRUNC %0			%2:sgpr(s16) = G_TRUNC %0
	%3:vgpr(s16) = G_TRUNC %1			%3:vgpr(s16) = G_TRUNC %1
	%4:vgpr(s16) = G_SHL %2, %3			%4:vgpr(s16) = G_SHL %2, %3
	Show All 35 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=WAVE64 %s		# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=WAVE64 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=WAVE32 %s		# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck -check-prefix=WAVE32 %s

---		---

name: sitofp		name: sitofp
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4		liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4

; WAVE64-LABEL: name: sitofp		; WAVE64-LABEL: name: sitofp
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4		; WAVE64: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; WAVE64: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec		; WAVE64: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec
; WAVE64: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec		; WAVE64: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec
; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)		; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)		; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; WAVE32-LABEL: name: sitofp		; WAVE32-LABEL: name: sitofp
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4		; WAVE32: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; WAVE32: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec		; WAVE32: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec
; WAVE32: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec		; WAVE32: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec
; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)		; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)		; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0

▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; WAVE64-LABEL: name: sitofp_s32_to_s16_vs		; WAVE64-LABEL: name: sitofp_s32_to_s16_vs
; WAVE64: liveins: $sgpr0		; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec		; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec		; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]		; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
; WAVE32-LABEL: name: sitofp_s32_to_s16_vs		; WAVE32-LABEL: name: sitofp_s32_to_s16_vs
; WAVE32: liveins: $sgpr0		; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec		; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec		; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]		; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s16) = G_SITOFP %0		%1:vgpr(s16) = G_SITOFP %0
%2:vgpr(s32) = G_ANYEXT %1		%2:vgpr(s32) = G_ANYEXT %1
$vgpr0 = COPY %2		$vgpr0 = COPY %2
...		...
Show All 10 Lines	bb.0:

; WAVE64-LABEL: name: sitofp_s1_to_s32_s_scc		; WAVE64-LABEL: name: sitofp_s1_to_s32_s_scc
; WAVE64: liveins: $sgpr0		; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; WAVE64: $scc = COPY [[COPY1]]		; WAVE64: $scc = COPY [[COPY1]]
; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 3212836864, implicit $scc		; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 3212836864, implicit $scc
; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]		; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
; WAVE32-LABEL: name: sitofp_s1_to_s32_s_scc		; WAVE32-LABEL: name: sitofp_s1_to_s32_s_scc
; WAVE32: liveins: $sgpr0		; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; WAVE32: $scc = COPY [[COPY1]]		; WAVE32: $scc = COPY [[COPY1]]
; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 3212836864, implicit $scc		; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 3212836864, implicit $scc
; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]		; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 0		%1:sgpr(s32) = G_CONSTANT i32 0
%2:scc(s1) = G_ICMP intpred(eq), %0, %1		%2:scc(s1) = G_ICMP intpred(eq), %0, %1
%3:sgpr(s32) = G_SITOFP %2		%3:sgpr(s32) = G_SITOFP %2
$sgpr0 = COPY %3		$sgpr0 = COPY %3
...		...

Show All 9 Lines	bb.0:

; WAVE64-LABEL: name: sitofp_s1_to_s16_to_s_scc		; WAVE64-LABEL: name: sitofp_s1_to_s16_to_s_scc
; WAVE64: liveins: $sgpr0		; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; WAVE64: $scc = COPY [[COPY1]]		; WAVE64: $scc = COPY [[COPY1]]
; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 48128, implicit $scc		; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 48128, implicit $scc
; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]		; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
; WAVE32-LABEL: name: sitofp_s1_to_s16_to_s_scc		; WAVE32-LABEL: name: sitofp_s1_to_s16_to_s_scc
; WAVE32: liveins: $sgpr0		; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; WAVE32: $scc = COPY [[COPY1]]		; WAVE32: $scc = COPY [[COPY1]]
; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 48128, implicit $scc		; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 48128, implicit $scc
; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]		; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 0		%1:sgpr(s32) = G_CONSTANT i32 0
%2:scc(s1) = G_ICMP intpred(eq), %0, %1		%2:scc(s1) = G_ICMP intpred(eq), %0, %1
%3:sgpr(s16) = G_SITOFP %2		%3:sgpr(s16) = G_SITOFP %2
%4:sgpr(s32) = G_ANYEXT %3		%4:sgpr(s32) = G_ANYEXT %3
$sgpr0 = COPY %4		$sgpr0 = COPY %4
...		...
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir

	Show All 23 Lines
	name: smax_s32_sv			name: smax_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: smax_s32_sv			; GCN-LABEL: name: smax_s32_sv
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MAX_I32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MAX_I32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_SMAX %0, %1			%2:vgpr(s32) = G_SMAX %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: smax_s32_vs			name: smax_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: smax_s32_vs			; GCN-LABEL: name: smax_s32_vs
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MAX_I32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MAX_I32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_SMAX %0, %1			%2:vgpr(s32) = G_SMAX %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir

	Show All 23 Lines
	name: smin_s32_sv			name: smin_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: smin_s32_sv			; GCN-LABEL: name: smin_s32_sv
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MIN_I32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MIN_I32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_SMIN %0, %1			%2:vgpr(s32) = G_SMIN %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: smin_s32_vs			name: smin_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: smin_s32_vs			; GCN-LABEL: name: smin_s32_vs
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MIN_I32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MIN_I32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_SMIN %0, %1			%2:vgpr(s32) = G_SMIN %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir

	Show All 30 Lines
	name: smulh_s32_sv			name: smulh_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: smulh_s32_sv			; GCN-LABEL: name: smulh_s32_sv
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MUL_HI_I32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MUL_HI_I32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_I32_]]			; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_I32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_SMULH %0, %1			%2:vgpr(s32) = G_SMULH %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: smulh_s32_vs			name: smulh_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: smulh_s32_vs			; GCN-LABEL: name: smulh_s32_vs
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MUL_HI_I32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MUL_HI_I32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_I32_]]			; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_I32_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_SMULH %0, %1			%2:vgpr(s32) = G_SMULH %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir

Show All 14 Lines	bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4		liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4


; GFX6-LABEL: name: sub_s32		; GFX6-LABEL: name: sub_s32
; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4		; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1		; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc		; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_SUB_I32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec		; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_SUB_I32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_SUB_I32_e64 [[S_SUB_U32_]], %7, 0, implicit $exec		; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_SUB_I32_e64 [[S_SUB_U32_]], %7, 0, implicit $exec
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_SUB_I32_e64 %8, [[COPY2]], 0, implicit $exec		; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_SUB_I32_e64 %8, [[COPY2]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit %9		; GFX6: S_ENDPGM 0, implicit %9
; GFX9-LABEL: name: sub_s32		; GFX9-LABEL: name: sub_s32
; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4		; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1		; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc		; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec		; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
; GFX9: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec		; GFX9: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
; GFX9: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec		; GFX9: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]		; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
; GFX10-LABEL: name: sub_s32		; GFX10-LABEL: name: sub_s32
; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4		; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX10: $vcc_hi = IMPLICIT_DEF		; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1		; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32_xm0 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc		; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX10: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec		; GFX10: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_U32_]], 0, implicit $exec
; GFX10: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec		; GFX10: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_U32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
; GFX10: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec		; GFX10: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]		; GFX10: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:vgpr(s32) = COPY $vgpr0		%2:vgpr(s32) = COPY $vgpr0
%3:vgpr(p1) = COPY $vgpr3_vgpr4		%3:vgpr(p1) = COPY $vgpr3_vgpr4
Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s -check-prefixes=GCN			# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - \| FileCheck %s -check-prefixes=GCN

	---			---

	name: trunc_sgpr_s32_to_s1			name: trunc_sgpr_s32_to_s1
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0
	; GCN-LABEL: name: trunc_sgpr_s32_to_s1			; GCN-LABEL: name: trunc_sgpr_s32_to_s1
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: S_ENDPGM 0, implicit [[COPY]]			; GCN: S_ENDPGM 0, implicit [[COPY]]
	%0:sgpr(s32) =COPY $sgpr0			%0:sgpr(s32) =COPY $sgpr0
	%1:sgpr(s1) = G_TRUNC %0			%1:sgpr(s1) = G_TRUNC %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...
	---			---

	name: trunc_sgpr_s32_to_s16			name: trunc_sgpr_s32_to_s16
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0			liveins: $sgpr0
	; GCN-LABEL: name: trunc_sgpr_s32_to_s16			; GCN-LABEL: name: trunc_sgpr_s32_to_s16
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: S_ENDPGM 0, implicit [[COPY]]			; GCN: S_ENDPGM 0, implicit [[COPY]]
	%0:sgpr(s32) =COPY $sgpr0			%0:sgpr(s32) =COPY $sgpr0
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...
	---			---

	name: trunc_sgpr_s64_to_s32			name: trunc_sgpr_s64_to_s32
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1
	; GCN-LABEL: name: trunc_sgpr_s64_to_s32			; GCN-LABEL: name: trunc_sgpr_s64_to_s32
	; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1			; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: S_ENDPGM 0, implicit [[COPY1]]			; GCN: S_ENDPGM 0, implicit [[COPY1]]
	%0:sgpr(s64) = COPY $sgpr0_sgpr1			%0:sgpr(s64) = COPY $sgpr0_sgpr1
	%1:sgpr(s32) = G_TRUNC %0			%1:sgpr(s32) = G_TRUNC %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...
	---			---

	name: trunc_sgpr_s64_to_s16			name: trunc_sgpr_s64_to_s16
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1
	; GCN-LABEL: name: trunc_sgpr_s64_to_s16			; GCN-LABEL: name: trunc_sgpr_s64_to_s16
	; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1			; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: S_ENDPGM 0, implicit [[COPY1]]			; GCN: S_ENDPGM 0, implicit [[COPY1]]
	%0:sgpr(s64) = COPY $sgpr0_sgpr1			%0:sgpr(s64) = COPY $sgpr0_sgpr1
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...
	---			---

	name: trunc_sgpr_s64_to_s1			name: trunc_sgpr_s64_to_s1
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1
	; GCN-LABEL: name: trunc_sgpr_s64_to_s1			; GCN-LABEL: name: trunc_sgpr_s64_to_s1
	; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1			; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: S_ENDPGM 0, implicit [[COPY1]]			; GCN: S_ENDPGM 0, implicit [[COPY1]]
	%0:sgpr(s64) = COPY $sgpr0_sgpr1			%0:sgpr(s64) = COPY $sgpr0_sgpr1
	%1:sgpr(s1) = G_TRUNC %0			%1:sgpr(s1) = G_TRUNC %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...
	---			---

	name: trunc_sgpr_s96_to_s16			name: trunc_sgpr_s96_to_s16
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1_sgpr2			liveins: $sgpr0_sgpr1_sgpr2
	; GCN-LABEL: name: trunc_sgpr_s96_to_s16			; GCN-LABEL: name: trunc_sgpr_s96_to_s16
	; GCN: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2			; GCN: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: S_ENDPGM 0, implicit [[COPY1]]			; GCN: S_ENDPGM 0, implicit [[COPY1]]
	%0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2			%0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...
	---			---

	name: trunc_sgpr_s96_to_s64			name: trunc_sgpr_s96_to_s64
	Show All 17 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1_sgpr2_sgpr3			liveins: $sgpr0_sgpr1_sgpr2_sgpr3
	; GCN-LABEL: name: trunc_sgpr_s128_to_s16			; GCN-LABEL: name: trunc_sgpr_s128_to_s16
	; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3			; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: S_ENDPGM 0, implicit [[COPY1]]			; GCN: S_ENDPGM 0, implicit [[COPY1]]
	%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3			%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
	%1:sgpr(s16) = G_TRUNC %0			%1:sgpr(s16) = G_TRUNC %0
	S_ENDPGM 0, implicit %1			S_ENDPGM 0, implicit %1
	...			...
	---			---

	name: trunc_sgpr_s128_to_s96			name: trunc_sgpr_s128_to_s96
	▲ Show 20 Lines • Show All 233 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir

	Show All 11 Lines
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1

	; GFX6-LABEL: name: uaddo_s32_s1_sss			; GFX6-LABEL: name: uaddo_s32_s1_sss
	; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GFX6: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GFX6: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GFX6: $scc = COPY [[COPY2]]			; GFX6: $scc = COPY [[COPY2]]
	; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc			; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
	; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]			; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]
	; GFX8-LABEL: name: uaddo_s32_s1_sss			; GFX8-LABEL: name: uaddo_s32_s1_sss
	; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GFX8: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GFX8: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GFX8: $scc = COPY [[COPY2]]			; GFX8: $scc = COPY [[COPY2]]
	; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc			; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
	; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]			; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]
	; GFX9-LABEL: name: uaddo_s32_s1_sss			; GFX9-LABEL: name: uaddo_s32_s1_sss
	; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GFX9: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GFX9: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GFX9: $scc = COPY [[COPY2]]			; GFX9: $scc = COPY [[COPY2]]
	; GFX9: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc			; GFX9: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
	; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]			; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]
	; GFX10-LABEL: name: uaddo_s32_s1_sss			; GFX10-LABEL: name: uaddo_s32_s1_sss
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GFX10: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GFX10: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GFX10: $scc = COPY [[COPY2]]			; GFX10: $scc = COPY [[COPY2]]
	; GFX10: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc			; GFX10: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
	; GFX10: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]			; GFX10: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = COPY $sgpr1			%1:sgpr(s32) = COPY $sgpr1
	%2:sgpr(s32), %3:scc(s1) = G_UADDO %0, %1			%2:sgpr(s32), %3:scc(s1) = G_UADDO %0, %1
	%4:sgpr(s32) = G_SELECT %3, %0, %1			%4:sgpr(s32) = G_SELECT %3, %0, %1
	S_ENDPGM 0, implicit %2, implicit %4			S_ENDPGM 0, implicit %2, implicit %4
	▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GFX6-LABEL: name: uaddo_s32_s1_vsv			; GFX6-LABEL: name: uaddo_s32_s1_vsv
	; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec			; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX8-LABEL: name: uaddo_s32_s1_vsv			; GFX8-LABEL: name: uaddo_s32_s1_vsv
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX8: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec			; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX9-LABEL: name: uaddo_s32_s1_vsv			; GFX9-LABEL: name: uaddo_s32_s1_vsv
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX9: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec			; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX10-LABEL: name: uaddo_s32_s1_vsv			; GFX10-LABEL: name: uaddo_s32_s1_vsv
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX10: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec			; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	Show All 10 Lines
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GFX6-LABEL: name: uaddo_s32_s1_vvs			; GFX6-LABEL: name: uaddo_s32_s1_vvs
	; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX6: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec			; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX8-LABEL: name: uaddo_s32_s1_vvs			; GFX8-LABEL: name: uaddo_s32_s1_vvs
	; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX8: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec			; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX9-LABEL: name: uaddo_s32_s1_vvs			; GFX9-LABEL: name: uaddo_s32_s1_vvs
	; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX9: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec			; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX10-LABEL: name: uaddo_s32_s1_vvs			; GFX10-LABEL: name: uaddo_s32_s1_vvs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX10: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec			; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_ADD_I32_e64_1]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32), %3:vcc(s1) = G_UADDO %0, %1			%2:vgpr(s32), %3:vcc(s1) = G_UADDO %0, %1
	%4:vgpr(s32) = G_CONSTANT i32 0			%4:vgpr(s32) = G_CONSTANT i32 0
	%5:vgpr(s32) = G_CONSTANT i32 1			%5:vgpr(s32) = G_CONSTANT i32 1
	%6:vgpr(s32) = G_SELECT %3, %4, %5			%6:vgpr(s32) = G_SELECT %3, %4, %5
	S_ENDPGM 0, implicit %2, implicit %6			S_ENDPGM 0, implicit %2, implicit %6
	...			...

test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir

Show All 34 Lines
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; WAVE64-LABEL: name: uitofp_s32_to_s32_vs		; WAVE64-LABEL: name: uitofp_s32_to_s32_vs
; WAVE64: liveins: $sgpr0		; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec		; WAVE64: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]		; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
; WAVE32-LABEL: name: uitofp_s32_to_s32_vs		; WAVE32-LABEL: name: uitofp_s32_to_s32_vs
; WAVE32: liveins: $sgpr0		; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec		; WAVE32: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]		; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_UITOFP %0		%1:vgpr(s32) = G_UITOFP %0
$vgpr0 = COPY %1		$vgpr0 = COPY %1
...		...

---		---
Show All 32 Lines
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; WAVE64-LABEL: name: uitofp_s32_to_s16_vs		; WAVE64-LABEL: name: uitofp_s32_to_s16_vs
; WAVE64: liveins: $sgpr0		; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec		; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec		; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]		; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
; WAVE32-LABEL: name: uitofp_s32_to_s16_vs		; WAVE32-LABEL: name: uitofp_s32_to_s16_vs
; WAVE32: liveins: $sgpr0		; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec		; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec		; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]		; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s16) = G_UITOFP %0		%1:vgpr(s16) = G_UITOFP %0
%2:vgpr(s32) = G_ANYEXT %1		%2:vgpr(s32) = G_ANYEXT %1
$vgpr0 = COPY %2		$vgpr0 = COPY %2
...		...
Show All 10 Lines	bb.0:

; WAVE64-LABEL: name: uitofp_s1_to_s32_s_scc		; WAVE64-LABEL: name: uitofp_s1_to_s32_s_scc
; WAVE64: liveins: $sgpr0		; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; WAVE64: $scc = COPY [[COPY1]]		; WAVE64: $scc = COPY [[COPY1]]
; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 1065353216, implicit $scc		; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1065353216, implicit $scc
; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]		; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
; WAVE32-LABEL: name: uitofp_s1_to_s32_s_scc		; WAVE32-LABEL: name: uitofp_s1_to_s32_s_scc
; WAVE32: liveins: $sgpr0		; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; WAVE32: $scc = COPY [[COPY1]]		; WAVE32: $scc = COPY [[COPY1]]
; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 1065353216, implicit $scc		; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1065353216, implicit $scc
; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]		; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 0		%1:sgpr(s32) = G_CONSTANT i32 0
%2:scc(s1) = G_ICMP intpred(eq), %0, %1		%2:scc(s1) = G_ICMP intpred(eq), %0, %1
%3:sgpr(s32) = G_UITOFP %2		%3:sgpr(s32) = G_UITOFP %2
$sgpr0 = COPY %3		$sgpr0 = COPY %3
...		...

Show All 9 Lines	bb.0:

; WAVE64-LABEL: name: uitofp_s1_to_s16_to_s_scc		; WAVE64-LABEL: name: uitofp_s1_to_s16_to_s_scc
; WAVE64: liveins: $sgpr0		; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; WAVE64: $scc = COPY [[COPY1]]		; WAVE64: $scc = COPY [[COPY1]]
; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 15360, implicit $scc		; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 15360, implicit $scc
; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]		; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
; WAVE32-LABEL: name: uitofp_s1_to_s16_to_s_scc		; WAVE32-LABEL: name: uitofp_s1_to_s16_to_s_scc
; WAVE32: liveins: $sgpr0		; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc		; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; WAVE32: $scc = COPY [[COPY1]]		; WAVE32: $scc = COPY [[COPY1]]
; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 15360, implicit $scc		; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 15360, implicit $scc
; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]		; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 0		%1:sgpr(s32) = G_CONSTANT i32 0
%2:scc(s1) = G_ICMP intpred(eq), %0, %1		%2:scc(s1) = G_ICMP intpred(eq), %0, %1
%3:sgpr(s16) = G_UITOFP %2		%3:sgpr(s16) = G_UITOFP %2
%4:sgpr(s32) = G_ANYEXT %3		%4:sgpr(s32) = G_ANYEXT %3
$sgpr0 = COPY %4		$sgpr0 = COPY %4
...		...
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir

	Show All 23 Lines
	name: umax_s32_sv			name: umax_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: umax_s32_sv			; GCN-LABEL: name: umax_s32_sv
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MAX_U32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MAX_U32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_UMAX %0, %1			%2:vgpr(s32) = G_UMAX %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: umax_s32_vs			name: umax_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: umax_s32_vs			; GCN-LABEL: name: umax_s32_vs
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MAX_U32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MAX_U32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_UMAX %0, %1			%2:vgpr(s32) = G_UMAX %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir

	Show All 23 Lines
	name: umin_s32_sv			name: umin_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: umin_s32_sv			; GCN-LABEL: name: umin_s32_sv
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MIN_U32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MIN_U32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_UMIN %0, %1			%2:vgpr(s32) = G_UMIN %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: umin_s32_vs			name: umin_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: umin_s32_vs			; GCN-LABEL: name: umin_s32_vs
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MIN_U32_e64_]]			; GCN: S_ENDPGM 0, implicit [[V_MIN_U32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_UMIN %0, %1			%2:vgpr(s32) = G_UMIN %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir

	Show All 30 Lines
	name: umulh_s32_sv			name: umulh_s32_sv
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: umulh_s32_sv			; GCN-LABEL: name: umulh_s32_sv
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[V_MUL_HI_U32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MUL_HI_U32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_U32_]]			; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_U32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	%2:vgpr(s32) = G_UMULH %0, %1			%2:vgpr(s32) = G_UMULH %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	---			---
	name: umulh_s32_vs			name: umulh_s32_vs
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GCN-LABEL: name: umulh_s32_vs			; GCN-LABEL: name: umulh_s32_vs
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GCN: [[V_MUL_HI_U32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32 [[COPY]], [[COPY1]], implicit $exec			; GCN: [[V_MUL_HI_U32_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32 [[COPY]], [[COPY1]], implicit $exec
	; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_U32_]]			; GCN: S_ENDPGM 0, implicit [[V_MUL_HI_U32_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32) = G_UMULH %0, %1			%2:vgpr(s32) = G_UMULH %0, %1
	S_ENDPGM 0, implicit %2			S_ENDPGM 0, implicit %2
	...			...

	Show All 18 Lines

test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir

	Show All 34 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1

	; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s_s64			; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s_s64
	; GCN: liveins: $sgpr0_sgpr1			; GCN: liveins: $sgpr0_sgpr1
	; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1			; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
	; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]			; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
	%0:sgpr(s64) = COPY $sgpr0_sgpr1			%0:sgpr(s64) = COPY $sgpr0_sgpr1
	%1:sgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0			%1:sgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0
	S_ENDPGM 0, implicit %1, implicit %2			S_ENDPGM 0, implicit %1, implicit %2
	...			...

	---			---
	name: test_unmerge_values_v_s32_s_s32_s_s64			name: test_unmerge_values_v_s32_s_s32_s_s64
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1

	; GCN-LABEL: name: test_unmerge_values_v_s32_s_s32_s_s64			; GCN-LABEL: name: test_unmerge_values_v_s32_s_s32_s_s64
	; GCN: liveins: $sgpr0_sgpr1			; GCN: liveins: $sgpr0_sgpr1
	; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1			; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
	; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]			; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
	%0:sgpr(s64) = COPY $sgpr0_sgpr1			%0:sgpr(s64) = COPY $sgpr0_sgpr1
	%1:vgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0			%1:vgpr(s32), %2:sgpr(s32) = G_UNMERGE_VALUES %0
	S_ENDPGM 0, implicit %1, implicit %2			S_ENDPGM 0, implicit %1, implicit %2
	...			...

	---			---
	name: test_unmerge_values_s_s32_v_s32_s_s64			name: test_unmerge_values_s_s32_v_s32_s_s64
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1			liveins: $sgpr0_sgpr1

	; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64			; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64
	; GCN: liveins: $sgpr0_sgpr1			; GCN: liveins: $sgpr0_sgpr1
	; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1			; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1			; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
	; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]			; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
	%0:sgpr(s64) = COPY $sgpr0_sgpr1			%0:sgpr(s64) = COPY $sgpr0_sgpr1
	%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0			%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES %0
	S_ENDPGM 0, implicit %1, implicit %2			S_ENDPGM 0, implicit %1, implicit %2
	...			...

	---			---
	name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src			name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:

	; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src			; GCN-LABEL: name: test_unmerge_values_s_s32_v_s32_s_s64_undef_src
	; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY undef %2.sub0:sreg_64_xexec			; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY undef %2.sub0:sreg_64_xexec
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY undef %2.sub1:sreg_64_xexec			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY undef %2.sub1:sreg_64_xexec
	; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]]			; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]]
	%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES undef %0:sgpr(s64)			%1:sgpr(s32), %2:vgpr(s32) = G_UNMERGE_VALUES undef %0:sgpr(s64)
	S_ENDPGM 0, implicit %1, implicit %2			S_ENDPGM 0, implicit %1, implicit %2
	...			...

	---			---
	name: test_unmerge_values_s_s32_s_s32_s32_s_s96			name: test_unmerge_values_s_s32_s_s32_s32_s_s96
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1_sgpr2			liveins: $sgpr0_sgpr1_sgpr2

	; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s96			; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s96
	; GCN: liveins: $sgpr0_sgpr1_sgpr2			; GCN: liveins: $sgpr0_sgpr1_sgpr2
	; GCN: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2			; GCN: [[COPY:%[0-9]+]]:sreg_96 = COPY $sgpr0_sgpr1_sgpr2
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
	; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub2			; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub2
	; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]]			; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]]
	%0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2			%0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
	%1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0			%1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0
	S_ENDPGM 0, implicit %1, implicit %2, implicit %3			S_ENDPGM 0, implicit %1, implicit %2, implicit %3
	...			...

	---			---
	name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128			name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	tracksRegLiveness: true			tracksRegLiveness: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1_sgpr2_sgpr3			liveins: $sgpr0_sgpr1_sgpr2_sgpr3

	; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128			; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
	; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3			; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
	; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3			; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
	; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0			; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
	; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1			; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
	; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub2			; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub2
	; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub3			; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub3
	; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]]			; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]]
	%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3			%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
	%1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32), %4:sgpr(s32) = G_UNMERGE_VALUES %0			%1:sgpr(s32), %2:sgpr(s32), %3:sgpr(s32), %4:sgpr(s32) = G_UNMERGE_VALUES %0
	S_ENDPGM 0, implicit %1, implicit %2, implicit %3, implicit %4			S_ENDPGM 0, implicit %1, implicit %2, implicit %3, implicit %4
	...			...

	---			---
	name: test_unmerge_values_s_s64_s_s64_s_s128			name: test_unmerge_values_s_s64_s_s64_s_s128
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test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir

	Show All 11 Lines
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1

	; GFX6-LABEL: name: usubo_s32_s1_sss			; GFX6-LABEL: name: usubo_s32_s1_sss
	; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GFX6: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GFX6: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GFX6: $scc = COPY [[COPY2]]			; GFX6: $scc = COPY [[COPY2]]
	; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc			; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
	; GFX6: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]			; GFX6: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
	; GFX8-LABEL: name: usubo_s32_s1_sss			; GFX8-LABEL: name: usubo_s32_s1_sss
	; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GFX8: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GFX8: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GFX8: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GFX8: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GFX8: $scc = COPY [[COPY2]]			; GFX8: $scc = COPY [[COPY2]]
	; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc			; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
	; GFX8: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]			; GFX8: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
	; GFX9-LABEL: name: usubo_s32_s1_sss			; GFX9-LABEL: name: usubo_s32_s1_sss
	; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GFX9: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GFX9: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GFX9: $scc = COPY [[COPY2]]			; GFX9: $scc = COPY [[COPY2]]
	; GFX9: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc			; GFX9: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
	; GFX9: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]			; GFX9: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
	; GFX10-LABEL: name: usubo_s32_s1_sss			; GFX10-LABEL: name: usubo_s32_s1_sss
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
	; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc			; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
	; GFX10: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $scc			; GFX10: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
	; GFX10: $scc = COPY [[COPY2]]			; GFX10: $scc = COPY [[COPY2]]
	; GFX10: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc			; GFX10: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
	; GFX10: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]			; GFX10: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:sgpr(s32) = COPY $sgpr1			%1:sgpr(s32) = COPY $sgpr1
	%2:sgpr(s32), %3:scc(s1) = G_USUBO %0, %1			%2:sgpr(s32), %3:scc(s1) = G_USUBO %0, %1
	%4:sgpr(s32) = G_SELECT %3, %0, %1			%4:sgpr(s32) = G_SELECT %3, %0, %1
	S_ENDPGM 0, implicit %2, implicit %4			S_ENDPGM 0, implicit %2, implicit %4
	▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GFX6-LABEL: name: usubo_s32_s1_vsv			; GFX6-LABEL: name: usubo_s32_s1_vsv
	; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX6: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec			; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX8-LABEL: name: usubo_s32_s1_vsv			; GFX8-LABEL: name: usubo_s32_s1_vsv
	; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX8: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec			; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX9-LABEL: name: usubo_s32_s1_vsv			; GFX9-LABEL: name: usubo_s32_s1_vsv
	; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX9: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec			; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX10-LABEL: name: usubo_s32_s1_vsv			; GFX10-LABEL: name: usubo_s32_s1_vsv
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX10: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec			; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	%0:sgpr(s32) = COPY $sgpr0			%0:sgpr(s32) = COPY $sgpr0
	%1:vgpr(s32) = COPY $vgpr0			%1:vgpr(s32) = COPY $vgpr0
	Show All 10 Lines
	regBankSelected: true			regBankSelected: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0

	; GFX6-LABEL: name: usubo_s32_s1_vvs			; GFX6-LABEL: name: usubo_s32_s1_vvs
	; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX6: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX6: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec			; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec
	; GFX6: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX6: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX8-LABEL: name: usubo_s32_s1_vvs			; GFX8-LABEL: name: usubo_s32_s1_vvs
	; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX8: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX8: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec			; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec
	; GFX8: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX8: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX9-LABEL: name: usubo_s32_s1_vvs			; GFX9-LABEL: name: usubo_s32_s1_vvs
	; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX9: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX9: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec			; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec
	; GFX9: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX9: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	; GFX10-LABEL: name: usubo_s32_s1_vvs			; GFX10-LABEL: name: usubo_s32_s1_vvs
	; GFX10: $vcc_hi = IMPLICIT_DEF			; GFX10: $vcc_hi = IMPLICIT_DEF
	; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0			; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
	; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0			; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
	; GFX10: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec			; GFX10: [[V_SUB_I32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_SUB_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
	; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec			; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
	; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec			; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
	; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec			; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_I32_e64_1]], implicit $exec
	; GFX10: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]			; GFX10: S_ENDPGM 0, implicit [[V_SUB_I32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
	%0:vgpr(s32) = COPY $vgpr0			%0:vgpr(s32) = COPY $vgpr0
	%1:sgpr(s32) = COPY $sgpr0			%1:sgpr(s32) = COPY $sgpr0
	%2:vgpr(s32), %3:vcc(s1) = G_USUBO %0, %1			%2:vgpr(s32), %3:vcc(s1) = G_USUBO %0, %1
	%4:vgpr(s32) = G_CONSTANT i32 0			%4:vgpr(s32) = G_CONSTANT i32 0
	%5:vgpr(s32) = G_CONSTANT i32 1			%5:vgpr(s32) = G_CONSTANT i32 1
	%6:vgpr(s32) = G_SELECT %3, %4, %5			%6:vgpr(s32) = G_SELECT %3, %4, %5
	S_ENDPGM 0, implicit %2, implicit %6			S_ENDPGM 0, implicit %2, implicit %6
	...			...

test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir

Show All 22 Lines	bb.0:
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]		; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
; WAVE32-LABEL: name: xor_s1_vcc_vcc_vcc		; WAVE32-LABEL: name: xor_s1_vcc_vcc_vcc
; WAVE32: liveins: $vgpr0, $vgpr1		; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec		; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec		; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec		; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]		; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_CONSTANT i32 0		%2:vgpr(s32) = G_CONSTANT i32 0
%3:vcc(s1) = G_ICMP intpred(eq), %0, %2		%3:vcc(s1) = G_ICMP intpred(eq), %0, %2
%4:vcc(s1) = G_ICMP intpred(eq), %1, %2		%4:vcc(s1) = G_ICMP intpred(eq), %1, %2
%5:vcc(s1) = G_XOR %3, %4		%5:vcc(s1) = G_XOR %3, %4
S_ENDPGM 0, implicit %5		S_ENDPGM 0, implicit %5
...		...

---		---

name: xor_s1_sgpr_sgpr_sgpr		name: xor_s1_sgpr_sgpr_sgpr
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1		liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: xor_s1_sgpr_sgpr_sgpr		; WAVE64-LABEL: name: xor_s1_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1		; WAVE64: liveins: $sgpr0, $sgpr1
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]]		; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]		; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
; WAVE32-LABEL: name: xor_s1_sgpr_sgpr_sgpr		; WAVE32-LABEL: name: xor_s1_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1		; WAVE32: liveins: $sgpr0, $sgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]]		; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s1) = G_TRUNC %0		%2:sgpr(s1) = G_TRUNC %0
%3:sgpr(s1) = G_TRUNC %1		%3:sgpr(s1) = G_TRUNC %1
%4:sgpr(s1) = G_XOR %2, %3		%4:sgpr(s1) = G_XOR %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
Show All 40 Lines
regBankSelected: true		regBankSelected: true
tracksRegLiveness: true		tracksRegLiveness: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1		liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: xor_s16_sgpr_sgpr_sgpr		; WAVE64-LABEL: name: xor_s16_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1		; WAVE64: liveins: $sgpr0, $sgpr1
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]]		; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]		; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
; WAVE32-LABEL: name: xor_s16_sgpr_sgpr_sgpr		; WAVE32-LABEL: name: xor_s16_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1		; WAVE32: liveins: $sgpr0, $sgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]]		; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1		%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s16) = G_TRUNC %0		%2:sgpr(s16) = G_TRUNC %0
%3:sgpr(s16) = G_TRUNC %1		%3:sgpr(s16) = G_TRUNC %1
%4:sgpr(s16) = G_XOR %2, %3		%4:sgpr(s16) = G_XOR %2, %3
S_ENDPGM 0, implicit %4		S_ENDPGM 0, implicit %4
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Lines

body: \|		body: \|
bb.0:		bb.0:
; WAVE64-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc		; WAVE64-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 undef %1:sreg_64, undef %2:sreg_64		; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 undef %1:sreg_64, undef %2:sreg_64
; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
; WAVE32-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc		; WAVE32-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0		; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 undef %1:sreg_32, undef %2:sreg_32
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%2:vcc(s1) = G_XOR undef %0:vcc(s1), undef %1:vcc(s1)		%2:vcc(s1) = G_XOR undef %0:vcc(s1), undef %1:vcc(s1)
S_ENDPGM 0, implicit %2		S_ENDPGM 0, implicit %2
...		...

---		---

name: xor_s1_sgpr_undef_sgpr_undef_sgpr		name: xor_s1_sgpr_undef_sgpr_undef_sgpr
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines	bb.0:
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]		; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
; WAVE32-LABEL: name: xor_s1_vcc_copy_to_vcc		; WAVE32-LABEL: name: xor_s1_vcc_copy_to_vcc
; WAVE32: liveins: $vgpr0, $vgpr1		; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]		; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%0:vgpr(s32) = COPY $vgpr0		%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1		%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s1) = G_TRUNC %0		%2:vgpr(s1) = G_TRUNC %0
%3:vgpr(s1) = G_TRUNC %1		%3:vgpr(s1) = G_TRUNC %1
%4:vcc(s1) = COPY %2		%4:vcc(s1) = COPY %2
%5:vcc(s1) = COPY %3		%5:vcc(s1) = COPY %3
%6:vcc(s1) = G_XOR %4, %5		%6:vcc(s1) = G_XOR %4, %5
Show All 11 Lines
tracksRegLiveness: true		tracksRegLiveness: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0

; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32		; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE64: liveins: $vgpr0		; WAVE64: liveins: $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; WAVE64: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]]		; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]]
; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[COPY2]]		; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]
; WAVE64: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]		; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY2]]
; WAVE64: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY3]]		; WAVE64: S_ENDPGM 0, implicit [[COPY3]]
; WAVE64: S_ENDPGM 0, implicit [[COPY4]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32		; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; WAVE32: liveins: $vgpr0		; WAVE32: liveins: $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]		; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]]
		; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)		%0:vgpr(s1) = G_TRUNC %1(s32)
%2:sgpr(s1) = G_CONSTANT i1 true		%2:sgpr(s1) = G_CONSTANT i1 true
%6:sgpr(s32) = G_CONSTANT i32 0		%6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF		%7:sgpr(p1) = G_IMPLICIT_DEF
%9:vcc(s1) = COPY %0(s1)		%9:vcc(s1) = COPY %0(s1)
%10:vcc(s1) = COPY %2(s1)		%10:vcc(s1) = COPY %2(s1)
%8:vcc(s1) = G_XOR %9, %10		%8:vcc(s1) = G_XOR %9, %10
Show All 10 Lines
tracksRegLiveness: true		tracksRegLiveness: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0		liveins: $vgpr0

; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64		; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE64: liveins: $vgpr0		; WAVE64: liveins: $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec		; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]		; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B64_]]		; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B64_]]
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]		; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64		; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
; WAVE32: liveins: $vgpr0		; WAVE32: liveins: $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF		; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1		; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]]		; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[COPY1]], [[COPY2]]		; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
; WAVE32: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]		; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]
; WAVE32: S_ENDPGM 0, implicit [[COPY3]]		; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
%1:vgpr(s32) = COPY $vgpr0		%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)		%0:vgpr(s1) = G_TRUNC %1(s32)
%2:sgpr(s1) = G_CONSTANT i1 true		%2:sgpr(s1) = G_CONSTANT i1 true
%6:sgpr(s32) = G_CONSTANT i32 0		%6:sgpr(s32) = G_CONSTANT i32 0
%7:sgpr(p1) = G_IMPLICIT_DEF		%7:sgpr(p1) = G_IMPLICIT_DEF
%9:vcc(s1) = COPY %0(s1)		%9:vcc(s1) = COPY %0(s1)
%10:vcc(s1) = COPY %2(s1)		%10:vcc(s1) = COPY %2(s1)
%8:vcc(s1) = G_XOR %9, %10		%8:vcc(s1) = G_XOR %9, %10
%3:sreg_64_xexec(s1) = COPY %8(s1)		%3:sreg_64_xexec(s1) = COPY %8(s1)
S_ENDPGM 0, implicit %3		S_ENDPGM 0, implicit %3

...		...

test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

Show All 9 Lines	body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: zext_scc_s1_to_sgpr_s32		; GCN-LABEL: name: zext_scc_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc		; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc		; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
; GCN: $scc = COPY [[COPY1]]		; GCN: $scc = COPY [[COPY1]]
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 1, implicit $scc		; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]		; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:scc(s1) = G_ICMP intpred(eq), %0, %0		%1:scc(s1) = G_ICMP intpred(eq), %0, %0
%2:sgpr(s32) = G_ZEXT %1		%2:sgpr(s32) = G_ZEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---
Show All 23 Lines
name: zext_sgpr_s1_to_sgpr_s32		name: zext_sgpr_s1_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32		; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], 1, implicit-def $scc		; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
; GCN: $sgpr0 = COPY [[S_AND_B32_]]		; GCN: $sgpr0 = COPY [[S_AND_B32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0		%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1		%2:sgpr(s32) = G_ZEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2
...		...

---		---

name: zext_sgpr_s1_to_sgpr_s64		name: zext_sgpr_s1_to_sgpr_s64
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64		; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF		; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1		; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64_xexec = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc		; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64_xexec = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]		; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0		%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s64) = G_ZEXT %1		%2:sgpr(s64) = G_ZEXT %1
$sgpr0_sgpr1 = COPY %2		$sgpr0_sgpr1 = COPY %2
...		...

---		---

name: zext_sgpr_s8_to_sgpr_s32		name: zext_sgpr_s8_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: zext_sgpr_s8_to_sgpr_s32		; GCN-LABEL: name: zext_sgpr_s8_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32_xm0 = S_BFE_U32 [[COPY]], 524288, implicit-def $scc		; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 524288, implicit-def $scc
; GCN: $sgpr0 = COPY [[S_BFE_U32_]]		; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s8) = G_TRUNC %0		%1:sgpr(s8) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1		%2:sgpr(s32) = G_ZEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2

...		...

---		---

name: zext_sgpr_s16_to_sgpr_s32		name: zext_sgpr_s16_to_sgpr_s32
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32		; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32_xm0 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc		; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
; GCN: $sgpr0 = COPY [[S_BFE_U32_]]		; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1		%2:sgpr(s32) = G_ZEXT %1
$sgpr0 = COPY %2		$sgpr0 = COPY %2

...		...

---		---

name: zext_sgpr_s16_to_sgpr_s64		name: zext_sgpr_s16_to_sgpr_s64
legalized: true		legalized: true
regBankSelected: true		regBankSelected: true
body: \|		body: \|
bb.0:		bb.0:
liveins: $sgpr0		liveins: $sgpr0

; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64		; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0		; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF		; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1		; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64_xexec = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc		; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64_xexec = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]		; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
%0:sgpr(s32) = COPY $sgpr0		%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0		%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_ZEXT %1		%2:sgpr(s64) = G_ZEXT %1
$sgpr0_sgpr1 = COPY %2		$sgpr0_sgpr1 = COPY %2
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s \| FileCheck -check-prefix=UNPACKED %s		; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s \| FileCheck -check-prefix=UNPACKED %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s \| FileCheck -check-prefix=PACKED %s		; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s \| FileCheck -check-prefix=PACKED %s

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6		; UNPACKED: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7 + 4095, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7 + 4095, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6		; PACKED: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7 + 4095, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7 + 4095, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; UNPACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6		; UNPACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
; UNPACKED: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY5]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY5]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
; UNPACKED: BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; PACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; PACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; PACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6		; PACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; PACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; PACKED: BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
Show All 11 Lines	define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; UNPACKED: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; UNPACKED: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3		; UNPACKED: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6		; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
; UNPACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2		; UNPACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
; UNPACKED: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY5]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY5]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
; UNPACKED: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1		; UNPACKED: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
; UNPACKED: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3		; UNPACKED: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
; UNPACKED: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec		; UNPACKED: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines	define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
call void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]		; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY6]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY6]], [[COPY4]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095		; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]		; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY6]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY6]], [[COPY4]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096		; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: %11:vgpr_32, dead %21:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; UNPACKED: %11:vgpr_32, dead %21:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
%voffset.add = add i32 %voffset, 16		%voffset.add = add i32 %voffset, 16
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: %11:vgpr_32, dead %22:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; UNPACKED: %11:vgpr_32, dead %22:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]		; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095		; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
%voffset.add = add i32 %voffset, 4095		%voffset.add = add i32 %voffset, 4095
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096		; UNPACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096
; UNPACKED: bb.1 (%ir-block.0):		; UNPACKED: bb.1 (%ir-block.0):
; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; UNPACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; UNPACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; UNPACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; UNPACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: %11:vgpr_32, dead %22:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; UNPACKED: %11:vgpr_32, dead %22:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]		; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1
; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; UNPACKED: BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; UNPACKED: S_ENDPGM 0		; UNPACKED: S_ENDPGM 0
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096		; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096
; PACKED: bb.1 (%ir-block.0):		; PACKED: bb.1 (%ir-block.0):
; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; PACKED: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; PACKED: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; PACKED: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; PACKED: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; PACKED: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; PACKED: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096		; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; PACKED: S_ENDPGM 0		; PACKED: S_ENDPGM 0
%voffset.add = add i32 %voffset, 4096		%voffset.add = add i32 %voffset, 4096
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}
Show All 9 Lines	define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
; UNPACKED: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; UNPACKED: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; UNPACKED: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; UNPACKED: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; UNPACKED: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3		; UNPACKED: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4		; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5		; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6		; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
; UNPACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2		; UNPACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096		; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; UNPACKED: %13:vgpr_32, dead %47:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec		; UNPACKED: %13:vgpr_32, dead %47:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; UNPACKED: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]		; UNPACKED: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY4]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY9]], [[COPY4]], implicit $exec
; UNPACKED: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]		; UNPACKED: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; UNPACKED: [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY10]], [[COPY5]], implicit $exec		; UNPACKED: [[V_LSHRREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY10]], [[COPY5]], implicit $exec
; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3		; UNPACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
; UNPACKED: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1		; UNPACKED: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
; UNPACKED: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3		; UNPACKED: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
; UNPACKED: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec		; UNPACKED: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
Show All 27 Lines	define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
; PACKED: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; PACKED: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; PACKED: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3		; PACKED: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4		; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5		; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
; PACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6		; PACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
; PACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2		; PACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; PACKED: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; PACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; PACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096		; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; PACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; PACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; PACKED: %13:vgpr_32, dead %31:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec		; PACKED: %13:vgpr_32, dead %31:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
; PACKED: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1		; PACKED: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
; PACKED: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3		; PACKED: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
; PACKED: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec		; PACKED: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
; PACKED: bb.2:		; PACKED: bb.2:
; PACKED: successors: %bb.3(0x40000000), %bb.2(0x40000000)		; PACKED: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; PACKED: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec		; PACKED: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec
Show All 26 Lines

test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s \| FileCheck %s		; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s \| FileCheck %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s \| FileCheck %s		; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s \| FileCheck %s

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4095, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4095, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2
; CHECK: BUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4		; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines	define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {
call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %13:vgpr_32, dead %15:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec		; CHECK: %13:vgpr_32, dead %15:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 16		%voffset.add = add i32 %voffset, 16
call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %13:vgpr_32, dead %15:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec		; CHECK: %13:vgpr_32, dead %15:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 4095		%voffset.add = add i32 %voffset, 4095
call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096		; CHECK-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %13:vgpr_32, dead %15:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec		; CHECK: %13:vgpr_32, dead %15:sreg_64_xexec = V_ADD_I32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 4096		%voffset.add = add i32 %voffset, 4096
call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}
Show All 12 Lines	define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32_add_4096(<4 x i32> %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8		; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8
; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2		; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; CHECK: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %15:vgpr_32, dead %33:sreg_64_xexec = V_ADD_I32_e64 [[COPY8]], [[COPY10]], 0, implicit $exec		; CHECK: %15:vgpr_32, dead %33:sreg_64_xexec = V_ADD_I32_e64 [[COPY8]], [[COPY10]], 0, implicit $exec
; CHECK: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1		; CHECK: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
; CHECK: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3		; CHECK: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec		; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
; CHECK: bb.2:		; CHECK: bb.2:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)		; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]].sub0, implicit $exec		; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]].sub0, implicit $exec
Show All 27 Lines

test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s		; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s \| FileCheck %s
; FIXME: Test with SI when argument lowering not broken for f16		; FIXME: Test with SI when argument lowering not broken for f16

; Natural mapping		; Natural mapping
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

; Copies for VGPR arguments		; Copies for VGPR arguments
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float inreg %val, i32 inreg %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float inreg %val, i32 inreg %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr6		; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[COPY5:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr7		; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr8		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr8
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]		; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY7]], [[COPY8]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY7]], [[COPY8]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
}		}

; Waterfall for soffset		; Waterfall for soffset
define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: successors: %bb.2(0x80000000)		; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec		; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
; CHECK: bb.2:		; CHECK: bb.2:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)		; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec		; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines	define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, float %val, i32 %voffset, i32 %soffset) {
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 3)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 3)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2
; CHECK: BUFFER_STORE_DWORDX3_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORDX3_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4		; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORDX4_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORDX4_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_BYTE_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom TargetCustom7, addrspace 4)		; CHECK: BUFFER_STORE_BYTE_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom TargetCustom7, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%val.trunc = trunc i32 %val to i8		%val.trunc = trunc i32 %val to i8
call void @llvm.amdgcn.raw.buffer.store.i8(i8 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.i8(i8 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%val.trunc = trunc i32 %val to i16		%val.trunc = trunc i32 %val to i16
call void @llvm.amdgcn.raw.buffer.store.i16(i16 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.i16(i16 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1		; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines	define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) {
call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4095, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4095, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec		; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4096, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4096, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 16		%voffset.add = add i32 %voffset, 16
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 4095		%voffset.add = add i32 %voffset, 4095
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 4096		%voffset.add = add i32 %voffset, 4096
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 16		%voffset.add = add i32 %voffset, 16
call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 4095		%voffset.add = add i32 %voffset, 4095
call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096		; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1		; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2		; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3		; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
; CHECK: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr4		; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5		; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)		; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
; CHECK: S_ENDPGM 0		; CHECK: S_ENDPGM 0
%voffset.add = add i32 %voffset, 4096		%voffset.add = add i32 %voffset, 4096
call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)		call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
ret void		ret void
}		}

; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.		; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop.
define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000(<4 x i32> %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {		define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000(<4 x i32> %rsrc, float %val, i32 %voffset, i32 inreg %soffset) {
; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000		; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000
; CHECK: bb.1 (%ir-block.0):		; CHECK: bb.1 (%ir-block.0):
; CHECK: successors: %bb.2(0x80000000)		; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5		; CHECK: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1		; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2		; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3		; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4		; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5		; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2		; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3		; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 5000		; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; CHECK: %11:vgpr_32, dead %29:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec		; CHECK: %11:vgpr_32, dead %29:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
; CHECK: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1		; CHECK: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
; CHECK: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3		; CHECK: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec		; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
; CHECK: bb.2:		; CHECK: bb.2:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)		; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec		; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs -stop-after=amdgpu-isel -o - %s \| FileCheck -check-prefix=GCN %s		; RUN: llc -march=amdgcn -verify-machineinstrs -stop-after=amdgpu-isel -o - %s \| FileCheck -check-prefix=GCN %s

define amdgpu_cs void @mmo_offsets0(<4 x i32> addrspace(6)* inreg noalias dereferenceable(18446744073709551615) %arg0, i32 %arg1) {		define amdgpu_cs void @mmo_offsets0(<4 x i32> addrspace(6)* inreg noalias dereferenceable(18446744073709551615) %arg0, i32 %arg1) {
; GCN-LABEL: name: mmo_offsets0		; GCN-LABEL: name: mmo_offsets0
; GCN: bb.0.bb.0:		; GCN: bb.0.bb.0:
; GCN: liveins: $sgpr0, $vgpr0		; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0		; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0		; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0		; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1		; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
; GCN: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM killed [[REG_SEQUENCE]], 0, 0, 0 :: (dereferenceable invariant load 16 from %ir.arg0, addrspace 6)		; GCN: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM killed [[REG_SEQUENCE]], 0, 0, 0 :: (dereferenceable invariant load 16 from %ir.arg0, addrspace 6)
; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 16, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 16, align 1, addrspace 4)
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec		; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
Show All 15 Lines	define amdgpu_cs void @mmo_offsets0(<4 x i32> addrspace(6)* inreg noalias dereferenceable(18446744073709551615) %arg0, i32 %arg1) {
; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 80, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 80, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 80, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 80, align 1, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_OFFEN [[COPY]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_OFFEN [[COPY]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 80, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 80, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 80, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 80, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY]], %subreg.sub1		; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY]], %subreg.sub1
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 96, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 96, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 96, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 96, align 1, addrspace 4)
; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub0		; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; GCN: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_OFFEN [[REG_SEQUENCE1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_OFFEN [[REG_SEQUENCE1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF1]].sub0		; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF1]].sub0
; GCN: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 96, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 96, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF2]].sub0		; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF2]].sub0
; GCN: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 96, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 96, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY5:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF3]].sub0		; GCN: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF3]].sub0
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec		; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
; GCN: BUFFER_ATOMIC_ADD_F32_OFFSET [[V_MOV_B32_e32_1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 112, 0, implicit $exec :: (load store 4 on custom TargetCustom7 + 112, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_F32_OFFSET [[V_MOV_B32_e32_1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 112, 0, implicit $exec :: (load store 4 on custom TargetCustom7 + 112, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_F32_OFFEN [[V_MOV_B32_e32_1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 0, 0, implicit $exec :: (load store 4 on custom TargetCustom7, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_F32_OFFEN [[V_MOV_B32_e32_1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 0, 0, implicit $exec :: (load store 4 on custom TargetCustom7, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_F32_IDXEN [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 112, 0, implicit $exec :: (load store 4 on custom TargetCustom7, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_F32_IDXEN [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 112, 0, implicit $exec :: (load store 4 on custom TargetCustom7, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_F32_IDXEN [[V_MOV_B32_e32_1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 112, 0, implicit $exec :: (load store 4 on custom TargetCustom7, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_F32_IDXEN [[V_MOV_B32_e32_1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 112, 0, implicit $exec :: (load store 4 on custom TargetCustom7, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 128, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 128, align 1, addrspace 4)
; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 64		; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 64
; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_1]], 64, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 128, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_1]], 64, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 128, align 1, addrspace 4)
; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 128		; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 128
; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_2]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 128, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_2]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 128, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_2]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_2]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET4:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[COPY6]], 128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET4:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[COPY6]], 128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 144, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 144, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFSET1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 144, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 144, align 1, addrspace 4)
; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 72		; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 72
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFSET2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFSET [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_3]], 72, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 144, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFSET2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFSET [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_3]], 72, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 144, align 1, addrspace 4)
; GCN: [[S_MOV_B32_4:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 144		; GCN: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 144
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFSET3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 144, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFSET3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 144, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFSET4:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFSET [[S_LOAD_DWORDX4_IMM]], [[COPY7]], 144, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_OFFSET4:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_OFFSET [[S_LOAD_DWORDX4_IMM]], [[COPY7]], 144, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 160, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 160, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 160, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 160, align 1, addrspace 4)
; GCN: [[S_MOV_B32_5:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 80		; GCN: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 80
; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_5]], 80, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 160, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_5]], 80, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 160, align 1, addrspace 4)
; GCN: [[S_MOV_B32_6:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 160		; GCN: [[S_MOV_B32_6:%[0-9]+]]:sreg_32 = S_MOV_B32 160
; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 160, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 160, align 1, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_OFFEN [[COPY]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_OFFEN [[COPY]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_6]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[COPY8]], 160, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_OFFSET [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[COPY8]], 160, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 176, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 176, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 176, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 176, align 1, addrspace 4)
; GCN: [[COPY9:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF4]].sub0		; GCN: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[DEF4]].sub0
; GCN: [[S_MOV_B32_7:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 88		; GCN: [[S_MOV_B32_7:%[0-9]+]]:sreg_32 = S_MOV_B32 88
; GCN: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_7]], 88, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 176, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_7]], 88, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 176, align 1, addrspace 4)
; GCN: [[COPY10:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF5]].sub0		; GCN: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[DEF5]].sub0
; GCN: [[S_MOV_B32_8:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 176		; GCN: [[S_MOV_B32_8:%[0-9]+]]:sreg_32 = S_MOV_B32 176
; GCN: [[DEF6:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF6:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_8]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 176, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_8]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 176, align 1, addrspace 4)
; GCN: [[COPY11:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF6]].sub0		; GCN: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[DEF6]].sub0
; GCN: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_OFFEN [[REG_SEQUENCE1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_8]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_OFFEN [[REG_SEQUENCE1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_8]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY12:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF7]].sub0		; GCN: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[DEF7]].sub0
; GCN: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: [[DEF8:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF8:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], [[COPY13]], 176, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_OFFSET [[REG_SEQUENCE1]], [[S_LOAD_DWORDX4_IMM]], [[COPY13]], 176, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY14:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF8]].sub0		; GCN: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[DEF8]].sub0
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: BUFFER_STORE_DWORDX4_OFFSET_exact killed [[BUFFER_LOAD_DWORDX4_OFFSET1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 192, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 192, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_OFFSET_exact killed [[BUFFER_LOAD_DWORDX4_OFFSET1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 192, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 192, align 1, addrspace 4)
; GCN: [[S_MOV_B32_9:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 96		; GCN: [[S_MOV_B32_9:%[0-9]+]]:sreg_32 = S_MOV_B32 96
; GCN: BUFFER_STORE_DWORDX4_OFFSET_exact killed [[BUFFER_LOAD_DWORDX4_OFFSET2]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_9]], 96, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 192, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_OFFSET_exact killed [[BUFFER_LOAD_DWORDX4_OFFSET2]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_9]], 96, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 192, align 1, addrspace 4)
; GCN: [[S_MOV_B32_10:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 192		; GCN: [[S_MOV_B32_10:%[0-9]+]]:sreg_32 = S_MOV_B32 192
; GCN: BUFFER_STORE_DWORDX4_OFFSET_exact killed [[BUFFER_LOAD_DWORDX4_OFFSET3]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_10]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 192, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_OFFSET_exact killed [[BUFFER_LOAD_DWORDX4_OFFSET3]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_10]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 192, align 1, addrspace 4)
; GCN: BUFFER_STORE_DWORDX4_OFFEN_exact killed [[BUFFER_LOAD_DWORDX4_OFFEN1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_10]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_OFFEN_exact killed [[BUFFER_LOAD_DWORDX4_OFFEN1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_10]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: BUFFER_STORE_DWORDX4_OFFSET_exact killed [[BUFFER_LOAD_DWORDX4_OFFSET4]], [[S_LOAD_DWORDX4_IMM]], [[COPY15]], 192, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_OFFSET_exact killed [[BUFFER_LOAD_DWORDX4_OFFSET4]], [[S_LOAD_DWORDX4_IMM]], [[COPY15]], 192, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFSET1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 208, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 208, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFSET1]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 208, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 208, align 1, addrspace 4)
; GCN: [[S_MOV_B32_11:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 104		; GCN: [[S_MOV_B32_11:%[0-9]+]]:sreg_32 = S_MOV_B32 104
; GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFSET2]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_11]], 104, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 208, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFSET2]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_11]], 104, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 208, align 1, addrspace 4)
; GCN: [[S_MOV_B32_12:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 208		; GCN: [[S_MOV_B32_12:%[0-9]+]]:sreg_32 = S_MOV_B32 208
; GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFSET3]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_12]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 208, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFSET3]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_12]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 208, align 1, addrspace 4)
; GCN: BUFFER_STORE_FORMAT_XYZW_OFFEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFEN1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_12]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_OFFEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFEN1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_12]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFSET4]], [[S_LOAD_DWORDX4_IMM]], [[COPY16]], 208, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_OFFSET_exact killed [[BUFFER_LOAD_FORMAT_XYZW_OFFSET4]], [[S_LOAD_DWORDX4_IMM]], [[COPY16]], 208, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY17]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 224, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 224, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY17]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 224, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 224, align 1, addrspace 4)
; GCN: [[S_MOV_B32_13:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 112		; GCN: [[S_MOV_B32_13:%[0-9]+]]:sreg_32 = S_MOV_B32 112
; GCN: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY18]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_13]], 112, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 224, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY18]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_13]], 112, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 224, align 1, addrspace 4)
; GCN: [[S_MOV_B32_14:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 224		; GCN: [[S_MOV_B32_14:%[0-9]+]]:sreg_32 = S_MOV_B32 224
; GCN: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN4:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY19]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_14]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 224, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN4:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY19]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_14]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 224, align 1, addrspace 4)
; GCN: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[COPY]], %subreg.sub1		; GCN: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[COPY]], %subreg.sub1
; GCN: [[BUFFER_LOAD_DWORDX4_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_BOTHEN [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_14]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_BOTHEN [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_14]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[COPY21:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY21:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN5:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY20]], [[S_LOAD_DWORDX4_IMM]], [[COPY21]], 224, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN5:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY20]], [[S_LOAD_DWORDX4_IMM]], [[COPY21]], 224, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN6:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 224, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN6:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 224, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN7:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 224, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN7:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 224, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY22]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 240, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 240, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN2:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY22]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 240, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 240, align 1, addrspace 4)
; GCN: [[S_MOV_B32_15:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 120		; GCN: [[S_MOV_B32_15:%[0-9]+]]:sreg_32 = S_MOV_B32 120
; GCN: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY23]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_15]], 120, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 240, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN3:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY23]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_15]], 120, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 240, align 1, addrspace 4)
; GCN: [[S_MOV_B32_16:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 240		; GCN: [[S_MOV_B32_16:%[0-9]+]]:sreg_32 = S_MOV_B32 240
; GCN: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN4:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY24]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_16]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 240, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN4:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY24]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_16]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 240, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_16]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_16]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[COPY26:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY26:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN5:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY25]], [[S_LOAD_DWORDX4_IMM]], [[COPY26]], 240, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN5:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY25]], [[S_LOAD_DWORDX4_IMM]], [[COPY26]], 240, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN6:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 240, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN6:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 240, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN7:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 240, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)		; GCN: [[BUFFER_LOAD_FORMAT_XYZW_IDXEN7:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 240, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY27]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 256, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 256, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY27]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 256, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 256, align 1, addrspace 4)
; GCN: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY28]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_2]], 128, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 256, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY28]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_2]], 128, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 256, align 1, addrspace 4)
; GCN: [[S_MOV_B32_17:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256		; GCN: [[S_MOV_B32_17:%[0-9]+]]:sreg_32 = S_MOV_B32 256
; GCN: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY29]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_17]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 256, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY29]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_17]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 256, align 1, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_BOTHEN [[COPY]], [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_17]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_BOTHEN [[COPY]], [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_17]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[COPY31:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY31:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY30]], [[S_LOAD_DWORDX4_IMM]], [[COPY31]], 256, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY30]], [[S_LOAD_DWORDX4_IMM]], [[COPY31]], 256, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 256, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 256, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 256, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_ADD_IDXEN [[COPY]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 256, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[DEF9:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF9:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY32]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 272, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 272, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY32]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 272, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 272, align 1, addrspace 4)
; GCN: [[COPY33:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF9]].sub0		; GCN: [[COPY33:%[0-9]+]]:sreg_32 = COPY [[DEF9]].sub0
; GCN: [[S_MOV_B32_18:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 136		; GCN: [[S_MOV_B32_18:%[0-9]+]]:sreg_32 = S_MOV_B32 136
; GCN: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[DEF10:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF10:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY34]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_18]], 136, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 272, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY34]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_18]], 136, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 272, align 1, addrspace 4)
; GCN: [[COPY35:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF10]].sub0		; GCN: [[COPY35:%[0-9]+]]:sreg_32 = COPY [[DEF10]].sub0
; GCN: [[S_MOV_B32_19:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 272		; GCN: [[S_MOV_B32_19:%[0-9]+]]:sreg_32 = S_MOV_B32 272
; GCN: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[DEF11:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF11:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY36]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_19]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 272, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY36]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_19]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7 + 272, align 1, addrspace 4)
; GCN: [[COPY37:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF11]].sub0		; GCN: [[COPY37:%[0-9]+]]:sreg_32 = COPY [[DEF11]].sub0
; GCN: [[DEF12:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF12:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_19]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_19]], 0, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY38:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF12]].sub0		; GCN: [[COPY38:%[0-9]+]]:sreg_32 = COPY [[DEF12]].sub0
; GCN: [[COPY39:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY39:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[COPY40:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY40:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: [[DEF13:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF13:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY39]], [[S_LOAD_DWORDX4_IMM]], [[COPY40]], 272, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY39]], [[S_LOAD_DWORDX4_IMM]], [[COPY40]], 272, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY41:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF13]].sub0		; GCN: [[COPY41:%[0-9]+]]:sreg_32 = COPY [[DEF13]].sub0
; GCN: [[DEF14:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF14:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 272, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 272, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY42:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF14]].sub0		; GCN: [[COPY42:%[0-9]+]]:sreg_32 = COPY [[DEF14]].sub0
; GCN: [[DEF15:%[0-9]+]]:vreg_64 = IMPLICIT_DEF		; GCN: [[DEF15:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 272, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_ATOMIC_CMPSWAP_IDXEN [[REG_SEQUENCE1]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 272, 0, implicit $exec :: (volatile dereferenceable load store 4 on custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY43:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF15]].sub0		; GCN: [[COPY43:%[0-9]+]]:sreg_32 = COPY [[DEF15]].sub0
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[COPY44:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY44:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN2]], [[COPY44]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 288, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 288, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN2]], [[COPY44]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 288, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 288, align 1, addrspace 4)
; GCN: [[COPY45:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY45:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN3]], [[COPY45]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_4]], 144, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 288, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN3]], [[COPY45]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_4]], 144, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 288, align 1, addrspace 4)
; GCN: [[S_MOV_B32_20:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 288		; GCN: [[S_MOV_B32_20:%[0-9]+]]:sreg_32 = S_MOV_B32 288
; GCN: [[COPY46:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY46:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN4]], [[COPY46]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_20]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 288, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN4]], [[COPY46]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_20]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 288, align 1, addrspace 4)
; GCN: BUFFER_STORE_DWORDX4_BOTHEN_exact killed [[BUFFER_LOAD_DWORDX4_BOTHEN]], [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_20]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_BOTHEN_exact killed [[BUFFER_LOAD_DWORDX4_BOTHEN]], [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_20]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY47:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY47:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[COPY48:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY48:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN5]], [[COPY47]], [[S_LOAD_DWORDX4_IMM]], [[COPY48]], 288, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN5]], [[COPY47]], [[S_LOAD_DWORDX4_IMM]], [[COPY48]], 288, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN6]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 288, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN6]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 288, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN7]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 288, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_DWORDX4_IDXEN_exact killed [[BUFFER_LOAD_DWORDX4_IDXEN7]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 288, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: INLINEASM &"", 1		; GCN: INLINEASM &"", 1
; GCN: [[COPY49:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY49:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN2]], [[COPY49]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 304, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 304, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN2]], [[COPY49]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 304, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 304, align 1, addrspace 4)
; GCN: [[S_MOV_B32_21:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 152		; GCN: [[S_MOV_B32_21:%[0-9]+]]:sreg_32 = S_MOV_B32 152
; GCN: [[COPY50:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY50:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN3]], [[COPY50]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_21]], 152, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 304, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN3]], [[COPY50]], [[S_LOAD_DWORDX4_IMM]], killed [[S_MOV_B32_21]], 152, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 304, align 1, addrspace 4)
; GCN: [[S_MOV_B32_22:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 304		; GCN: [[S_MOV_B32_22:%[0-9]+]]:sreg_32 = S_MOV_B32 304
; GCN: [[COPY51:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY51:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN4]], [[COPY51]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_22]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 304, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN4]], [[COPY51]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_22]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7 + 304, align 1, addrspace 4)
; GCN: BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]], [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_22]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]], [[REG_SEQUENCE2]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_22]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: [[COPY52:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]		; GCN: [[COPY52:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN: [[COPY53:%[0-9]+]]:sreg_32 = COPY [[COPY]]		; GCN: [[COPY53:%[0-9]+]]:sreg_32 = COPY [[COPY]]
; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN5]], [[COPY52]], [[S_LOAD_DWORDX4_IMM]], [[COPY53]], 304, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN5]], [[COPY52]], [[S_LOAD_DWORDX4_IMM]], [[COPY53]], 304, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN6]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 304, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN6]], [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 304, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN7]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 304, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)		; GCN: BUFFER_STORE_FORMAT_XYZW_IDXEN_exact killed [[BUFFER_LOAD_FORMAT_XYZW_IDXEN7]], [[COPY]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 304, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
▲ Show 20 Lines • Show All 190 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll

	; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s -stop-after=amdgpu-isel \| FileCheck -check-prefix=GCN %s			; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s -stop-after=amdgpu-isel \| FileCheck -check-prefix=GCN %s

	; We want to see a BUFFER_LOAD, some register shuffling, and a BUFFER_STORE.			; We want to see a BUFFER_LOAD, some register shuffling, and a BUFFER_STORE.
	; Specifically, we do not want to see a BUFFER_STORE that says "store into			; Specifically, we do not want to see a BUFFER_STORE that says "store into
	; stack" in the middle.			; stack" in the middle.

	define amdgpu_hs void @main([0 x i8] addrspace(6)* inreg %arg) {			define amdgpu_hs void @main([0 x i8] addrspace(6)* inreg %arg) {
	; GCN-LABEL: name: main			; GCN-LABEL: name: main
	; GCN: bb.0.main_body:			; GCN: bb.0.main_body:
	; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0			; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
	; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF			; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
	; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]			; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
	; GCN: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF			; GCN: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
	; GCN: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[DEF1]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)			; GCN: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[DEF1]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
	; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2			; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
	; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1			; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
	; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0			; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
	; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_96 = REG_SEQUENCE killed [[COPY3]], %subreg.sub0, killed [[COPY2]], %subreg.sub1, killed [[COPY1]], %subreg.sub2			; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_96 = REG_SEQUENCE killed [[COPY3]], %subreg.sub0, killed [[COPY2]], %subreg.sub1, killed [[COPY1]], %subreg.sub2
	; GCN: [[COPY4:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE]]			; GCN: [[COPY4:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE]]
	; GCN: [[DEF2:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF			; GCN: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
	; GCN: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]			; GCN: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]
	; GCN: [[DEF3:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF			; GCN: [[DEF3:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
	; GCN: BUFFER_STORE_DWORDX3_OFFEN_exact killed [[COPY4]], [[COPY5]], [[DEF3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)			; GCN: BUFFER_STORE_DWORDX3_OFFEN_exact killed [[COPY4]], [[COPY5]], [[DEF3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)
	; GCN: S_ENDPGM 0			; GCN: S_ENDPGM 0
	main_body:			main_body:
	%tmp25 = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> undef, i32 undef, i32 0, i32 0)			%tmp25 = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> undef, i32 undef, i32 0, i32 0)
	%tmp27 = bitcast <4 x float> %tmp25 to <16 x i8>			%tmp27 = bitcast <4 x float> %tmp25 to <16 x i8>
	%tmp28 = shufflevector <16 x i8> %tmp27, <16 x i8> undef, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>			%tmp28 = shufflevector <16 x i8> %tmp27, <16 x i8> undef, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
	%tmp29 = bitcast <12 x i8> %tmp28 to <3 x i32>			%tmp29 = bitcast <12 x i8> %tmp28 to <3 x i32>
	call void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32> %tmp29, <4 x i32> undef, i32 undef, i32 0, i32 0) #3			call void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32> %tmp29, <4 x i32> undef, i32 undef, i32 0, i32 0) #3
	ret void			ret void
	}			}

	declare void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32 immarg)			declare void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32 immarg)
	declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32 immarg)			declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32 immarg)

test/CodeGen/AMDGPU/inline-constraints.ll

Show All 24 Lines	entry:
%s32_2 = tail call <2 x i32> asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s32_2 = tail call <2 x i32> asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
%s64 = tail call i64 asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s64 = tail call i64 asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
%s4_32 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s4_32 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
%s128 = tail call i128 asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s128 = tail call i128 asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
ret void		ret void
}		}

; FIXME: Should be able to avoid copy
; GCN-LABEL: {{^}}inline_sreg_constraint_m0:		; GCN-LABEL: {{^}}inline_sreg_constraint_m0:
; GCN: s_mov_b32 m0, -1		; GCN: s_mov_b32 m0, -1
; GCN: s_mov_b32 [[COPY_M0:s[0-9]+]], m0		; GCN-NOT: m0
; GCN: ; use [[COPY_M0]]		; GCN: ; use m0
define amdgpu_kernel void @inline_sreg_constraint_m0() {		define amdgpu_kernel void @inline_sreg_constraint_m0() {
%m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={m0}"()		%m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={m0}"()
tail call void asm sideeffect "; use $0", "s"(i32 %m0)		tail call void asm sideeffect "; use $0", "s"(i32 %m0)
ret void		ret void
}		}

; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i32:		; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i32:
; GCN: s_mov_b32 [[REG:s[0-9]+]], 32		; GCN: s_mov_b32 [[REG:s[0-9]+]], 32
Show All 32 Lines

test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll

	Show All 24 Lines
	; CHECK-NOT: [[VVAL]]			; CHECK-NOT: [[VVAL]]
	; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]			; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
	define amdgpu_kernel void @test_readfirstlane_imm_fold(i32 addrspace(1)* %out) #1 {			define amdgpu_kernel void @test_readfirstlane_imm_fold(i32 addrspace(1)* %out) #1 {
	%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 32)			%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 32)
	store i32 %readfirstlane, i32 addrspace(1)* %out, align 4			store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
	ret void			ret void
	}			}

	; TODO: m0 should be folded.
	; CHECK-LABEL: {{^}}test_readfirstlane_m0:			; CHECK-LABEL: {{^}}test_readfirstlane_m0:
	; CHECK: s_mov_b32 m0, -1			; CHECK: s_mov_b32 m0, -1
	; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0			; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], m0
	; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], [[COPY_M0]]
	; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]			; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
	define amdgpu_kernel void @test_readfirstlane_m0(i32 addrspace(1)* %out) #1 {			define amdgpu_kernel void @test_readfirstlane_m0(i32 addrspace(1)* %out) #1 {
	%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()			%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
	%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %m0)			%readfirstlane = call i32 @llvm.amdgcn.readfirstlane(i32 %m0)
	store i32 %readfirstlane, i32 addrspace(1)* %out, align 4			store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
	ret void			ret void
	}			}

	Show All 28 Lines

test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll

Show All 38 Lines	define amdgpu_kernel void @test_readlane_vregs(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
%readlane = call i32 @llvm.amdgcn.readlane(i32 %value, i32 %lane)		%readlane = call i32 @llvm.amdgcn.readlane(i32 %value, i32 %lane)
store i32 %readlane, i32 addrspace(1)* %out, align 4		store i32 %readlane, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

; TODO: m0 should be folded.		; TODO: m0 should be folded.
; CHECK-LABEL: {{^}}test_readlane_m0_sreg:		; CHECK-LABEL: {{^}}test_readlane_m0_sreg:
; CHECK: s_mov_b32 m0, -1		; CHECK: s_mov_b32 m0, -1
; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0		; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], m0
; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], [[COPY_M0]]
; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]		; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
define amdgpu_kernel void @test_readlane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {		define amdgpu_kernel void @test_readlane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()		%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
%readlane = call i32 @llvm.amdgcn.readlane(i32 %m0, i32 %src1)		%readlane = call i32 @llvm.amdgcn.readlane(i32 %m0, i32 %src1)
store i32 %readlane, i32 addrspace(1)* %out, align 4		store i32 %readlane, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

Show All 29 Lines

test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll

Show All 29 Lines	define amdgpu_kernel void @test_writelane_vreg_lane(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
%args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in		%args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in
%oldval = load i32, i32 addrspace(1)* %out		%oldval = load i32, i32 addrspace(1)* %out
%lane = extractelement <2 x i32> %args, i32 1		%lane = extractelement <2 x i32> %args, i32 1
%writelane = call i32 @llvm.amdgcn.writelane(i32 12, i32 %lane, i32 %oldval)		%writelane = call i32 @llvm.amdgcn.writelane(i32 12, i32 %lane, i32 %oldval)
store i32 %writelane, i32 addrspace(1)* %out, align 4		store i32 %writelane, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

; TODO: m0 should be folded.
; CHECK-LABEL: {{^}}test_writelane_m0_sreg:		; CHECK-LABEL: {{^}}test_writelane_m0_sreg:
; CHECK: s_mov_b32 m0, -1		; CHECK: s_mov_b32 m0, -1
; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0		; CHECK: v_writelane_b32 v{{[0-9]+}}, m0, s{{[0-9]+}}
; CHECK: v_writelane_b32 v{{[0-9]+}}, [[COPY_M0]], s{{[0-9]+}}
define amdgpu_kernel void @test_writelane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {		define amdgpu_kernel void @test_writelane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
%oldval = load i32, i32 addrspace(1)* %out		%oldval = load i32, i32 addrspace(1)* %out
%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()		%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
%writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %src1, i32 %oldval)		%writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %src1, i32 %oldval)
store i32 %writelane, i32 addrspace(1)* %out, align 4		store i32 %writelane, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

Show All 32 Lines

test/CodeGen/AMDGPU/read_register.ll

	; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s \| FileCheck %s			; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s \| FileCheck %s

	declare i32 @llvm.read_register.i32(metadata) #0			declare i32 @llvm.read_register.i32(metadata) #0
	declare i64 @llvm.read_register.i64(metadata) #0			declare i64 @llvm.read_register.i64(metadata) #0

	; FIXME: Should be able to eliminate copy
	; CHECK-LABEL: {{^}}test_read_m0:			; CHECK-LABEL: {{^}}test_read_m0:
	; CHECK: s_mov_b32 m0, -1			; CHECK: s_mov_b32 m0, -1
	; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0			; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], m0
	; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], [[COPY_M0]]
	; CHECK: buffer_store_dword [[COPY]]			; CHECK: buffer_store_dword [[COPY]]
	define amdgpu_kernel void @test_read_m0(i32 addrspace(1)* %out) #0 {			define amdgpu_kernel void @test_read_m0(i32 addrspace(1)* %out) #0 {
	store volatile i32 0, i32 addrspace(3)* undef			store volatile i32 0, i32 addrspace(3)* undef
	%m0 = call i32 @llvm.read_register.i32(metadata !0)			%m0 = call i32 @llvm.read_register.i32(metadata !0)
	store i32 %m0, i32 addrspace(1)* %out			store i32 %m0, i32 addrspace(1)* %out
	ret void			ret void
	}			}

	▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

AMDGPU: Relax 32-bit SGPR register classClosedPublic

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Revision Contents

Diff 224427

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

lib/Target/AMDGPU/SIISelLowering.cpp

lib/Target/AMDGPU/SIInstrInfo.cpp

lib/Target/AMDGPU/SIRegisterInfo.h

lib/Target/AMDGPU/SIRegisterInfo.cpp

test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir

AMDGPU: Relax 32-bit SGPR register class
ClosedPublic