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Differential D68348

[AMDGPU][MC][GFX10] Enabled decoding of 'null' operand
ClosedPublic

Authored by dp on Oct 2 2019, 10:53 AM.

Details

Reviewers
rampitec
arsenm
Commits
rG9bd763679fe9: [AMDGPU][MC][GFX10] Enabled decoding of 'null' operand
rL373740: [AMDGPU][MC][GFX10] Enabled decoding of 'null' operand
Summary

null cannot be decoded when used as a source operand of 64-bit SOP instructions.

0x7d,0x00,0x80,0x91

Expected result is the following:

s_ashr_i64 s[0:1], null, s0

Actual result: an assert.

See bug 43485: https://bugs.llvm.org/show_bug.cgi?id=43485

Diff Detail

Repository
rL LLVM

Event Timeline

dp created this revision.Oct 2 2019, 10:53 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptOct 2 2019, 10:53 AM
rampitec accepted this revision.Oct 2 2019, 10:58 AM

LGTM

This revision is now accepted and ready to land.Oct 2 2019, 10:58 AM
Closed by commit rL373740: [AMDGPU][MC][GFX10] Enabled decoding of 'null' operand (authored by dpreobra). · Explain WhyOct 4 2019, 5:39 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptOct 4 2019, 5:39 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
Disassembler/
1 line
test/
MC/
Disassembler/
AMDGPU/
7 lines

Diff 223196

llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Show First 20 Lines • Show All 1,089 Lines • ▼ Show 20 LinesMCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
using namespace AMDGPU; using namespace AMDGPU;
switch (Val) { switch (Val) {
case 102: return createRegOperand(FLAT_SCR); case 102: return createRegOperand(FLAT_SCR);
case 104: return createRegOperand(XNACK_MASK); case 104: return createRegOperand(XNACK_MASK);
case 106: return createRegOperand(VCC); case 106: return createRegOperand(VCC);
case 108: return createRegOperand(TBA); case 108: return createRegOperand(TBA);
case 110: return createRegOperand(TMA); case 110: return createRegOperand(TMA);
case 125: return createRegOperand(SGPR_NULL);
case 126: return createRegOperand(EXEC); case 126: return createRegOperand(EXEC);
case 235: return createRegOperand(SRC_SHARED_BASE); case 235: return createRegOperand(SRC_SHARED_BASE);
case 236: return createRegOperand(SRC_SHARED_LIMIT); case 236: return createRegOperand(SRC_SHARED_LIMIT);
case 237: return createRegOperand(SRC_PRIVATE_BASE); case 237: return createRegOperand(SRC_PRIVATE_BASE);
case 238: return createRegOperand(SRC_PRIVATE_LIMIT); case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
case 251: return createRegOperand(SRC_VCCZ); case 251: return createRegOperand(SRC_VCCZ);
case 252: return createRegOperand(SRC_EXECZ); case 252: return createRegOperand(SRC_EXECZ);
▲ Show 20 Lines • Show All 163 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt

# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10
# GFX10: s_ashr_i64 s[0:1], null, s0 ; encoding: [0x7d,0x00,0x80,0x91]
0x7d,0x00,0x80,0x91
# GFX10: s_and_b64 s[0:1], null, null ; encoding: [0x7d,0x7d,0x80,0x87]
0x7d,0x7d,0x80,0x87