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Differential D68151

[GlobalISel] Add an operand to memory intrinsics to denote the "tail" marker.
ClosedPublic

Authored by aemerson on Sep 27 2019, 11:22 AM.

Details

Reviewers
paquette
arsenm
Commits
rG509a4947c911: Add an operand to memory intrinsics to denote the "tail" marker.
rL373140: Add an operand to memory intrinsics to denote the "tail" marker.
Summary

We need to propagate this information from the IR in order to be able to safely do tail call optimizations on the intrinsics during legalization. Assuming it's safe to do tail call opt without checking for the marker isn't safe because the mem libcall may use allocas from the caller.

This adds an extra immediate operand to the end of the intrinsics and fixes the legalizer to handle it.

Diff Detail

Repository
rL LLVM

Event Timeline

aemerson created this revision.Sep 27 2019, 11:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 27 2019, 11:22 AM
Herald added subscribers: Petar.Avramovic, volkan, atanasyan and 5 others. · View Herald Transcript
paquette added a comment.EditedSep 27 2019, 11:34 AM

Can we also have a check for say, __memcpy_chk?

e.g.

define void @test_memcpy_chk() {
  %dst = bitcast %struct.T1* @t1 to i8*
  %src = bitcast %struct.T2* @t2 to i8*
  %ret = tail call i8* @__memcpy_chk(i8* %dst, i8* %src, i64 1824, i64 1824)
  ret void
}

This is correctly emitted as a normal call to memcpy by SelectionDAG, but incorrectly emitted as a tail call by GlobalISel.

paquette accepted this revision.Sep 27 2019, 3:30 PM

LGTM with test change

This revision is now accepted and ready to land.Sep 27 2019, 3:30 PM
arsenm added a comment.Sep 27 2019, 4:19 PM

I'm somewhat worried about this wrt. eventually verifying intrinsics have the correct number of operands

arsenm added a comment.Sep 27 2019, 4:19 PM
In D68151#1686687, @arsenm wrote:

I'm somewhat worried about this wrt. eventually verifying intrinsics have the correct number of operands

At minimum the verifier should manually check this operand and manually verify these intrinsics

aemerson added a comment.Sep 27 2019, 4:26 PM
In D68151#1686689, @arsenm wrote:
In D68151#1686687, @arsenm wrote:

I'm somewhat worried about this wrt. eventually verifying intrinsics have the correct number of operands

At minimum the verifier should manually check this operand and manually verify these intrinsics

I'll add the verifier checks for this as well. If we want a different solution in general then let's start a separate discussion. Maybe we can explore adding more flags to MachineInstr, or dedicated G_CALL opcode that has a bitfield operand that propagates the flags from the CallInst.

arsenm added a comment.Sep 27 2019, 4:30 PM
In D68151#1686700, @aemerson wrote:
In D68151#1686689, @arsenm wrote:
In D68151#1686687, @arsenm wrote:

I'm somewhat worried about this wrt. eventually verifying intrinsics have the correct number of operands

At minimum the verifier should manually check this operand and manually verify these intrinsics

I'll add the verifier checks for this as well. If we want a different solution in general then let's start a separate discussion. Maybe we can explore adding more flags to MachineInstr, or dedicated G_CALL opcode that has a bitfield operand that propagates the flags from the CallInst.

For AMDGPU I'm going to need a regbankselectable G_CALL at some point anyway

Closed by commit rL373140: Add an operand to memory intrinsics to denote the "tail" marker. (authored by aemerson). · Explain WhySep 27 2019, 10:31 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
GlobalISel/
5 lines
6 lines
14 lines
test/
CodeGen/
AArch64/
GlobalISel/
18 lines
8 lines
12 lines
10 lines
6 lines
78 lines
30 lines
Mips/
GlobalISel/
irtranslator/
4 lines
legalizer/
2 lines
X86/
GlobalISel/
18 lines
MachineVerifier/
27 lines

Diff 222282

llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 1,137 Lines • ▼ Show 20 Linesbool IRTranslator::translateMemFunc(const CallInst &CI,
} else if (auto *MMI = dyn_cast<MemMoveInst>(&CI)) { } else if (auto *MMI = dyn_cast<MemMoveInst>(&CI)) {
DstAlign = std::max<unsigned>(MMI->getDestAlignment(), 1); DstAlign = std::max<unsigned>(MMI->getDestAlignment(), 1);
SrcAlign = std::max<unsigned>(MMI->getSourceAlignment(), 1); SrcAlign = std::max<unsigned>(MMI->getSourceAlignment(), 1);
} else { } else {
auto *MSI = cast<MemSetInst>(&CI); auto *MSI = cast<MemSetInst>(&CI);
DstAlign = std::max<unsigned>(MSI->getDestAlignment(), 1); DstAlign = std::max<unsigned>(MSI->getDestAlignment(), 1);
} }
// We need to propagate the tail call flag from the IR inst as an argument.
// Otherwise, we have to pessimize and assume later that we cannot tail call
// any memory intrinsics.
ICall.addImm(CI.isTailCall() ? 1 : 0);
// Create mem operands to store the alignment and volatile info. // Create mem operands to store the alignment and volatile info.
auto VolFlag = IsVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone; auto VolFlag = IsVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
ICall.addMemOperand(MF->getMachineMemOperand( ICall.addMemOperand(MF->getMachineMemOperand(
MachinePointerInfo(CI.getArgOperand(0)), MachinePointerInfo(CI.getArgOperand(0)),
MachineMemOperand::MOStore | VolFlag, 1, DstAlign)); MachineMemOperand::MOStore | VolFlag, 1, DstAlign));
if (ID != Intrinsic::memset) if (ID != Intrinsic::memset)
ICall.addMemOperand(MF->getMachineMemOperand( ICall.addMemOperand(MF->getMachineMemOperand(
MachinePointerInfo(CI.getArgOperand(1)), MachinePointerInfo(CI.getArgOperand(1)),
▲ Show 20 Lines • Show All 1,225 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 389 Lines • ▼ Show 20 Lines
LegalizerHelper::LegalizeResult LegalizerHelper::LegalizeResult
llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
MachineInstr &MI) { MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS); assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
SmallVector<CallLowering::ArgInfo, 3> Args; SmallVector<CallLowering::ArgInfo, 3> Args;
for (unsigned i = 1; i < MI.getNumOperands(); i++) { // Add all the args, except for the last which is an imm denoting 'tail'.
for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
Register Reg = MI.getOperand(i).getReg(); Register Reg = MI.getOperand(i).getReg();
// Need derive an IR type for call lowering. // Need derive an IR type for call lowering.
LLT OpLLT = MRI.getType(Reg); LLT OpLLT = MRI.getType(Reg);
Type *OpTy = nullptr; Type *OpTy = nullptr;
if (OpLLT.isPointer()) if (OpLLT.isPointer())
OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
else else
Show All 21 Linesllvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
const char *Name = TLI.getLibcallName(RTLibcall); const char *Name = TLI.getLibcallName(RTLibcall);
MIRBuilder.setInstr(MI); MIRBuilder.setInstr(MI);
CallLowering::CallLoweringInfo Info; CallLowering::CallLoweringInfo Info;
Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
Info.Callee = MachineOperand::CreateES(Name); Info.Callee = MachineOperand::CreateES(Name);
Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)); Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
Info.IsTailCall = isLibCallInTailPosition(MI); Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
isLibCallInTailPosition(MI);
std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
if (!CLI.lowerCall(MIRBuilder, Info)) if (!CLI.lowerCall(MIRBuilder, Info))
return LegalizerHelper::UnableToLegalize; return LegalizerHelper::UnableToLegalize;
if (Info.LoweredTailCall) { if (Info.LoweredTailCall) {
assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
// We must have a return following the call to get past // We must have a return following the call to get past
▲ Show 20 Lines • Show All 3,653 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Show First 20 Lines • Show All 1,362 Lines • ▼ Show 20 Lines if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
report("G_INTRINSIC used with intrinsic that accesses memory", MI); report("G_INTRINSIC used with intrinsic that accesses memory", MI);
break; break;
} }
if (!NoSideEffects && !DeclHasSideEffects) { if (!NoSideEffects && !DeclHasSideEffects) {
report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI); report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
break; break;
} }
} }
switch (IntrID) {
case Intrinsic::memcpy:
if (MI->getNumOperands() != 5)
report("Expected memcpy intrinsic to have 5 operands", MI);
break;
case Intrinsic::memmove:
if (MI->getNumOperands() != 5)
report("Expected memmove intrinsic to have 5 operands", MI);
break;
case Intrinsic::memset:
if (MI->getNumOperands() != 5)
report("Expected memset intrinsic to have 5 operands", MI);
break;
}
break; break;
} }
case TargetOpcode::G_SEXT_INREG: { case TargetOpcode::G_SEXT_INREG: {
if (!MI->getOperand(2).isImm()) { if (!MI->getOperand(2).isImm()) {
report("G_SEXT_INREG expects an immediate operand #2", MI); report("G_SEXT_INREG expects an immediate operand #2", MI);
break; break;
} }
▲ Show 20 Lines • Show All 1,452 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Show First 20 Lines • Show All 1,128 Lines • ▼ Show 20 Lines
} }
declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1) declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1)
define void @test_memcpy(i8* %dst, i8* %src, i64 %size) { define void @test_memcpy(i8* %dst, i8* %src, i64 %size) {
; CHECK-LABEL: name: test_memcpy ; CHECK-LABEL: name: test_memcpy
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[DST]](p0), [[SRC]](p0), [[SIZE]](s64) :: (store 1 into %ir.dst), (load 1 from %ir.src) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 0 :: (store 1 into %ir.dst), (load 1 from %ir.src)
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i1 0) call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i1 0)
ret void ret void
} }
define void @test_memcpy_tail(i8* %dst, i8* %src, i64 %size) {
; CHECK-LABEL: name: test_memcpy_tail
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 1 :: (store 1 into %ir.dst), (load 1 from %ir.src)
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i1 0)
ret void
}
declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)*, i8 addrspace(1)*, i64, i1) declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)*, i8 addrspace(1)*, i64, i1)
define void @test_memcpy_nonzero_as(i8 addrspace(1)* %dst, i8 addrspace(1) * %src, i64 %size) { define void @test_memcpy_nonzero_as(i8 addrspace(1)* %dst, i8 addrspace(1) * %src, i64 %size) {
; CHECK-LABEL: name: test_memcpy_nonzero_as ; CHECK-LABEL: name: test_memcpy_nonzero_as
; CHECK: [[DST:%[0-9]+]]:_(p1) = COPY $x0 ; CHECK: [[DST:%[0-9]+]]:_(p1) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p1) = COPY $x1 ; CHECK: [[SRC:%[0-9]+]]:_(p1) = COPY $x1
; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[DST]](p1), [[SRC]](p1), [[SIZE]](s64) :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 1) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[DST]](p1), [[SRC]](p1), [[SIZE]](s64), 0 :: (store 1 into %ir.dst, addrspace 1), (load 1 from %ir.src, addrspace 1)
call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* %dst, i8 addrspace(1)* %src, i64 %size, i1 0) call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* %dst, i8 addrspace(1)* %src, i64 %size, i1 0)
ret void ret void
} }
declare void @llvm.memmove.p0i8.p0i8.i64(i8*, i8*, i64, i1) declare void @llvm.memmove.p0i8.p0i8.i64(i8*, i8*, i64, i1)
define void @test_memmove(i8* %dst, i8* %src, i64 %size) { define void @test_memmove(i8* %dst, i8* %src, i64 %size) {
; CHECK-LABEL: name: test_memmove ; CHECK-LABEL: name: test_memmove
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), [[DST]](p0), [[SRC]](p0), [[SIZE]](s64) :: (store 1 into %ir.dst), (load 1 from %ir.src) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 0 :: (store 1 into %ir.dst), (load 1 from %ir.src)
call void @llvm.memmove.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i1 0) call void @llvm.memmove.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i1 0)
ret void ret void
} }
declare void @llvm.memset.p0i8.i64(i8*, i8, i64, i1) declare void @llvm.memset.p0i8.i64(i8*, i8, i64, i1)
define void @test_memset(i8* %dst, i8 %val, i64 %size) { define void @test_memset(i8* %dst, i8 %val, i64 %size) {
; CHECK-LABEL: name: test_memset ; CHECK-LABEL: name: test_memset
; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]] ; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]]
; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), [[DST]](p0), [[SRC]](s8), [[SIZE]](s64) :: (store 1 into %ir.dst) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), [[DST]](p0), [[SRC]](s8), [[SIZE]](s64), 0 :: (store 1 into %ir.dst)
call void @llvm.memset.p0i8.i64(i8* %dst, i8 %val, i64 %size, i1 0) call void @llvm.memset.p0i8.i64(i8* %dst, i8 %val, i64 %size, i1 0)
ret void ret void
} }
declare i64 @llvm.objectsize.i64(i8*, i1) declare i64 @llvm.objectsize.i64(i8*, i1)
declare i32 @llvm.objectsize.i32(i8*, i1) declare i32 @llvm.objectsize.i32(i8*, i1)
define void @test_objectsize(i8* %addr0, i8* %addr1) { define void @test_objectsize(i8* %addr0, i8* %addr1) {
; CHECK-LABEL: name: test_objectsize ; CHECK-LABEL: name: test_objectsize
▲ Show 20 Lines • Show All 1,158 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesbody: |
bb.1.entry: bb.1.entry:
liveins: $x0, $x1, $x2 liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_memcpy1 ; CHECK-LABEL: name: test_memcpy1
; CHECK: liveins: $x0, $x1, $x2 ; CHECK: liveins: $x0, $x1, $x2
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[COPY]](p0), [[COPY1]](p0), [[COPY2]](s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[COPY]](p0), [[COPY1]](p0), [[COPY2]](s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = COPY $x2 %2:_(s64) = COPY $x2
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_memcpy2_const name: test_memcpy2_const
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
Show All 30 Lines bb.1.entry:
; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C3]](s64) ; CHECK: [[GEP6:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C3]](s64)
; CHECK: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[GEP6]](p0) :: (load 8 from %ir.1 + 64, align 4) ; CHECK: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[GEP6]](p0) :: (load 8 from %ir.1 + 64, align 4)
; CHECK: [[GEP7:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C3]](s64) ; CHECK: [[GEP7:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C3]](s64)
; CHECK: G_STORE [[LOAD4]](s64), [[GEP7]](p0) :: (store 8 into %ir.0 + 64, align 4) ; CHECK: G_STORE [[LOAD4]](s64), [[GEP7]](p0) :: (store 8 into %ir.0 + 64, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = G_CONSTANT i64 72 %2:_(s64) = G_CONSTANT i64 72
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_memcpy3_const_arrays_unaligned name: test_memcpy3_const_arrays_unaligned
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines bb.1.entry:
; CHECK: [[GEP14:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C7]](s64) ; CHECK: [[GEP14:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C7]](s64)
; CHECK: [[LOAD8:%[0-9]+]]:_(s128) = G_LOAD [[GEP14]](p0) :: (load 16 from %ir.1 + 127, align 4) ; CHECK: [[LOAD8:%[0-9]+]]:_(s128) = G_LOAD [[GEP14]](p0) :: (load 16 from %ir.1 + 127, align 4)
; CHECK: [[GEP15:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C7]](s64) ; CHECK: [[GEP15:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C7]](s64)
; CHECK: G_STORE [[LOAD8]](s128), [[GEP15]](p0) :: (store 16 into %ir.0 + 127, align 4) ; CHECK: G_STORE [[LOAD8]](s128), [[GEP15]](p0) :: (store 16 into %ir.0 + 127, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = G_CONSTANT i64 143 %2:_(s64) = G_CONSTANT i64 143
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesbody: |
bb.1.entry: bb.1.entry:
liveins: $x0, $x1, $x2 liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_memmove1 ; CHECK-LABEL: name: test_memmove1
; CHECK: liveins: $x0, $x1, $x2 ; CHECK: liveins: $x0, $x1, $x2
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), [[COPY]](p0), [[COPY1]](p0), [[COPY2]](s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), [[COPY]](p0), [[COPY1]](p0), [[COPY2]](s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = COPY $x2 %2:_(s64) = COPY $x2
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_memmove2_const name: test_memmove2_const
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
Show All 17 Lines bb.1.entry:
; CHECK: G_STORE [[LOAD1]](s128), [[GEP2]](p0) :: (store 16 into %ir.0 + 16, align 4) ; CHECK: G_STORE [[LOAD1]](s128), [[GEP2]](p0) :: (store 16 into %ir.0 + 16, align 4)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C3]](s64) ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C3]](s64)
; CHECK: G_STORE [[LOAD2]](s128), [[GEP3]](p0) :: (store 16 into %ir.0 + 32, align 4) ; CHECK: G_STORE [[LOAD2]](s128), [[GEP3]](p0) :: (store 16 into %ir.0 + 32, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = G_CONSTANT i64 48 %2:_(s64) = G_CONSTANT i64 48
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_memmove3_const_toolarge name: test_memmove3_const_toolarge
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: test_memmove3_const_toolarge ; CHECK-LABEL: name: test_memmove3_const_toolarge
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 96 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 96
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), [[COPY]](p0), [[COPY1]](p0), [[C]](s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), [[COPY]](p0), [[COPY1]](p0), [[C]](s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = G_CONSTANT i64 96 %2:_(s64) = G_CONSTANT i64 96
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_memmove4_const_unaligned name: test_memmove4_const_unaligned
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
Show All 23 Lines bb.1.entry:
; CHECK: G_STORE [[LOAD2]](s128), [[GEP4]](p0) :: (store 16 into %ir.0 + 32, align 4) ; CHECK: G_STORE [[LOAD2]](s128), [[GEP4]](p0) :: (store 16 into %ir.0 + 32, align 4)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C5]](s64) ; CHECK: [[GEP5:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C5]](s64)
; CHECK: G_STORE [[LOAD3]](s32), [[GEP5]](p0) :: (store 4 into %ir.0 + 48) ; CHECK: G_STORE [[LOAD3]](s32), [[GEP5]](p0) :: (store 4 into %ir.0 + 48)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = G_CONSTANT i64 52 %2:_(s64) = G_CONSTANT i64 52
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/inline-memset.mir

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines bb.1.entry:
; CHECK-LABEL: name: test_ms1 ; CHECK-LABEL: name: test_ms1
; CHECK: liveins: $w1, $w2, $x0 ; CHECK: liveins: $w1, $w2, $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), [[COPY]](p0), [[TRUNC]](s8), [[ZEXT]](s64) :: (store 1 into %ir.dst) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), [[COPY]](p0), [[TRUNC]](s8), [[ZEXT]](s64), 1 :: (store 1 into %ir.dst)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1 %1:_(s32) = COPY $w1
%2:_(s32) = COPY $w2 %2:_(s32) = COPY $w2
%3:_(s8) = G_TRUNC %1(s32) %3:_(s8) = G_TRUNC %1(s32)
%4:_(s64) = G_ZEXT %2(s32) %4:_(s64) = G_ZEXT %2(s32)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %3(s8), %4(s64) :: (store 1 into %ir.dst) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %3(s8), %4(s64), 1 :: (store 1 into %ir.dst)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_ms2_const name: test_ms2_const
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
Show All 12 Lines bb.1.entry:
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s64)
; CHECK: G_STORE [[MUL]](s64), [[GEP]](p0) :: (store 8 into %ir.dst + 8, align 1) ; CHECK: G_STORE [[MUL]](s64), [[GEP]](p0) :: (store 8 into %ir.dst + 8, align 1)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1 %1:_(s32) = COPY $w1
%3:_(s64) = G_CONSTANT i64 16 %3:_(s64) = G_CONSTANT i64 16
%2:_(s8) = G_TRUNC %1(s32) %2:_(s8) = G_TRUNC %1(s32)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %2(s8), %3(s64) :: (store 1 into %ir.dst) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %2(s8), %3(s64), 1 :: (store 1 into %ir.dst)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_ms3_const_both name: test_ms3_const_both
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_ms3_const_both ; CHECK-LABEL: name: test_ms3_const_both
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4629771061636907072 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4629771061636907072
; CHECK: G_STORE [[C]](s64), [[COPY]](p0) :: (store 8 into %ir.dst, align 1) ; CHECK: G_STORE [[C]](s64), [[COPY]](p0) :: (store 8 into %ir.dst, align 1)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s64)
; CHECK: G_STORE [[C]](s64), [[GEP]](p0) :: (store 8 into %ir.dst + 8, align 1) ; CHECK: G_STORE [[C]](s64), [[GEP]](p0) :: (store 8 into %ir.dst + 8, align 1)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 64 %1:_(s8) = G_CONSTANT i8 64
%2:_(s64) = G_CONSTANT i64 16 %2:_(s64) = G_CONSTANT i64 16
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %1(s8), %2(s64) :: (store 1 into %ir.dst) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %1(s8), %2(s64), 1 :: (store 1 into %ir.dst)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_ms4_const_both_unaligned name: test_ms4_const_both_unaligned
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
Show All 11 Lines bb.1.entry:
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C2]](s64) ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[TRUNC]](s16), [[GEP1]](p0) :: (store 2 into %ir.dst + 16, align 1) ; CHECK: G_STORE [[TRUNC]](s16), [[GEP1]](p0) :: (store 2 into %ir.dst + 16, align 1)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 64 %1:_(s8) = G_CONSTANT i8 64
%2:_(s64) = G_CONSTANT i64 18 %2:_(s64) = G_CONSTANT i64 18
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %1(s8), %2(s64) :: (store 1 into %ir.dst) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %1(s8), %2(s64), 1 :: (store 1 into %ir.dst)
RET_ReallyLR RET_ReallyLR
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines bb.1.entry:
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C]](s64) ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[GEP]](p0) :: (load 16 from %ir.1 + 16, align 4) ; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[GEP]](p0) :: (load 16 from %ir.1 + 16, align 4)
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64) ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: G_STORE [[LOAD1]](s128), [[GEP1]](p0) :: (store 16 into %ir.0 + 16, align 4) ; CHECK: G_STORE [[LOAD1]](s128), [[GEP1]](p0) :: (store 16 into %ir.0 + 16, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = G_CONSTANT i64 32 %2:_(s64) = G_CONSTANT i64 32
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_large_memcpy name: test_large_memcpy
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: test_large_memcpy ; CHECK-LABEL: name: test_large_memcpy
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[COPY]](p0), [[COPY1]](p0), [[C]](s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[COPY]](p0), [[COPY1]](p0), [[C]](s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s64) = G_CONSTANT i64 36 %2:_(s64) = G_CONSTANT i64 36
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %2(s64), 1 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
RET_ReallyLR RET_ReallyLR
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
--- ---
name: test_memcpy name: test_memcpy
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $w2, $x0, $x1 liveins: $w2, $x0, $x1
; CHECK-LABEL: name: test_memcpy ; CHECK-LABEL: name: test_memcpy
; CHECK: liveins: $w2, $x0, $x1 ; CHECK: liveins: $w2, $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x0 = COPY [[COPY]](p0)
; CHECK: $x1 = COPY [[COPY1]](p0) ; CHECK: $x1 = COPY [[COPY1]](p0)
; CHECK: $x2 = COPY [[ZEXT]](s64) ; CHECK: $x2 = COPY [[ZEXT]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C]] ; CHECK: RET_ReallyLR
; CHECK: $w3 = COPY [[AND]](s32) %0:_(p0) = COPY $x0
; CHECK: TCRETURNdi &memcpy, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3 %1:_(p0) = COPY $x1
%2:_(s32) = COPY $w2
%3:_(s64) = G_ZEXT %2(s32)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %3(s64), 0
RET_ReallyLR
...
---
name: test_memcpy_tail
tracksRegLiveness: true
body: |
bb.1:
liveins: $w2, $x0, $x1
; CHECK-LABEL: name: test_memcpy_tail
; CHECK: liveins: $w2, $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: $x0 = COPY [[COPY]](p0)
; CHECK: $x1 = COPY [[COPY1]](p0)
; CHECK: $x2 = COPY [[ZEXT]](s64)
; CHECK: TCRETURNdi &memcpy, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $x1, implicit $x2
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s32) = COPY $w2 %2:_(s32) = COPY $w2
%4:_(s1) = G_CONSTANT i1 false
%3:_(s64) = G_ZEXT %2(s32) %3:_(s64) = G_ZEXT %2(s32)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %3(s64), %4(s1) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %3(s64), 1
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_memmove name: test_memmove
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $w2, $x0, $x1 liveins: $w2, $x0, $x1
; CHECK-LABEL: name: test_memmove ; CHECK-LABEL: name: test_memmove
; CHECK: liveins: $w2, $x0, $x1 ; CHECK: liveins: $w2, $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x0 = COPY [[COPY]](p0)
; CHECK: $x1 = COPY [[COPY1]](p0) ; CHECK: $x1 = COPY [[COPY1]](p0)
; CHECK: $x2 = COPY [[ZEXT]](s64) ; CHECK: $x2 = COPY [[ZEXT]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: BL &memmove, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C]] ; CHECK: RET_ReallyLR
; CHECK: $w3 = COPY [[AND]](s32)
; CHECK: TCRETURNdi &memmove, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s32) = COPY $w2 %2:_(s32) = COPY $w2
%4:_(s1) = G_CONSTANT i1 false
%3:_(s64) = G_ZEXT %2(s32) %3:_(s64) = G_ZEXT %2(s32)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %3(s64), %4(s1) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %1(p0), %3(s64), 0
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: test_memset name: test_memset
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $w1, $w2, $x0 liveins: $w1, $w2, $x0
; CHECK-LABEL: name: test_memset ; CHECK-LABEL: name: test_memset
; CHECK: liveins: $w1, $w2, $x0 ; CHECK: liveins: $w1, $w2, $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x0 = COPY [[COPY]](p0)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: $w1 = COPY [[COPY3]](s32) ; CHECK: $w1 = COPY [[COPY3]](s32)
; CHECK: $x2 = COPY [[ZEXT]](s64) ; CHECK: $x2 = COPY [[ZEXT]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: BL &memset, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C]] ; CHECK: RET_ReallyLR
; CHECK: $w3 = COPY [[AND]](s32)
; CHECK: TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1, implicit $x2, implicit $w3
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1 %1:_(s32) = COPY $w1
%2:_(s32) = COPY $w2 %2:_(s32) = COPY $w2
%5:_(s1) = G_CONSTANT i1 false
%3:_(s8) = G_TRUNC %1(s32) %3:_(s8) = G_TRUNC %1(s32)
%4:_(s64) = G_ZEXT %2(s32) %4:_(s64) = G_ZEXT %2(s32)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %3(s8), %4(s64), %5(s1) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %3(s8), %4(s64), 0
RET_ReallyLR RET_ReallyLR
... ...
--- ---
name: no_tail_call name: no_tail_call
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $w2, $x0, $x1 liveins: $w2, $x0, $x1
; CHECK-LABEL: name: no_tail_call ; CHECK-LABEL: name: no_tail_call
; CHECK: liveins: $w2, $x0, $x1 ; CHECK: liveins: $w2, $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x0 = COPY [[COPY]](p0)
; CHECK: $x1 = COPY [[COPY1]](p0) ; CHECK: $x1 = COPY [[COPY1]](p0)
; CHECK: $x2 = COPY [[ZEXT]](s64) ; CHECK: $x2 = COPY [[ZEXT]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C]]
; CHECK: $w3 = COPY [[AND]](s32)
; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[ZEXT]](s64) ; CHECK: $x0 = COPY [[ZEXT]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s32) = COPY $w2 %2:_(s32) = COPY $w2
%4:_(s1) = G_CONSTANT i1 false
%3:_(s64) = G_ZEXT %2(s32) %3:_(s64) = G_ZEXT %2(s32)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %3(s64), %4(s1) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %3(s64), 1
$x0 = COPY %3 $x0 = COPY %3
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...
--- ---
name: dont_tc_twice name: dont_tc_twice
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1: bb.1:
liveins: $w2, $x0, $x1 liveins: $w2, $x0, $x1
; CHECK-LABEL: name: dont_tc_twice ; CHECK-LABEL: name: dont_tc_twice
; CHECK: liveins: $w2, $x0, $x1 ; CHECK: liveins: $w2, $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x0 = COPY [[COPY]](p0)
; CHECK: $x1 = COPY [[COPY1]](p0) ; CHECK: $x1 = COPY [[COPY1]](p0)
; CHECK: $x2 = COPY [[ZEXT]](s64) ; CHECK: $x2 = COPY [[ZEXT]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C]]
; CHECK: $w3 = COPY [[AND]](s32)
; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp ; CHECK: TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp
%0:_(p0) = COPY $x0 %0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s32) = COPY $w2 %2:_(s32) = COPY $w2
%4:_(s1) = G_CONSTANT i1 false %4:_(s1) = G_CONSTANT i1 false
%3:_(s64) = G_ZEXT %2(s32) %3:_(s64) = G_ZEXT %2(s32)
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %3(s64), %4(s1) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %1(p0), %3(s64), 1
TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp TCRETURNdi &memset, 0, csr_aarch64_aapcs, implicit $sp

llvm/trunk/test/CodeGen/AArch64/GlobalISel/memcpy_chk_no_tail.ll

; RUN: llc -global-isel -verify-machineinstrs %s -o - | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios13.0.0"
%struct.int_sqrt = type { i32, i32 }
; Function Attrs: nounwind optsize ssp uwtable
; CHECK-LABEL: @usqrt
; CHECK-NOT: b memcpy
; CHECK: bl _memcpy
define void @usqrt(i32 %x, %struct.int_sqrt* %q) local_unnamed_addr #0 {
%a = alloca i32, align 4
%bc = bitcast i32* %a to i8*
%bc2 = bitcast %struct.int_sqrt* %q to i8*
%obj = tail call i64 @llvm.objectsize.i64.p0i8(i8* %bc2, i1 false, i1 true, i1 false)
%call = call i8* @__memcpy_chk(i8* %bc2, i8* nonnull %bc, i64 1000, i64 %obj) #4
ret void
}
; Function Attrs: nofree nounwind optsize
declare i8* @__memcpy_chk(i8*, i8*, i64, i64) local_unnamed_addr #2
; Function Attrs: nounwind readnone speculatable willreturn
declare i64 @llvm.objectsize.i64.p0i8(i8*, i1 immarg, i1 immarg, i1 immarg) #3
attributes #0 = { optsize "disable-tail-calls"="false" "frame-pointer"="all" }
attributes #2 = { nofree nounwind "disable-tail-calls"="false" "frame-pointer"="all" }
attributes #3 = { nounwind readnone speculatable willreturn }
attributes #4 = { nounwind optsize }

llvm/trunk/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
define void @call_symbol(i8* nocapture readonly %src, i8* nocapture %dest, i32 signext %length) { define void @call_symbol(i8* nocapture readonly %src, i8* nocapture %dest, i32 signext %length) {
; MIPS32-LABEL: name: call_symbol ; MIPS32-LABEL: name: call_symbol
; MIPS32: bb.1.entry: ; MIPS32: bb.1.entry:
; MIPS32: liveins: $a0, $a1, $a2 ; MIPS32: liveins: $a0, $a1, $a2
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[COPY1]](p0), [[COPY]](p0), [[COPY2]](s32) :: (store 1 into %ir.dest), (load 1 from %ir.src) ; MIPS32: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[COPY1]](p0), [[COPY]](p0), [[COPY2]](s32), 0 :: (store 1 into %ir.dest), (load 1 from %ir.src)
; MIPS32: RetRA ; MIPS32: RetRA
; MIPS32_PIC-LABEL: name: call_symbol ; MIPS32_PIC-LABEL: name: call_symbol
; MIPS32_PIC: bb.1.entry: ; MIPS32_PIC: bb.1.entry:
; MIPS32_PIC: liveins: $a0, $a1, $a2 ; MIPS32_PIC: liveins: $a0, $a1, $a2
; MIPS32_PIC: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; MIPS32_PIC: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 ; MIPS32_PIC: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32_PIC: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32_PIC: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[COPY1]](p0), [[COPY]](p0), [[COPY2]](s32) :: (store 1 into %ir.dest), (load 1 from %ir.src) ; MIPS32_PIC: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[COPY1]](p0), [[COPY]](p0), [[COPY2]](s32), 0 :: (store 1 into %ir.dest), (load 1 from %ir.src)
; MIPS32_PIC: RetRA ; MIPS32_PIC: RetRA
entry: entry:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %dest, i8* align 1 %src, i32 %length, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %dest, i8* align 1 %src, i32 %length, i1 false)
ret void ret void
} }
declare void @f_with_void_ret(); declare void @f_with_void_ret();
Show All 21 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines bb.1.entry:
%13:_(s8) = G_CONSTANT i8 0 %13:_(s8) = G_CONSTANT i8 0
%4:_(s32) = G_ADD %1, %3 %4:_(s32) = G_ADD %1, %3
%5:_(s32) = G_MUL %4, %3 %5:_(s32) = G_MUL %4, %3
%6:_(s32) = G_CONSTANT i32 7 %6:_(s32) = G_CONSTANT i32 7
%7:_(s32) = nuw G_ADD %5, %6 %7:_(s32) = nuw G_ADD %5, %6
%8:_(s32) = G_CONSTANT i32 -8 %8:_(s32) = G_CONSTANT i32 -8
%9:_(s32) = G_AND %7, %8 %9:_(s32) = G_AND %7, %8
%10:_(p0) = G_DYN_STACKALLOC %9(s32), 0 %10:_(p0) = G_DYN_STACKALLOC %9(s32), 0
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %10(p0), %0(s8), %1(s32) :: (store 1 into %ir.vla) G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %10(p0), %0(s8), %1(s32), 0 :: (store 1 into %ir.vla)
%11:_(p0) = G_GEP %10, %1(s32) %11:_(p0) = G_GEP %10, %1(s32)
%12:_(p0) = COPY %11(p0) %12:_(p0) = COPY %11(p0)
G_STORE %13(s8), %12(p0) :: (store 1 into %ir.arrayidx) G_STORE %13(s8), %12(p0) :: (store 1 into %ir.arrayidx)
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %10(p0) $a0 = COPY %10(p0)
JAL @puts, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $v0 JAL @puts, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $v0
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA RetRA
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll

Show All 13 Linesdefine float @test_return_f1(float %f.coerce) {
; ALL: bb.1.entry: ; ALL: bb.1.entry:
; ALL: liveins: $xmm0 ; ALL: liveins: $xmm0
; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0 ; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
; ALL: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128) ; ALL: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.f ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.f
; ALL: G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store 4 into %ir.coerce.dive2) ; ALL: G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store 4 into %ir.coerce.dive2)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64), 0 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
; ALL: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %ir.coerce.dive13) ; ALL: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %ir.coerce.dive13)
; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD]](s32) ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD]](s32)
; ALL: $xmm0 = COPY [[ANYEXT]](s128) ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
; ALL: RET 0, implicit $xmm0 ; ALL: RET 0, implicit $xmm0
entry: entry:
%retval = alloca %struct.f1, align 4 %retval = alloca %struct.f1, align 4
%f = alloca %struct.f1, align 4 %f = alloca %struct.f1, align 4
%coerce.dive = getelementptr inbounds %struct.f1, %struct.f1* %f, i32 0, i32 0 %coerce.dive = getelementptr inbounds %struct.f1, %struct.f1* %f, i32 0, i32 0
Show All 13 Linesdefine double @test_return_d1(double %d.coerce) {
; ALL: bb.1.entry: ; ALL: bb.1.entry:
; ALL: liveins: $xmm0 ; ALL: liveins: $xmm0
; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0 ; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
; ALL: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) ; ALL: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.d ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.d
; ALL: G_STORE [[TRUNC]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.coerce.dive2) ; ALL: G_STORE [[TRUNC]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.coerce.dive2)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64) :: (store 1 into %ir.0, align 8), (load 1 from %ir.1, align 8) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64), 0 :: (store 1 into %ir.0, align 8), (load 1 from %ir.1, align 8)
; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.coerce.dive13) ; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.coerce.dive13)
; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD]](s64) ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD]](s64)
; ALL: $xmm0 = COPY [[ANYEXT]](s128) ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
; ALL: RET 0, implicit $xmm0 ; ALL: RET 0, implicit $xmm0
entry: entry:
%retval = alloca %struct.d1, align 8 %retval = alloca %struct.d1, align 8
%d = alloca %struct.d1, align 8 %d = alloca %struct.d1, align 8
%coerce.dive = getelementptr inbounds %struct.d1, %struct.d1* %d, i32 0, i32 0 %coerce.dive = getelementptr inbounds %struct.d1, %struct.d1* %d, i32 0, i32 0
Show All 16 Linesdefine { double, double } @test_return_d2(double %d.coerce0, double %d.coerce1) {
; ALL: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128) ; ALL: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.d ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.d
; ALL: G_STORE [[TRUNC]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.1) ; ALL: G_STORE [[TRUNC]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.1)
; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C1]](s64) ; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C1]](s64)
; ALL: G_STORE [[TRUNC1]](s64), [[GEP]](p0) :: (store 8 into %ir.2) ; ALL: G_STORE [[TRUNC1]](s64), [[GEP]](p0) :: (store 8 into %ir.2)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64) :: (store 1 into %ir.3, align 8), (load 1 from %ir.4, align 8) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64), 0 :: (store 1 into %ir.3, align 8), (load 1 from %ir.4, align 8)
; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.5) ; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.5)
; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C1]](s64) ; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C1]](s64)
; ALL: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.5 + 8) ; ALL: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.5 + 8)
; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD]](s64) ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD]](s64)
; ALL: $xmm0 = COPY [[ANYEXT]](s128) ; ALL: $xmm0 = COPY [[ANYEXT]](s128)
; ALL: [[ANYEXT1:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD1]](s64) ; ALL: [[ANYEXT1:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD1]](s64)
; ALL: $xmm1 = COPY [[ANYEXT1]](s128) ; ALL: $xmm1 = COPY [[ANYEXT1]](s128)
; ALL: RET 0, implicit $xmm0, implicit $xmm1 ; ALL: RET 0, implicit $xmm0, implicit $xmm1
Show All 17 Linesdefine i32 @test_return_i1(i32 %i.coerce) {
; ALL-LABEL: name: test_return_i1 ; ALL-LABEL: name: test_return_i1
; ALL: bb.1.entry: ; ALL: bb.1.entry:
; ALL: liveins: $edi ; ALL: liveins: $edi
; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY $edi ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i
; ALL: G_STORE [[COPY]](s32), [[FRAME_INDEX1]](p0) :: (store 4 into %ir.coerce.dive2) ; ALL: G_STORE [[COPY]](s32), [[FRAME_INDEX1]](p0) :: (store 4 into %ir.coerce.dive2)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64) :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64), 0 :: (store 1 into %ir.0, align 4), (load 1 from %ir.1, align 4)
; ALL: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %ir.coerce.dive13) ; ALL: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %ir.coerce.dive13)
; ALL: $eax = COPY [[LOAD]](s32) ; ALL: $eax = COPY [[LOAD]](s32)
; ALL: RET 0, implicit $eax ; ALL: RET 0, implicit $eax
entry: entry:
%retval = alloca %struct.i1, align 4 %retval = alloca %struct.i1, align 4
%i = alloca %struct.i1, align 4 %i = alloca %struct.i1, align 4
%coerce.dive = getelementptr inbounds %struct.i1, %struct.i1* %i, i32 0, i32 0 %coerce.dive = getelementptr inbounds %struct.i1, %struct.i1* %i, i32 0, i32 0
store i32 %i.coerce, i32* %coerce.dive, align 4 store i32 %i.coerce, i32* %coerce.dive, align 4
Show All 9 Linesdefine i64 @test_return_i2(i64 %i.coerce) {
; ALL-LABEL: name: test_return_i2 ; ALL-LABEL: name: test_return_i2
; ALL: bb.1.entry: ; ALL: bb.1.entry:
; ALL: liveins: $rdi ; ALL: liveins: $rdi
; ALL: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi ; ALL: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i
; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.0, align 4) ; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.0, align 4)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64) :: (store 1 into %ir.1, align 4), (load 1 from %ir.2, align 4) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64), 0 :: (store 1 into %ir.1, align 4), (load 1 from %ir.2, align 4)
; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.3, align 4) ; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.3, align 4)
; ALL: $rax = COPY [[LOAD]](s64) ; ALL: $rax = COPY [[LOAD]](s64)
; ALL: RET 0, implicit $rax ; ALL: RET 0, implicit $rax
entry: entry:
%retval = alloca %struct.i2, align 4 %retval = alloca %struct.i2, align 4
%i = alloca %struct.i2, align 4 %i = alloca %struct.i2, align 4
%0 = bitcast %struct.i2* %i to i64* %0 = bitcast %struct.i2* %i to i64*
store i64 %i.coerce, i64* %0, align 4 store i64 %i.coerce, i64* %0, align 4
Show All 15 Linesdefine { i64, i32 } @test_return_i3(i64 %i.coerce0, i32 %i.coerce1) {
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i
; ALL: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.coerce ; ALL: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.coerce
; ALL: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.tmp ; ALL: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.tmp
; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX2]](p0) :: (store 8 into %ir.0, align 4) ; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX2]](p0) :: (store 8 into %ir.0, align 4)
; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX2]], [[C1]](s64) ; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX2]], [[C1]](s64)
; ALL: G_STORE [[COPY1]](s32), [[GEP]](p0) :: (store 4 into %ir.1) ; ALL: G_STORE [[COPY1]](s32), [[GEP]](p0) :: (store 4 into %ir.1)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX1]](p0), [[FRAME_INDEX2]](p0), [[C]](s64) :: (store 1 into %ir.2, align 4), (load 1 from %ir.3, align 4) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX1]](p0), [[FRAME_INDEX2]](p0), [[C]](s64), 0 :: (store 1 into %ir.2, align 4), (load 1 from %ir.3, align 4)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64) :: (store 1 into %ir.4, align 4), (load 1 from %ir.5, align 4) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64), 0 :: (store 1 into %ir.4, align 4), (load 1 from %ir.5, align 4)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX3]](p0), [[FRAME_INDEX]](p0), [[C]](s64) :: (store 1 into %ir.6, align 8), (load 1 from %ir.7, align 4) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX3]](p0), [[FRAME_INDEX]](p0), [[C]](s64), 0 :: (store 1 into %ir.6, align 8), (load 1 from %ir.7, align 4)
; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 8 from %ir.tmp) ; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 8 from %ir.tmp)
; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX3]], [[C1]](s64) ; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX3]], [[C1]](s64)
; ALL: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.tmp + 8, align 8) ; ALL: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.tmp + 8, align 8)
; ALL: $rax = COPY [[LOAD]](s64) ; ALL: $rax = COPY [[LOAD]](s64)
; ALL: $edx = COPY [[LOAD1]](s32) ; ALL: $edx = COPY [[LOAD1]](s32)
; ALL: RET 0, implicit $rax, implicit $edx ; ALL: RET 0, implicit $rax, implicit $edx
entry: entry:
%retval = alloca %struct.i3, align 4 %retval = alloca %struct.i3, align 4
Show All 25 Linesdefine { i64, i64 } @test_return_i4(i64 %i.coerce0, i64 %i.coerce1) {
; ALL: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi ; ALL: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; ALL: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval ; ALL: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i ; ALL: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.i
; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.1, align 4) ; ALL: G_STORE [[COPY]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.1, align 4)
; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; ALL: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C1]](s64) ; ALL: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C1]](s64)
; ALL: G_STORE [[COPY1]](s64), [[GEP]](p0) :: (store 8 into %ir.2, align 4) ; ALL: G_STORE [[COPY1]](s64), [[GEP]](p0) :: (store 8 into %ir.2, align 4)
; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64) :: (store 1 into %ir.3, align 4), (load 1 from %ir.4, align 4) ; ALL: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), [[FRAME_INDEX]](p0), [[FRAME_INDEX1]](p0), [[C]](s64), 0 :: (store 1 into %ir.3, align 4), (load 1 from %ir.4, align 4)
; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.5, align 4) ; ALL: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.5, align 4)
; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C1]](s64) ; ALL: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C1]](s64)
; ALL: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.5 + 8, align 4) ; ALL: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.5 + 8, align 4)
; ALL: $rax = COPY [[LOAD]](s64) ; ALL: $rax = COPY [[LOAD]](s64)
; ALL: $rdx = COPY [[LOAD1]](s64) ; ALL: $rdx = COPY [[LOAD1]](s64)
; ALL: RET 0, implicit $rax, implicit $rdx ; ALL: RET 0, implicit $rax, implicit $rdx
entry: entry:
%retval = alloca %struct.i4, align 4 %retval = alloca %struct.i4, align 4
Show All 13 Lines

llvm/trunk/test/MachineVerifier/test_memccpy_intrinsics.mir

# RUN: not llc -o - -march=aarch64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
# REQUIRES: aarch64-registered-target
---
name: test_memcpy_et_al
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
liveins:
body: |
bb.0:
%0:_(p0) = G_IMPLICIT_DEF
%1:_(s64) = G_IMPLICIT_DEF
%2:_(s1) = G_IMPLICIT_DEF
; CHECK: Bad machine code: Expected memcpy intrinsic to have 5 operands
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memcpy), %0(p0), %0(p0), %1(s64)
; CHECK: Bad machine code: Expected memmove intrinsic to have 5 operands
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memmove), %0(p0), %0(p0), %1(s64)
; CHECK: Bad machine code: Expected memset intrinsic to have 5 operands
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.memset), %0(p0), %0(p0), %1(s64)
...