[ARM] Add a vrinta.f16.f16 alias

[dmgreen]

Summary

The v8.1-m ARMARM uses the "vrinta.f16.f16" names, as opposed to "vrinta.f16". This adds an alias for it in the same way that we have for f32 and f64.

[SjoerdMeijer]

Just checking because you mentioned:

The v8.1-m ARMARM uses the "vrinta.f16.f16" names,

But I guess that's also true for v8a, so say in general when FP16 is supported? (that's why the tests are added to -triple armv8a-none-eabi tests)

[dmgreen]

No... The v8-a ARMARM seems to use "vrinta.f16" names. For both Neon and VFP.

8.1-m seems to use "vrinta.f16.f16" for VFP but "vrinta.f16" for MVE.

I'm guessing that's where the alias came from, an attempt to cover both bases.

[SjoerdMeijer]

LGTM

llvm/lib/Target/ARM/ARMInstrVFP.td

def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
                    (outs DPR:$Dd), (ins DPR:$Dm),
                    NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
                    [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
                    Requires<[HasFPARMv8, HasDPVFP]> {
       let Inst{17-16} = rm;
     }
   }
 
+  def : InstAlias<!strconcat("vrint", opc, ".f16.f16\t$Sd, $Sm"),
+                  (!cast<Instruction>(NAME#"H") HPR:$Sd, HPR:$Sm), 0>,
+        Requires<[HasFullFP16]>;
   def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
                   (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
         Requires<[HasFPARMv8]>;
   def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
                   (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,
         Requires<[HasFPARMv8,HasDPVFP]>;
 }
 

llvm/test/MC/ARM/fullfp16-neg.s

@ CHECK: instruction requires: full half-float
 
   vmaxnm.f16 s5, s12, s0
 @ CHECK: instruction requires: full half-float
 
   vminnm.f16 s0, s0, s12
 @ CHECK: instruction requires: full half-float
 
   vrintz.f16 s3, s24
+  vrintz.f16.f16 s3, s24
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintr.f16 s0, s9
+  vrintr.f16.f16 s0, s9
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintx.f16 s10, s14
+  vrintx.f16.f16 s10, s14
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrinta.f16 s12, s1
+  vrinta.f16.f16 s12, s1
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintn.f16 s12, s1
+  vrintn.f16.f16 s12, s1
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintp.f16 s12, s1
+  vrintp.f16.f16 s12, s1
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vrintm.f16 s12, s1
+  vrintm.f16.f16 s12, s1
+@ CHECK: instruction requires: full half-float
 @ CHECK: instruction requires: full half-float
 
   vfma.f16 s2, s7, s4
 @ CHECK: instruction requires: full half-float
 
   vfms.f16 s2, s7, s4
 @ CHECK: instruction requires: full half-float
 

llvm/test/MC/ARM/fullfp16.s

 @ ARM:   vmaxnm.f16 s5, s12, s0    @ encoding: [0x00,0x29,0xc6,0xfe]
 @ THUMB: vmaxnm.f16 s5, s12, s0    @ encoding: [0xc6,0xfe,0x00,0x29]
 
   vminnm.f16 s0, s0, s12
 @ ARM:   vminnm.f16 s0, s0, s12    @ encoding: [0x46,0x09,0x80,0xfe]
 @ THUMB: vminnm.f16 s0, s0, s12    @ encoding: [0x80,0xfe,0x46,0x09]
 
   vrintz.f16 s3, s24
+  vrintz.f16.f16 s3, s24
 @ ARM:   vrintz.f16 s3, s24     @ encoding: [0xcc,0x19,0xf6,0xee]
+@ ARM:   vrintz.f16 s3, s24     @ encoding: [0xcc,0x19,0xf6,0xee]
+@ THUMB: vrintz.f16 s3, s24     @ encoding: [0xf6,0xee,0xcc,0x19]
 @ THUMB: vrintz.f16 s3, s24     @ encoding: [0xf6,0xee,0xcc,0x19]
 
   vrintr.f16 s0, s9
+  vrintr.f16.f16 s0, s9
 @ ARM:   vrintr.f16 s0, s9      @ encoding: [0x64,0x09,0xb6,0xee]
+@ ARM:   vrintr.f16 s0, s9      @ encoding: [0x64,0x09,0xb6,0xee]
+@ THUMB: vrintr.f16 s0, s9      @ encoding: [0xb6,0xee,0x64,0x09]
 @ THUMB: vrintr.f16 s0, s9      @ encoding: [0xb6,0xee,0x64,0x09]
 
   vrintx.f16 s10, s14
+  vrintx.f16.f16 s10, s14
 @ ARM:   vrintx.f16 s10, s14  @ encoding: [0x47,0x59,0xb7,0xee]
+@ ARM:   vrintx.f16 s10, s14  @ encoding: [0x47,0x59,0xb7,0xee]
+@ THUMB: vrintx.f16 s10, s14  @ encoding: [0xb7,0xee,0x47,0x59]
 @ THUMB: vrintx.f16 s10, s14  @ encoding: [0xb7,0xee,0x47,0x59]
 
   vrinta.f16 s12, s1
+  vrinta.f16.f16 s12, s1
+@ ARM:   vrinta.f16 s12, s1    @ encoding: [0x60,0x69,0xb8,0xfe]
 @ ARM:   vrinta.f16 s12, s1    @ encoding: [0x60,0x69,0xb8,0xfe]
 @ THUMB: vrinta.f16 s12, s1    @ encoding: [0xb8,0xfe,0x60,0x69]
+@ THUMB: vrinta.f16 s12, s1    @ encoding: [0xb8,0xfe,0x60,0x69]
 
   vrintn.f16 s12, s1
+  vrintn.f16.f16 s12, s1
+@ ARM:   vrintn.f16 s12, s1    @ encoding: [0x60,0x69,0xb9,0xfe]
 @ ARM:   vrintn.f16 s12, s1    @ encoding: [0x60,0x69,0xb9,0xfe]
 @ THUMB: vrintn.f16 s12, s1    @ encoding: [0xb9,0xfe,0x60,0x69]
+@ THUMB: vrintn.f16 s12, s1    @ encoding: [0xb9,0xfe,0x60,0x69]
 
   vrintp.f16 s12, s1
+  vrintp.f16.f16 s12, s1
+@ ARM:   vrintp.f16 s12, s1    @ encoding: [0x60,0x69,0xba,0xfe]
 @ ARM:   vrintp.f16 s12, s1    @ encoding: [0x60,0x69,0xba,0xfe]
 @ THUMB: vrintp.f16 s12, s1    @ encoding: [0xba,0xfe,0x60,0x69]
+@ THUMB: vrintp.f16 s12, s1    @ encoding: [0xba,0xfe,0x60,0x69]
 
   vrintm.f16 s12, s1
+  vrintm.f16.f16 s12, s1
+@ ARM:   vrintm.f16 s12, s1    @ encoding: [0x60,0x69,0xbb,0xfe]
 @ ARM:   vrintm.f16 s12, s1    @ encoding: [0x60,0x69,0xbb,0xfe]
 @ THUMB: vrintm.f16 s12, s1    @ encoding: [0xbb,0xfe,0x60,0x69]
+@ THUMB: vrintm.f16 s12, s1    @ encoding: [0xbb,0xfe,0x60,0x69]
 
   vfma.f16 s2, s7, s4
 @ ARM:   vfma.f16        s2, s7, s4      @ encoding: [0x82,0x19,0xa3,0xee]
 @ THUMB: vfma.f16        s2, s7, s4      @ encoding: [0xa3,0xee,0x82,0x19]
 
   vfms.f16 s2, s7, s4
 @ ARM:   vfms.f16        s2, s7, s4      @ encoding: [0xc2,0x19,0xa3,0xee]
 @ THUMB: vfms.f16        s2, s7, s4      @ encoding: [0xa3,0xee,0xc2,0x19]