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Differential D68113

[WebAssembly] v128.andnot
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Authored by tlively on Sep 26 2019, 5:25 PM.

Details

Reviewers
aheejin
Commits
rG3fcdd25ad556: [WebAssembly] v128.andnot
rL373041: [WebAssembly] v128.andnot
Summary

As specified at
https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-and-not

Diff Detail

Repository
rL LLVM

Event Timeline

tlively created this revision.Sep 26 2019, 5:25 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 26 2019, 5:25 PM
Herald added subscribers: llvm-commits, sunfish, hiraditya and 3 others. · View Herald Transcript
Harbormaster completed remote builds in B38628: Diff 222060.Sep 26 2019, 5:25 PM
aheejin accepted this revision.Sep 26 2019, 6:40 PM
This revision is now accepted and ready to land.Sep 26 2019, 6:40 PM
Closed by commit rL373041: [WebAssembly] v128.andnot (authored by tlively). · Explain WhySep 26 2019, 7:10 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
WebAssembly/
5 lines
test/
CodeGen/
WebAssembly/
63 lines
MC/
WebAssembly/
3 lines

Diff 222070

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

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// Bitwise logic: v128.and / v128.or / v128.xor // Bitwise logic: v128.and / v128.or / v128.xor
let isCommutable = 1 in { let isCommutable = 1 in {
defm AND : SIMDBitwise<and, "and", 77>; defm AND : SIMDBitwise<and, "and", 77>;
defm OR : SIMDBitwise<or, "or", 78>; defm OR : SIMDBitwise<or, "or", 78>;
defm XOR : SIMDBitwise<xor, "xor", 79>; defm XOR : SIMDBitwise<xor, "xor", 79>;
} // isCommutable = 1 } // isCommutable = 1
// Bitwise logic: v128.andnot
def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>;
let Predicates = [HasUnimplementedSIMD128] in
defm ANDNOT : SIMDBitwise<andnot, "andnot", 216>;
// Bitwise select: v128.bitselect // Bitwise select: v128.bitselect
foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
defm BITSELECT_#vec_t : defm BITSELECT_#vec_t :
SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
[(set (vec_t V128:$dst), [(set (vec_t V128:$dst),
(vec_t (int_wasm_bitselect (vec_t (int_wasm_bitselect
(vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c) (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
)) ))
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llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll

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define <16 x i8> @not_v16i8(<16 x i8> %x) { define <16 x i8> @not_v16i8(<16 x i8> %x) {
%a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, %a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1,
i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
i8 -1, i8 -1, i8 -1, i8 -1> i8 -1, i8 -1, i8 -1, i8 -1>
ret <16 x i8> %a ret <16 x i8> %a
} }
; CHECK-LABEL: andnot_v16i8:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128.andnot
; SIMD128-NEXT: .functype andnot_v16i8 (v128, v128) -> (v128){{$}}
; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
; SIMD128-FAST-NEXT: v128.not
; SIMD128-FAST-NEXT: v128.and
; SIMD128-FAST-NEXT: return
define <16 x i8> @andnot_v16i8(<16 x i8> %x, <16 x i8> %y) {
%inv_y = xor <16 x i8> %y,
<i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%a = and <16 x i8> %x, %inv_y
ret <16 x i8> %a
}
; CHECK-LABEL: bitselect_v16i8: ; CHECK-LABEL: bitselect_v16i8:
; NO-SIMD128-NOT: v128 ; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
; SIMD128-FAST-NEXT: v128.and ; SIMD128-FAST-NEXT: v128.and
; SIMD128-FAST-NEXT: v128.not ; SIMD128-FAST-NEXT: v128.not
; SIMD128-FAST-NEXT: v128.and ; SIMD128-FAST-NEXT: v128.and
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; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @not_v8i16(<8 x i16> %x) { define <8 x i16> @not_v8i16(<8 x i16> %x) {
%a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, %a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1,
i16 -1, i16 -1, i16 -1, i16 -1> i16 -1, i16 -1, i16 -1, i16 -1>
ret <8 x i16> %a ret <8 x i16> %a
} }
; CHECK-LABEL: andnot_v8i16:
; SIMD128-VM-NOT: v128.andnot
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype andnot_v8i16 (v128, v128) -> (v128){{$}}
; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
; SIMD128-FAST-NEXT: v128.not
; SIMD128-FAST-NEXT: v128.and
; SIMD128-FAST-NEXT: return
define <8 x i16> @andnot_v8i16(<8 x i16> %x, <8 x i16> %y) {
%inv_y = xor <8 x i16> %y,
<i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%a = and <8 x i16> %x, %inv_y
ret <8 x i16> %a
}
; CHECK-LABEL: bitselect_v8i16: ; CHECK-LABEL: bitselect_v8i16:
; NO-SIMD128-NOT: v128 ; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
; SIMD128-FAST-NEXT: v128.and ; SIMD128-FAST-NEXT: v128.and
; SIMD128-FAST-NEXT: v128.not ; SIMD128-FAST-NEXT: v128.not
; SIMD128-FAST-NEXT: v128.and ; SIMD128-FAST-NEXT: v128.and
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; SIMD128-NEXT: .functype not_v4i32 (v128) -> (v128){{$}} ; SIMD128-NEXT: .functype not_v4i32 (v128) -> (v128){{$}}
; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @not_v4i32(<4 x i32> %x) { define <4 x i32> @not_v4i32(<4 x i32> %x) {
%a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %a ret <4 x i32> %a
} }
; CHECK-LABEL: andnot_v4i32:
; SIMD128-VM-NOT: v128.andnot
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype andnot_v4i32 (v128, v128) -> (v128){{$}}
; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
; SIMD128-FAST-NEXT: v128.not
; SIMD128-FAST-NEXT: v128.and
; SIMD128-FAST-NEXT: return
define <4 x i32> @andnot_v4i32(<4 x i32> %x, <4 x i32> %y) {
%inv_y = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
%a = and <4 x i32> %x, %inv_y
ret <4 x i32> %a
}
; CHECK-LABEL: bitselect_v4i32: ; CHECK-LABEL: bitselect_v4i32:
; NO-SIMD128-NOT: v128 ; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
; SIMD128-FAST-NEXT: v128.not ; SIMD128-FAST-NEXT: v128.not
; SIMD128-FAST-NEXT: v128.and ; SIMD128-FAST-NEXT: v128.and
; SIMD128-FAST-NEXT: v128.and ; SIMD128-FAST-NEXT: v128.and
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; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}} ; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}}
; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}} ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @not_v2i64(<2 x i64> %x) { define <2 x i64> @not_v2i64(<2 x i64> %x) {
%a = xor <2 x i64> %x, <i64 -1, i64 -1> %a = xor <2 x i64> %x, <i64 -1, i64 -1>
ret <2 x i64> %a ret <2 x i64> %a
} }
; CHECK-LABEL: andnot_v2i64:
; SIMD128-VM-NOT: v128.andnot
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype andnot_v2i64 (v128, v128) -> (v128){{$}}
; SIMD128-SLOW-NEXT: v128.andnot $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
; SIMD128-FAST-NEXT: v128.not
; SIMD128-FAST-NEXT: v128.and
; SIMD128-FAST-NEXT: return
define <2 x i64> @andnot_v2i64(<2 x i64> %x, <2 x i64> %y) {
%inv_y = xor <2 x i64> %y, <i64 -1, i64 -1>
%a = and <2 x i64> %x, %inv_y
ret <2 x i64> %a
}
; CHECK-LABEL: bitselect_v2i64: ; CHECK-LABEL: bitselect_v2i64:
; NO-SIMD128-NOT: v128 ; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128 ; SIMD128-VM-NOT: v128
; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}} ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}} ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
; SIMD128-FAST-NEXT: v128.not ; SIMD128-FAST-NEXT: v128.not
; SIMD128-FAST-NEXT: v128.and ; SIMD128-FAST-NEXT: v128.and
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llvm/trunk/test/MC/WebAssembly/simd-encodings.s

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i32x4.load16x4_u 32 i32x4.load16x4_u 32
# CHECK: i64x2.load32x2_s 32 # encoding: [0xfd,0xd6,0x01,0x03,0x20] # CHECK: i64x2.load32x2_s 32 # encoding: [0xfd,0xd6,0x01,0x03,0x20]
i64x2.load32x2_s 32 i64x2.load32x2_s 32
# CHECK: i64x2.load32x2_u 32 # encoding: [0xfd,0xd7,0x01,0x03,0x20] # CHECK: i64x2.load32x2_u 32 # encoding: [0xfd,0xd7,0x01,0x03,0x20]
i64x2.load32x2_u 32 i64x2.load32x2_u 32
# CHECK: v128.andnot # encoding: [0xfd,0xd8,0x01]
v128.andnot
end_function end_function