[MIPS GlobalISel] Lower aggregate structure return arguments

[Petar.Avramovic]

Summary

Implement aggregate structure split to simpler types in splitToValueTypes.
splitToValueTypes is used for return values.
According to MipsABIInfo from clang/lib/CodeGen/TargetInfo.cpp,
aggregate structure arguments for O32 always get simplified and thus
will remain unsupported by the MIPS GlobalISel for the time being.
For O32, aggregate structures can be encountered only for complex number
returns e.g. 'complex float' or 'complex double' from <complex.h>.

[atanasyan]

LGTM
It looks like the tests check calling the splitToValueTypes from the MipsCallLowering::lowerReturn only. If it's true, could you add more tests to cover passing arguments?

[Petar.Avramovic]

It looks like the tests check calling the splitToValueTypes from the MipsCallLowering::lowerReturn only.

Right. I will add tests for call of a function that returns aggregate structure.
Now that I think of it, I didn't encounter any aggregate structure as an argument in test-suite.
They get turned into inreg arguments like in this tests,
maybe we could mark aggregate structure as unsupported if they are arguments for now
and only allow them if they are return values?

lib/Target/Mips/MipsCallLowering.cpp

466

If yes, then we could also inline old splitToValueTypes here.

586

and here.

[atanasyan]

In D67963#1680964, @Petar.Avramovic wrote:

It looks like the tests check calling the splitToValueTypes from the MipsCallLowering::lowerReturn only.

Right. I will add tests for call of a function that returns aggregate structure.
Now that I think of it, I didn't encounter any aggregate structure as an argument in test-suite.
They get turned into inreg arguments like in this tests,

I think the following code is affected by the change in MipsCallLowering::lowerFormalArguments.

define { double, double } @bar({ double, double } %s) {
entry:
  %retval = alloca { double, double }, align 8
  %inval = alloca { double, double }, align 8
  store { double, double } %s, { double, double }* %inval, align 8
  %0 = bitcast { double, double }* %retval to i8*
  %1 = bitcast { double, double }* %inval to i8*
  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %0, i8* align 8 %1, i32 16, i1 false)
  %2 = load { double, double }, { double, double }* %retval, align 8
  ret { double, double } %2
}

declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)

I do not know how to get such LLVM-IR code from, for example, C code. In Clang the MipsABIInfo::classifyArgumentType coerces an aggregate argument into series of i32 arguments. But if your patch generates a correct code for aggregate arguments (I didn't check) let's add a test case and keep the patch as-is.

[Petar.Avramovic]

I also looked into MipsABIInfo today and it doesn't allow any aggregate structure like argument for O32, and only aggregate structure that can be encountered is return value that has ComplexType. Even structure with two floats or doubles returns get transformed into pointer argument despite the fact it is similar thing as complex float or complex double.
I am not so sure about correctness for aggregate struct arguments since I can't generate them with clang, and for that reason I would mark aggregate structures arguments as unsupported for now, and only handle aggregate structure returns. When test with aggregate structure arguments appears we can add handling for it.

[Petar.Avramovic]

Aggregate structure arguments remain unsupported like before this patch.
Support aggregate returns and update tests.

[atanasyan]

LGTM

lib/Target/Mips/MipsCallLowering.h

private:
   /// type.
   template <typename T>
   void subTargetRegTypeForCallingConv(const Function &F, ArrayRef<ArgInfo> Args,
                                       ArrayRef<unsigned> OrigArgIndices,
                                       SmallVectorImpl<T> &ISDArgs) const;
 
   /// Split structures and arrays, save original argument indices since
   /// Mips calling convention needs info about original argument type.
-  void splitToValueTypes(const ArgInfo &OrigArg, unsigned OriginalIndex,
+  void splitToValueTypes(const DataLayout &DL, const ArgInfo &OrigArg,
+                         unsigned OriginalIndex,
                          SmallVectorImpl<ArgInfo> &SplitArgs,
                          SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_MIPS_MIPSCALLLOWERING_H

lib/Target/Mips/MipsCallLowering.cpp

 
 static bool isSupportedType(Type *T) {
   if (T->isIntegerTy())
     return true;
   if (T->isPointerTy())
     return true;
   if (T->isFloatingPointTy())
     return true;
+  if (T->isAggregateType())
+    return true;
   return false;
 }
 
 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
                                              const ISD::ArgFlagsTy &Flags) {
   // > does not mean loss of information as type RegisterVT can't hold type VT,
   // it means that type VT is split into multiple registers of type RegisterVT
   if (VT.getSizeInBits() >= RegisterVT.getSizeInBits())
bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
   if (Val != nullptr && !isSupportedType(Val->getType()))
     return false;
 
   if (!VRegs.empty()) {
     MachineFunction &MF = MIRBuilder.getMF();
     const Function &F = MF.getFunction();
     const DataLayout &DL = MF.getDataLayout();
     const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
-    LLVMContext &Ctx = Val->getType()->getContext();
-
-    SmallVector<EVT, 4> SplitEVTs;
-    ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
-    assert(VRegs.size() == SplitEVTs.size() &&
-           "For each split Type there should be exactly one VReg.");
 
     SmallVector<ArgInfo, 8> RetInfos;
     SmallVector<unsigned, 8> OrigArgIndices;
 
-    for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
-      ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
-      setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
-      splitToValueTypes(CurArgInfo, 0, RetInfos, OrigArgIndices);
-    }
+    ArgInfo ArgRetInfo(VRegs, Val->getType());
+    setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F);
+    splitToValueTypes(DL, ArgRetInfo, 0, RetInfos, OrigArgIndices);
 
     SmallVector<ISD::OutputArg, 8> Outs;
     subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
 
     SmallVector<CCValAssign, 16> ArgLocs;
     MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
                        F.getContext());
     CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
bool MipsCallLowering::lowerFormalArguments(
   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
 
   SmallVector<ArgInfo, 8> ArgInfos;
   SmallVector<unsigned, 8> OrigArgIndices;
   unsigned i = 0;
   for (auto &Arg : F.args()) {
     ArgInfo AInfo(VRegs[i], Arg.getType());
     setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
-    splitToValueTypes(AInfo, i, ArgInfos, OrigArgIndices);
+    splitToValueTypes(DL, AInfo, i, ArgInfos, OrigArgIndices);
     ++i;
   }
 
   SmallVector<ISD::InputArg, 8> Ins;
   subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
 
   SmallVector<CCValAssign, 16> ArgLocs;
   MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy())
       return false;
   }
 
   if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedType(Info.OrigRet.Ty))
     return false;
 
   MachineFunction &MF = MIRBuilder.getMF();
   const Function &F = MF.getFunction();
+  const DataLayout &DL = MF.getDataLayout();
   const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
   const MipsTargetMachine &TM =
       static_cast<const MipsTargetMachine &>(MF.getTarget());
   const MipsABIInfo &ABI = TM.getABI();
 
   MachineInstrBuilder CallSeqStart =
       MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
 
bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   SmallVector<unsigned, 8> OrigArgIndices;
   unsigned i = 0;
   for (auto &Arg : Info.OrigArgs) {
 
     TargetLowering::ArgListEntry Entry;
     Entry.Ty = Arg.Ty;
     FuncOrigArgs.push_back(Entry);
 
-    splitToValueTypes(Arg, i, ArgInfos, OrigArgIndices);
+    splitToValueTypes(DL, Arg, i, ArgInfos, OrigArgIndices);
     ++i;
   }
 
   SmallVector<ISD::OutputArg, 8> Outs;
   subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
 
   SmallVector<CCValAssign, 8> ArgLocs;
   bool IsCalleeVarArg = false;
if (MIB->getOpcode() == Mips::JALRPseudo) {
     MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
                          *STI.getRegBankInfo());
   }
 
   if (!Info.OrigRet.Ty->isVoidTy()) {
     ArgInfos.clear();
     SmallVector<unsigned, 8> OrigRetIndices;
 
-    splitToValueTypes(Info.OrigRet, 0, ArgInfos, OrigRetIndices);
+    splitToValueTypes(DL, Info.OrigRet, 0, ArgInfos, OrigRetIndices);
 
     SmallVector<ISD::InputArg, 8> Ins;
     subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
 
     SmallVector<CCValAssign, 8> ArgLocs;
     MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
                        F.getContext());
 
for (unsigned i = 0; i < NumRegs; ++i) {
       ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
                            0);
     }
     ++ArgNo;
   }
 }
 
 void MipsCallLowering::splitToValueTypes(
-    const ArgInfo &OrigArg, unsigned OriginalIndex,
+    const DataLayout &DL, const ArgInfo &OrigArg, unsigned OriginalIndex,
     SmallVectorImpl<ArgInfo> &SplitArgs,
     SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
 
-  // TODO : perform structure and array split. For now we only deal with
-  // types that pass isSupportedType check.
-  SplitArgs.push_back(OrigArg);
+  SmallVector<EVT, 4> SplitEVTs;
+  SmallVector<Register, 4> SplitVRegs;
+  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
+  LLVMContext &Ctx = OrigArg.Ty->getContext();
+
+  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitEVTs);
+
+  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
+    ArgInfo Info = ArgInfo{OrigArg.Regs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
+    Info.Flags = OrigArg.Flags;
+    SplitArgs.push_back(Info);
     SplitArgsOrigIndices.push_back(OriginalIndex);
   }
+}

test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+
+define { float, float } @ret_complex_float(i32 inreg %a.coerce0, i32 inreg %a.coerce1) {
+  ; MIPS32-LABEL: name: ret_complex_float
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
+  ; MIPS32:   [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.a
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX1]](p0)
+  ; MIPS32:   G_STORE [[COPY]](s32), [[COPY2]](p0) :: (store 4 into %ir.1)
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C]](s32)
+  ; MIPS32:   G_STORE [[COPY1]](s32), [[GEP]](p0) :: (store 4 into %ir.2)
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX1]](p0)
+  ; MIPS32:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY3]](p0) :: (load 4 from %ir.a.realp)
+  ; MIPS32:   [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C]](s32)
+  ; MIPS32:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.a.imagp)
+  ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX]](p0)
+  ; MIPS32:   [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C]](s32)
+  ; MIPS32:   G_STORE [[LOAD]](s32), [[COPY4]](p0) :: (store 4 into %ir.retval.realp)
+  ; MIPS32:   G_STORE [[LOAD1]](s32), [[GEP2]](p0) :: (store 4 into %ir.retval.imagp)
+  ; MIPS32:   [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %ir.retval)
+  ; MIPS32:   [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C]](s32)
+  ; MIPS32:   [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load 4 from %ir.retval + 4)
+  ; MIPS32:   $f0 = COPY [[LOAD2]](s32)
+  ; MIPS32:   $f2 = COPY [[LOAD3]](s32)
+  ; MIPS32:   RetRA implicit $f0, implicit $f2
+entry:
+  %retval = alloca { float, float }, align 4
+  %a = alloca { float, float }, align 4
+  %0 = bitcast { float, float }* %a to { i32, i32 }*
+  %1 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %0, i32 0, i32 0
+  store i32 %a.coerce0, i32* %1, align 4
+  %2 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %0, i32 0, i32 1
+  store i32 %a.coerce1, i32* %2, align 4
+  %a.realp = getelementptr inbounds { float, float }, { float, float }* %a, i32 0, i32 0
+  %a.real = load float, float* %a.realp, align 4
+  %a.imagp = getelementptr inbounds { float, float }, { float, float }* %a, i32 0, i32 1
+  %a.imag = load float, float* %a.imagp, align 4
+  %retval.realp = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 0
+  %retval.imagp = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 1
+  store float %a.real, float* %retval.realp, align 4
+  store float %a.imag, float* %retval.imagp, align 4
+  %3 = load { float, float }, { float, float }* %retval, align 4
+  ret { float, float } %3
+}
+
+define { double, double } @ret_complex_double(i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %a.coerce2, i32 inreg %a.coerce3) {
+  ; MIPS32-LABEL: name: ret_complex_double
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1, $a2, $a3
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+  ; MIPS32:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
+  ; MIPS32:   [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.a
+  ; MIPS32:   [[COPY4:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX1]](p0)
+  ; MIPS32:   G_STORE [[COPY]](s32), [[COPY4]](p0) :: (store 4 into %ir.1, align 8)
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+  ; MIPS32:   [[GEP:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C]](s32)
+  ; MIPS32:   G_STORE [[COPY1]](s32), [[GEP]](p0) :: (store 4 into %ir.2)
+  ; MIPS32:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+  ; MIPS32:   [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C1]](s32)
+  ; MIPS32:   G_STORE [[COPY2]](s32), [[GEP1]](p0) :: (store 4 into %ir.3, align 8)
+  ; MIPS32:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+  ; MIPS32:   [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C2]](s32)
+  ; MIPS32:   G_STORE [[COPY3]](s32), [[GEP2]](p0) :: (store 4 into %ir.4)
+  ; MIPS32:   [[COPY5:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX1]](p0)
+  ; MIPS32:   [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY5]](p0) :: (load 8 from %ir.a.realp)
+  ; MIPS32:   [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX1]], [[C1]](s32)
+  ; MIPS32:   [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP3]](p0) :: (load 8 from %ir.a.imagp)
+  ; MIPS32:   [[COPY6:%[0-9]+]]:_(p0) = COPY [[FRAME_INDEX]](p0)
+  ; MIPS32:   [[GEP4:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C1]](s32)
+  ; MIPS32:   G_STORE [[LOAD]](s64), [[COPY6]](p0) :: (store 8 into %ir.retval.realp)
+  ; MIPS32:   G_STORE [[LOAD1]](s64), [[GEP4]](p0) :: (store 8 into %ir.retval.imagp)
+  ; MIPS32:   [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load 8 from %ir.retval)
+  ; MIPS32:   [[GEP5:%[0-9]+]]:_(p0) = G_GEP [[FRAME_INDEX]], [[C1]](s32)
+  ; MIPS32:   [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[GEP5]](p0) :: (load 8 from %ir.retval + 8)
+  ; MIPS32:   $d0 = COPY [[LOAD2]](s64)
+  ; MIPS32:   $d1 = COPY [[LOAD3]](s64)
+  ; MIPS32:   RetRA implicit $d0, implicit $d1
+entry:
+  %retval = alloca { double, double }, align 8
+  %a = alloca { double, double }, align 8
+  %0 = bitcast { double, double }* %a to { i32, i32, i32, i32 }*
+  %1 = getelementptr inbounds { i32, i32, i32, i32 }, { i32, i32, i32, i32 }* %0, i32 0, i32 0
+  store i32 %a.coerce0, i32* %1, align 8
+  %2 = getelementptr inbounds { i32, i32, i32, i32 }, { i32, i32, i32, i32 }* %0, i32 0, i32 1
+  store i32 %a.coerce1, i32* %2, align 4
+  %3 = getelementptr inbounds { i32, i32, i32, i32 }, { i32, i32, i32, i32 }* %0, i32 0, i32 2
+  store i32 %a.coerce2, i32* %3, align 8
+  %4 = getelementptr inbounds { i32, i32, i32, i32 }, { i32, i32, i32, i32 }* %0, i32 0, i32 3
+  store i32 %a.coerce3, i32* %4, align 4
+  %a.realp = getelementptr inbounds { double, double }, { double, double }* %a, i32 0, i32 0
+  %a.real = load double, double* %a.realp, align 8
+  %a.imagp = getelementptr inbounds { double, double }, { double, double }* %a, i32 0, i32 1
+  %a.imag = load double, double* %a.imagp, align 8
+  %retval.realp = getelementptr inbounds { double, double }, { double, double }* %retval, i32 0, i32 0
+  %retval.imagp = getelementptr inbounds { double, double }, { double, double }* %retval, i32 0, i32 1
+  store double %a.real, double* %retval.realp, align 8
+  store double %a.imag, double* %retval.imagp, align 8
+  %5 = load { double, double }, { double, double }* %retval, align 8
+  ret { double, double } %5
+}

test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define { float, float } @ret_complex_float(i32 inreg %a.coerce0, i32 inreg %a.coerce1) {
+; MIPS32-LABEL: ret_complex_float:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -16
+; MIPS32-NEXT:    .cfi_def_cfa_offset 16
+; MIPS32-NEXT:    addiu $1, $sp, 8
+; MIPS32-NEXT:    addiu $2, $sp, 0
+; MIPS32-NEXT:    sw $4, 0($2)
+; MIPS32-NEXT:    sw $5, 4($2)
+; MIPS32-NEXT:    lw $3, 0($2)
+; MIPS32-NEXT:    lw $2, 4($2)
+; MIPS32-NEXT:    sw $3, 0($1)
+; MIPS32-NEXT:    sw $2, 4($1)
+; MIPS32-NEXT:    lwc1 $f0, 0($1)
+; MIPS32-NEXT:    lwc1 $f2, 4($1)
+; MIPS32-NEXT:    addiu $sp, $sp, 16
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %retval = alloca { float, float }, align 4
+  %a = alloca { float, float }, align 4
+  %0 = bitcast { float, float }* %a to { i32, i32 }*
+  %1 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %0, i32 0, i32 0
+  store i32 %a.coerce0, i32* %1, align 4
+  %2 = getelementptr inbounds { i32, i32 }, { i32, i32 }* %0, i32 0, i32 1
+  store i32 %a.coerce1, i32* %2, align 4
+  %a.realp = getelementptr inbounds { float, float }, { float, float }* %a, i32 0, i32 0
+  %a.real = load float, float* %a.realp, align 4
+  %a.imagp = getelementptr inbounds { float, float }, { float, float }* %a, i32 0, i32 1
+  %a.imag = load float, float* %a.imagp, align 4
+  %retval.realp = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 0
+  %retval.imagp = getelementptr inbounds { float, float }, { float, float }* %retval, i32 0, i32 1
+  store float %a.real, float* %retval.realp, align 4
+  store float %a.imag, float* %retval.imagp, align 4
+  %3 = load { float, float }, { float, float }* %retval, align 4
+  ret { float, float } %3
+}
+
+define { double, double } @ret_complex_double(i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %a.coerce2, i32 inreg %a.coerce3) {
+; MIPS32-LABEL: ret_complex_double:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -32
+; MIPS32-NEXT:    .cfi_def_cfa_offset 32
+; MIPS32-NEXT:    addiu $1, $sp, 16
+; MIPS32-NEXT:    addiu $2, $sp, 0
+; MIPS32-NEXT:    sw $4, 0($2)
+; MIPS32-NEXT:    sw $5, 4($2)
+; MIPS32-NEXT:    sw $6, 8($2)
+; MIPS32-NEXT:    sw $7, 12($2)
+; MIPS32-NEXT:    ldc1 $f0, 0($2)
+; MIPS32-NEXT:    ldc1 $f2, 8($2)
+; MIPS32-NEXT:    sdc1 $f0, 0($1)
+; MIPS32-NEXT:    sdc1 $f2, 8($1)
+; MIPS32-NEXT:    ldc1 $f0, 0($1)
+; MIPS32-NEXT:    ldc1 $f2, 8($1)
+; MIPS32-NEXT:    addiu $sp, $sp, 32
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %retval = alloca { double, double }, align 8
+  %a = alloca { double, double }, align 8
+  %0 = bitcast { double, double }* %a to { i32, i32, i32, i32 }*
+  %1 = getelementptr inbounds { i32, i32, i32, i32 }, { i32, i32, i32, i32 }* %0, i32 0, i32 0
+  store i32 %a.coerce0, i32* %1, align 8
+  %2 = getelementptr inbounds { i32, i32, i32, i32 }, { i32, i32, i32, i32 }* %0, i32 0, i32 1
+  store i32 %a.coerce1, i32* %2, align 4
+  %3 = getelementptr inbounds { i32, i32, i32, i32 }, { i32, i32, i32, i32 }* %0, i32 0, i32 2
+  store i32 %a.coerce2, i32* %3, align 8
+  %4 = getelementptr inbounds { i32, i32, i32, i32 }, { i32, i32, i32, i32 }* %0, i32 0, i32 3
+  store i32 %a.coerce3, i32* %4, align 4
+  %a.realp = getelementptr inbounds { double, double }, { double, double }* %a, i32 0, i32 0
+  %a.real = load double, double* %a.realp, align 8
+  %a.imagp = getelementptr inbounds { double, double }, { double, double }* %a, i32 0, i32 1
+  %a.imag = load double, double* %a.imagp, align 8
+  %retval.realp = getelementptr inbounds { double, double }, { double, double }* %retval, i32 0, i32 0
+  %retval.imagp = getelementptr inbounds { double, double }, { double, double }* %retval, i32 0, i32 1
+  store double %a.real, double* %retval.realp, align 8
+  store double %a.imag, double* %retval.imagp, align 8
+  %5 = load { double, double }, { double, double }* %retval, align 8
+  ret { double, double } %5
+}