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AMDGPU/GlobalISel: Allow scc/vcc alternative mappings for s1 constants
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Authored by arsenm on Sep 15 2019, 4:40 PM.

Reviewers

ping

LGTM

This revision is now accepted and ready to land.Sep 29 2019, 9:28 PM

r373295

Path

Size

lib/

Target/

AMDGPU/

16 lines

Show First 20 Lines • Show All 333 Lines • ▼ Show 20 Lines	AMDGPURegisterBankInfo::getInstrAlternativeMappings(
const MachineInstr &MI) const {		const MachineInstr &MI) const {

const MachineFunction &MF = *MI.getParent()->getParent();		const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();		const MachineRegisterInfo &MRI = MF.getRegInfo();


InstructionMappings AltMappings;		InstructionMappings AltMappings;
switch (MI.getOpcode()) {		switch (MI.getOpcode()) {
case TargetOpcode::G_CONSTANT:		case TargetOpcode::G_CONSTANT: {
		unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
		if (Size == 1) {
		static const OpRegBankEntry<1> Table[4] = {
		{ { AMDGPU::VGPRRegBankID }, 1 },
		{ { AMDGPU::SGPRRegBankID }, 1 },
		{ { AMDGPU::VCCRegBankID }, 1 },
		{ { AMDGPU::SCCRegBankID }, 1 }
		};

		return addMappingFromTable<1>(MI, MRI, { 0 }, Table);
		}

		LLVM_FALLTHROUGH;
		}
case TargetOpcode::G_FCONSTANT:		case TargetOpcode::G_FCONSTANT:
case TargetOpcode::G_FRAME_INDEX:		case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE: {		case TargetOpcode::G_GLOBAL_VALUE: {
static const OpRegBankEntry<1> Table[2] = {		static const OpRegBankEntry<1> Table[2] = {
{ { AMDGPU::VGPRRegBankID }, 1 },		{ { AMDGPU::VGPRRegBankID }, 1 },
{ { AMDGPU::SGPRRegBankID }, 1 }		{ { AMDGPU::SGPRRegBankID }, 1 }
};		};

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