AMDGPU/GlobalISel: Select s1 src G_SITOFP/G_UITOFP

[arsenm]

ping

[nhaehnle]

LGTM

[arsenm]

r373298

lib/Target/AMDGPU/AMDGPUInstructionSelector.h

private:
 
   MachineOperand getSubOperand64(MachineOperand &MO,
                                  const TargetRegisterClass &SubRC,
                                  unsigned SubIdx) const;
   bool selectCOPY(MachineInstr &I) const;
   bool selectPHI(MachineInstr &I) const;
   bool selectG_TRUNC(MachineInstr &I) const;
   bool selectG_SZA_EXT(MachineInstr &I) const;
+  bool selectG_SITOFP_UITOFP(MachineInstr &I) const;
   bool selectG_CONSTANT(MachineInstr &I) const;
   bool selectG_AND_OR_XOR(MachineInstr &I) const;
   bool selectG_ADD_SUB(MachineInstr &I) const;
   bool selectG_UADDO_USUBO(MachineInstr &I) const;
   bool selectG_EXTRACT(MachineInstr &I) const;
   bool selectG_MERGE_VALUES(MachineInstr &I) const;
   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
   bool selectG_GEP(MachineInstr &I) const;

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

if (SrcBank->getID() == AMDGPU::SGPRRegBankID && DstSize <= 64) {
 
     I.eraseFromParent();
     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, MRI);
   }
 
   return false;
 }
 
+static int64_t getFPTrueImmVal(unsigned Size, bool Signed) {
+  switch (Size) {
+  case 16:
+    return Signed ? 0xBC00 : 0x3C00;
+  case 32:
+    return Signed ? 0xbf800000 : 0x3f800000;
+  case 64:
+    return Signed ? 0xbff0000000000000 : 0x3ff0000000000000;
+  default:
+    llvm_unreachable("Invalid FP type size");
+  }
+}
+
+bool AMDGPUInstructionSelector::selectG_SITOFP_UITOFP(MachineInstr &I) const {
+  MachineBasicBlock *MBB = I.getParent();
+  MachineFunction *MF = MBB->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+  Register Src = I.getOperand(1).getReg();
+  if (!isSCC(Src, MRI))
+    return selectImpl(I, *CoverageInfo);
+
+  bool Signed = I.getOpcode() == AMDGPU::G_SITOFP;
+  Register DstReg = I.getOperand(0).getReg();
+  const LLT DstTy = MRI.getType(DstReg);
+  const unsigned DstSize = DstTy.getSizeInBits();
+  const DebugLoc &DL = I.getDebugLoc();
+
+  BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
+    .addReg(Src);
+
+  unsigned NewOpc =
+    DstSize > 32 ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
+  auto MIB = BuildMI(*MBB, I, DL, TII.get(NewOpc), DstReg)
+    .addImm(0)
+    .addImm(getFPTrueImmVal(DstSize, Signed));
+
+  if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
+    return false;
+
+  I.eraseFromParent();
+  return true;
+}
+
 bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
   MachineBasicBlock *BB = I.getParent();
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
   MachineOperand &ImmOp = I.getOperand(1);
 
   // The AMDGPU backend only supports Imm operands and not CImm or FPImm.
   if (ImmOp.isFPImm()) {
bool AMDGPUInstructionSelector::select(MachineInstr &I) {
   case TargetOpcode::G_STORE:
     return selectG_STORE(I);
   case TargetOpcode::G_TRUNC:
     return selectG_TRUNC(I);
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
   case TargetOpcode::G_ANYEXT:
     return selectG_SZA_EXT(I);
+  case TargetOpcode::G_SITOFP:
+  case TargetOpcode::G_UITOFP:
+    return selectG_SITOFP_UITOFP(I);
   case TargetOpcode::G_BRCOND:
     return selectG_BRCOND(I);
   case TargetOpcode::G_FRAME_INDEX:
     return selectG_FRAME_INDEX(I);
   case TargetOpcode::G_FENCE:
     // FIXME: Tablegen importer doesn't handle the imm operands correctly, and
     // is checking for G_CONSTANT
     I.setDesc(TII.get(AMDGPU::ATOMIC_FENCE));

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
     .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
                {S32, S1}, {S64, S1}, {S16, S1},
                {S96, S32},
                // FIXME: Hack
                {S64, LLT::scalar(33)},
                {S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}})
     .scalarize(0);
 
-  // TODO: Legal for s1->s64, requires split for VALU.
+  // TODO: Split s1->s64 during regbankselect for VALU.
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
-    .legalFor({{S32, S32}, {S64, S32}, {S16, S32}, {S32, S1}, {S16, S1}})
+    .legalFor({{S32, S32}, {S64, S32}, {S16, S32}, {S32, S1}, {S16, S1}, {S64, S1}})
     .lowerFor({{S32, S64}})
     .customFor({{S64, S64}})
     .scalarize(0);
 
   getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
     .legalFor({{S32, S32}, {S32, S64}, {S32, S16}})
     .scalarize(0);
 

lib/Target/AMDGPU/SIInstructions.td

 }
 } // end isWave32
 
 def : GCNPat <
   (f16 (sint_to_fp i1:$src)),
   (V_CVT_F16_F32_e32 (
       V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                         /*src1mod*/(i32 0), /*src1*/(i32 CONST.FP32_NEG_ONE),
-                        $src))
+                        SSrc_i1:$src))
 >;
 
 def : GCNPat <
   (f16 (uint_to_fp i1:$src)),
   (V_CVT_F16_F32_e32 (
       V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                         /*src1mod*/(i32 0), /*src1*/(i32 CONST.FP32_ONE),
-                        $src))
+                        SSrc_i1:$src))
 >;
 
 def : GCNPat <
   (f32 (sint_to_fp i1:$src)),
   (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                         /*src1mod*/(i32 0), /*src1*/(i32 CONST.FP32_NEG_ONE),
-                        $src)
+                        SSrc_i1:$src)
 >;
 
 def : GCNPat <
   (f32 (uint_to_fp i1:$src)),
   (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                         /*src1mod*/(i32 0), /*src1*/(i32 CONST.FP32_ONE),
-                        $src)
+                        SSrc_i1:$src)
 >;
 
 def : GCNPat <
   (f64 (sint_to_fp i1:$src)),
   (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                                         /*src1mod*/(i32 0), /*src1*/(i32 -1),
-                                        $src))
+                                        SSrc_i1:$src))
 >;
 
 def : GCNPat <
   (f64 (uint_to_fp i1:$src)),
   (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                                         /*src1mod*/(i32 0), /*src1*/(i32 1),
-                                        $src))
+                                        SSrc_i1:$src))
 >;
 
 //===----------------------------------------------------------------------===//
 // Miscellaneous Patterns
 //===----------------------------------------------------------------------===//
 def : GCNPat <
   (i32 (AMDGPUfp16_zext f16:$src)),
   (COPY $src)

test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
 
 ---
 
 name:            sitofp
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
 
-    ; GCN-LABEL: name: sitofp
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
-    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
-    ; GCN: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec
-    ; GCN: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec
-    ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
-    ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
+    ; WAVE64-LABEL: name: sitofp
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
+    ; WAVE64: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec
+    ; WAVE64: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec
+    ; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
+    ; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
+    ; WAVE32-LABEL: name: sitofp
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
+    ; WAVE32: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec
+    ; WAVE32: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec
+    ; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
+    ; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
     %0:sgpr(s32) = COPY $sgpr0
 
     %1:vgpr(s32) = COPY $vgpr0
 
     %2:vgpr(p1) = COPY $vgpr3_vgpr4
 
     ; sitofp s
     %3:vgpr(s32) = G_SITOFP %0

 legalized: true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $vgpr0
 
-    ; GCN-LABEL: name: sitofp_s32_to_s16_vv
-    ; GCN: liveins: $vgpr0
-    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
-    ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE64-LABEL: name: sitofp_s32_to_s16_vv
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
+    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE32-LABEL: name: sitofp_s32_to_s16_vv
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
+    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_SITOFP %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 ...
 
 ---
 name: sitofp_s32_to_s16_vs
 legalized: true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GCN-LABEL: name: sitofp_s32_to_s16_vs
-    ; GCN: liveins: $sgpr0
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
-    ; GCN: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
-    ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE64-LABEL: name: sitofp_s32_to_s16_vs
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
+    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE32-LABEL: name: sitofp_s32_to_s16_vs
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
+    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s16) = G_SITOFP %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 ...
+
+---
+name: sitofp_s1_to_s32_s_scc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; WAVE64-LABEL: name: sitofp_s1_to_s32_s_scc
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE64: $scc = COPY [[COPY1]]
+    ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 3212836864, implicit $scc
+    ; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
+    ; WAVE32-LABEL: name: sitofp_s1_to_s32_s_scc
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE32: $scc = COPY [[COPY1]]
+    ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 3212836864, implicit $scc
+    ; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = G_CONSTANT i32 0
+    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:sgpr(s32) = G_SITOFP %2
+    $sgpr0 = COPY %3
+...
+
+---
+name: sitofp_s1_to_s16_to_s_scc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; WAVE64-LABEL: name: sitofp_s1_to_s16_to_s_scc
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE64: $scc = COPY [[COPY1]]
+    ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 48128, implicit $scc
+    ; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
+    ; WAVE32-LABEL: name: sitofp_s1_to_s16_to_s_scc
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE32: $scc = COPY [[COPY1]]
+    ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 48128, implicit $scc
+    ; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = G_CONSTANT i32 0
+    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:sgpr(s16) = G_SITOFP %2
+    %4:sgpr(s32) = G_ANYEXT %3
+    $sgpr0 = COPY %4
+...
+
+---
+name: sitofp_s1_to_s64_s_scc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; WAVE64-LABEL: name: sitofp_s1_to_s64_s_scc
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE64: $scc = COPY [[COPY1]]
+    ; WAVE64: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, -4616189618054758400, implicit $scc
+    ; WAVE64: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
+    ; WAVE32-LABEL: name: sitofp_s1_to_s64_s_scc
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE32: $scc = COPY [[COPY1]]
+    ; WAVE32: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, -4616189618054758400, implicit $scc
+    ; WAVE32: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = G_CONSTANT i32 0
+    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:sgpr(s64) = G_SITOFP %2
+    $sgpr0_sgpr1 = COPY %3
+...
+
+---
+name: sitofp_s1_to_s32_v_vcc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: sitofp_s1_to_s32_v_vcc
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 3212836864, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
+    ; WAVE32-LABEL: name: sitofp_s1_to_s32_v_vcc
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 3212836864, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_CONSTANT i32 0
+    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:vgpr(s32) = G_SITOFP %2
+    $vgpr0 = COPY %3
+...
+
+---
+name: sitofp_s1_to_s16_to_v_vcc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: sitofp_s1_to_s16_to_v_vcc
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 3212836864, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE32-LABEL: name: sitofp_s1_to_s16_to_v_vcc
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 3212836864, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_CONSTANT i32 0
+    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:vgpr(s16) = G_SITOFP %2
+    %4:vgpr(s32) = G_ANYEXT %3
+    $vgpr0 = COPY %4
+...
+
+---
+name: sitofp_s1_to_s64_v_vcc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: sitofp_s1_to_s64_v_vcc
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE64: [[V_CVT_F64_I32_e32_:%[0-9]+]]:vreg_64 = V_CVT_F64_I32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
+    ; WAVE64: $vgpr0_vgpr1 = COPY [[V_CVT_F64_I32_e32_]]
+    ; WAVE32-LABEL: name: sitofp_s1_to_s64_v_vcc
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE32: [[V_CVT_F64_I32_e32_:%[0-9]+]]:vreg_64 = V_CVT_F64_I32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
+    ; WAVE32: $vgpr0_vgpr1 = COPY [[V_CVT_F64_I32_e32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_CONSTANT i32 0
+    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:vgpr(s64) = G_SITOFP %2
+    $vgpr0_vgpr1 = COPY %3
+...

test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
 
 ---
 name: uitofp_s32_to_s32_vv
 legalized: true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $vgpr0
 
-    ; GCN-LABEL: name: uitofp_s32_to_s32_vv
-    ; GCN: liveins: $vgpr0
-    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
+    ; WAVE64-LABEL: name: uitofp_s32_to_s32_vv
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
+    ; WAVE32-LABEL: name: uitofp_s32_to_s32_vv
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_UITOFP %0
     $vgpr0 = COPY %1
 ...
 
 ---
 name: uitofp_s32_to_s32_vs
 legalized: true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GCN-LABEL: name: uitofp_s32_to_s32_vs
-    ; GCN: liveins: $sgpr0
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
-    ; GCN: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
+    ; WAVE64-LABEL: name: uitofp_s32_to_s32_vs
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
+    ; WAVE32-LABEL: name: uitofp_s32_to_s32_vs
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s32) = G_UITOFP %0
     $vgpr0 = COPY %1
 ...
 
 ---
 name: uitofp_s32_to_s16_vv
 legalized: true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $vgpr0
 
-    ; GCN-LABEL: name: uitofp_s32_to_s16_vv
-    ; GCN: liveins: $vgpr0
-    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
-    ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE64-LABEL: name: uitofp_s32_to_s16_vv
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
+    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE32-LABEL: name: uitofp_s32_to_s16_vv
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
+    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_UITOFP %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 ...
 
 ---
 name: uitofp_s32_to_s16_vs
 legalized: true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
-    ; GCN-LABEL: name: uitofp_s32_to_s16_vs
-    ; GCN: liveins: $sgpr0
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
-    ; GCN: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
-    ; GCN: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE64-LABEL: name: uitofp_s32_to_s16_vs
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
+    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE32-LABEL: name: uitofp_s32_to_s16_vs
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
+    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s16) = G_UITOFP %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 ...
+
+---
+name: uitofp_s1_to_s32_s_scc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; WAVE64-LABEL: name: uitofp_s1_to_s32_s_scc
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE64: $scc = COPY [[COPY1]]
+    ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 1065353216, implicit $scc
+    ; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
+    ; WAVE32-LABEL: name: uitofp_s1_to_s32_s_scc
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE32: $scc = COPY [[COPY1]]
+    ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 1065353216, implicit $scc
+    ; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = G_CONSTANT i32 0
+    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:sgpr(s32) = G_UITOFP %2
+    $sgpr0 = COPY %3
+...
+
+---
+name: uitofp_s1_to_s16_to_s_scc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; WAVE64-LABEL: name: uitofp_s1_to_s16_to_s_scc
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE64: $scc = COPY [[COPY1]]
+    ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 15360, implicit $scc
+    ; WAVE64: $sgpr0 = COPY [[S_CSELECT_B32_]]
+    ; WAVE32-LABEL: name: uitofp_s1_to_s16_to_s_scc
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE32: $scc = COPY [[COPY1]]
+    ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0 = S_CSELECT_B32 0, 15360, implicit $scc
+    ; WAVE32: $sgpr0 = COPY [[S_CSELECT_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = G_CONSTANT i32 0
+    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:sgpr(s16) = G_UITOFP %2
+    %4:sgpr(s32) = G_ANYEXT %3
+    $sgpr0 = COPY %4
+...
+
+---
+name: uitofp_s1_to_s64_s_scc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; WAVE64-LABEL: name: uitofp_s1_to_s64_s_scc
+    ; WAVE64: liveins: $sgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE64: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE64: $scc = COPY [[COPY1]]
+    ; WAVE64: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, 4607182418800017408, implicit $scc
+    ; WAVE64: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
+    ; WAVE32-LABEL: name: uitofp_s1_to_s64_s_scc
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; WAVE32: S_CMP_EQ_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
+    ; WAVE32: $scc = COPY [[COPY1]]
+    ; WAVE32: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, 4607182418800017408, implicit $scc
+    ; WAVE32: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = G_CONSTANT i32 0
+    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:sgpr(s64) = G_UITOFP %2
+    $sgpr0_sgpr1 = COPY %3
+...
+
+---
+name: uitofp_s1_to_s32_v_vcc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: uitofp_s1_to_s32_v_vcc
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1065353216, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
+    ; WAVE32-LABEL: name: uitofp_s1_to_s32_v_vcc
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1065353216, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_CONSTANT i32 0
+    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:vgpr(s32) = G_UITOFP %2
+    $vgpr0 = COPY %3
+...
+
+---
+name: uitofp_s1_to_s16_to_v_vcc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: uitofp_s1_to_s16_to_v_vcc
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1065353216, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
+    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    ; WAVE32-LABEL: name: uitofp_s1_to_s16_to_v_vcc
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1065353216, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
+    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_CONSTANT i32 0
+    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:vgpr(s16) = G_UITOFP %2
+    %4:vgpr(s32) = G_ANYEXT %3
+    $vgpr0 = COPY %4
+...
+
+---
+name: uitofp_s1_to_s64_v_vcc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: uitofp_s1_to_s64_v_vcc
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE64: [[V_CVT_F64_U32_e32_:%[0-9]+]]:vreg_64 = V_CVT_F64_U32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
+    ; WAVE64: $vgpr0_vgpr1 = COPY [[V_CVT_F64_U32_e32_]]
+    ; WAVE32-LABEL: name: uitofp_s1_to_s64_v_vcc
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec
+    ; WAVE32: [[V_CVT_F64_U32_e32_:%[0-9]+]]:vreg_64 = V_CVT_F64_U32_e32 [[V_CNDMASK_B32_e64_]], implicit $exec
+    ; WAVE32: $vgpr0_vgpr1 = COPY [[V_CVT_F64_U32_e32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_CONSTANT i32 0
+    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
+    %3:vgpr(s64) = G_UITOFP %2
+    $vgpr0_vgpr1 = COPY %3
+...