AMDGPU/GlobalISel: Avoid creating shift of 0 in arg lowering

[arsenm]

Summary

This is sort of papering over the fact that we don't run a combiner
anywhere, but avoiding creating 2 instructions in the first place is
easy.

[arsenm]

ping

[kerbowa]

LGTM

[arsenm]

r373293

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
   Register LiveIn = getLiveInRegister(MRI, Arg->getRegister(), Ty);
 
   if (Arg->isMasked()) {
     // TODO: Should we try to emit this once in the entry block?
     const LLT S32 = LLT::scalar(32);
     const unsigned Mask = Arg->getMask();
     const unsigned Shift = countTrailingZeros<unsigned>(Mask);
 
+    Register AndMaskSrc = LiveIn;
+
+    if (Shift != 0) {
       auto ShiftAmt = B.buildConstant(S32, Shift);
-    auto LShr = B.buildLShr(S32, LiveIn, ShiftAmt);
-    B.buildAnd(DstReg, LShr, B.buildConstant(S32, Mask >> Shift));
+      AndMaskSrc = B.buildLShr(S32, LiveIn, ShiftAmt).getReg(0);
+    }
+
+    B.buildAnd(DstReg, AndMaskSrc, B.buildConstant(S32, Mask >> Shift));
   } else
     B.buildCopy(DstReg, LiveIn);
 
   // Insert the argument copy if it doens't already exist.
   // FIXME: It seems EmitLiveInCopies isn't called anywhere?
   if (!MRI.getVRegDef(LiveIn)) {
     // FIXME: Should have scoped insert pt
     MachineBasicBlock &OrigInsBB = B.getMBB();

test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll

bb1:
   store volatile i32 %id, i32 addrspace(1)* %out
   br label %bb2
 
 bb2:
   ret void
 }
 
 ; ALL-LABEL: {{^}}test_workitem_id_x_func:
-; ALL: v_lshrrev_b32_e32 v2, 0, v2
+; ALL: s_waitcnt
 ; ALL-NEXT: v_and_b32_e32 v2, 0x3ff, v2
 define void @test_workitem_id_x_func(i32 addrspace(1)* %out) #1 {
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   store i32 %id, i32 addrspace(1)* %out
   ret void
 }
 
 ; ALL-LABEL: {{^}}test_workitem_id_y_func: