Implement FastMaterializeAlloca in Mips fast-isel

[vkalintiris]

Summary

Implement the method FastMaterializeAlloca in Mips fast-isel

[vkalintiris]

Add explicit type parameter to load/GEP instructions.

[dsanders]

LGTM with some changes

lib/Target/Mips/MipsFastISel.cpp

260–263 ↗

(On Diff #23843)

This is redundant. DenseMapBase<...>::find() returns DenseMapBase<...>::end() when the key isn't found so there's no need to separately count(AI) and find(AI)

test/CodeGen/Mips/Fast-ISel/fastalloca.ll

4–7 ↗

(On Diff #23843)

Please drop these four lines from the test. It's better to specify the triple on the command line and using the default datalayout will be better if it ever needs to change.

(sorry for the duplicate comment, Phabricator won't let me delete either of them for some reason)

16–29 ↗

(On Diff #23843)

I think we could simplify this test quite a lot. We only want to test alloca instructions so I think we could do something like:

define i32 @foo(i32* %d) {
  %0 = alloca i32, align 4
  store i32 %0, i32* %d, align 4
}

and just check that appropriate addiu's and sw's are created. Obviously, we'd want to test a few layouts.

That said, we've discussed (off-list) your plan to migrate these tests to a style similar to the test/CodeGen/Mips/llvm-ir tests (which tries to test each LLVM-IR instruction with as few dependencies as possible) once the backlog is cleared and I'm happy for this kind of change to be made at that point.

31 ↗

(On Diff #23843)

Nit: indentation

39–57 ↗

(On Diff #23843)

Nit: Not needed.

3–6 ↗

(On Diff #17518)

Please drop these four lines from the test. It's better to specify the triple on the command line and using the default datalayout will be better if it ever needs to change.

llvm/trunk/lib/Target/Mips/MipsFastISel.cpp

explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
     Context = &funcInfo.Fn->getContext();
     TargetSupported =
         ((TM.getRelocationModel() == Reloc::PIC_) &&
          ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
           (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
     UnsupportedFPMode = Subtarget->isFP64bit();
   }
 
+  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
   unsigned fastMaterializeConstant(const Constant *C) override;
   bool fastSelectInstruction(const Instruction *I) override;
 
 #include "MipsGenFastISel.inc"
 };
 } // end anonymous namespace.
 
 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
 
   if (!RHSReg)
     return 0;
 
   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
   return ResultReg;
 }
 
+unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
+  assert(TLI.getValueType(AI->getType(), true) == MVT::i32 &&
+         "Alloca should always return a pointer.");
+
+  DenseMap<const AllocaInst *, int>::iterator SI =
+      FuncInfo.StaticAllocaMap.find(AI);
+
+  if (SI != FuncInfo.StaticAllocaMap.end()) {
+    unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
+            ResultReg)
+        .addFrameIndex(SI->second)
+        .addImm(0);
+    return ResultReg;
+  }
+
+  return 0;
+}
+
 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
     return 0;
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   const ConstantInt *CI = cast<ConstantInt>(C);
   int64_t Imm;
   if ((VT != MVT::i1) && CI->isNegative())
     Imm = CI->getSExtValue();

llvm/trunk/test/CodeGen/Mips/Fast-ISel/fastalloca.ll

+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+
+%struct.x = type { i32 }
+
+@i = common global i32 0, align 4
+
+define i32 @foobar(i32 signext %x) {
+entry:
+; CHECK-LABEL: foobar:
+  %retval = alloca i32, align 4
+  %x.addr = alloca i32, align 4
+  %a = alloca %struct.x, align 4
+  %c = alloca %struct.x*, align 4
+  store i32 %x, i32* %x.addr, align 4
+  %x1 = getelementptr inbounds %struct.x, %struct.x* %a, i32 0, i32 0
+  %0 = load i32, i32* %x.addr, align 4
+  store i32 %0, i32* %x1, align 4
+  store %struct.x* %a, %struct.x** %c, align 4
+  %1 = load %struct.x*, %struct.x** %c, align 4
+  %x2 = getelementptr inbounds %struct.x, %struct.x* %1, i32 0, i32 0
+  %2 = load i32, i32* %x2, align 4
+  store i32 %2, i32* @i, align 4
+  %3 = load i32, i32* %retval
+; CHECK-DAG:    lw      $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
+; CHECK-DAG:    addiu   $[[A_ADDR:[0-9]+]], $sp, 8
+; CHECK-DAG:    sw      $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp)
+; CHECK-DAG:    lw      $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp)
+; CHECK-DAG:    lw      $[[A_X:[0-9]+]], 0($[[A_ADDR2]])
+; CHECK-DAG:    sw      $[[A_X]], 0($[[I_ADDR]])
+  ret i32 %3
+}