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Differential D67181

[MIPS GlobalISel] Select G_FENCE
ClosedPublic

Authored by Petar.Avramovic on Sep 4 2019, 8:20 AM.

Details

Reviewers
atanasyan
petarj
Commits
rL371056: [MIPS GlobalISel] Select G_FENCE
rGa4bfc8dfdaef: [MIPS GlobalISel] Select G_FENCE
Summary

G_FENCE comes form fence instruction. For MIPS fence is generated in
AtomicExpandPass when atomic instruction gets surrounded with fence
instruction when needed.
G_FENCE arguments don't have LLT, because of that there is no job for
legalizer and regbankselect. Instruction select G_FENCE for MIPS32.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Sep 4 2019, 8:20 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 4 2019, 8:20 AM
Herald added subscribers: llvm-commits, jfb, jrtc27 and 3 others. · View Herald Transcript
atanasyan accepted this revision.Sep 4 2019, 1:16 PM

LGTM

This revision is now accepted and ready to land.Sep 4 2019, 1:16 PM
Closed by commit rGa4bfc8dfdaef: [MIPS GlobalISel] Select G_FENCE (authored by Petar.Avramovic). · Explain WhySep 5 2019, 4:20 AM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: hiraditya. · View Herald TranscriptSep 5 2019, 4:20 AM

Revision Contents

PathSize
llvm/
lib/
Target/
Mips/
4 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
31 lines
legalizer/
29 lines
llvm-ir/
13 lines
regbankselect/
30 lines

Diff 218888

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 746 Lines • ▼ Show 20 Lines MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode))
.addUse(Mips::FCC0) .addUse(Mips::FCC0)
.addUse(TrueInReg); .addUse(TrueInReg);
if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
return false; return false;
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
} }
case G_FENCE: {
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
break;
}
default: default:
return false; return false;
} }
I.eraseFromParent(); I.eraseFromParent();
return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
} }
namespace llvm { namespace llvm {
InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM, InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM,
MipsSubtarget &Subtarget, MipsSubtarget &Subtarget,
MipsRegisterBankInfo &RBI) { MipsRegisterBankInfo &RBI) {
return new MipsInstructionSelector(TM, Subtarget, RBI); return new MipsInstructionSelector(TM, Subtarget, RBI);
} }
} // end namespace llvm } // end namespace llvm

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @atomic_load_i32(i32* %ptr) { ret void }
...
---
name: atomic_load_i32
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
liveins: $a0
; MIPS32-LABEL: name: atomic_load_i32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load monotonic 4 from %ir.ptr)
; MIPS32: SYNC 0
; MIPS32: $v0 = COPY [[LW]]
; MIPS32: RetRA implicit $v0
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
G_FENCE 4, 1
$v0 = COPY %1(s32)
RetRA implicit $v0
...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @atomic_load_i32(i32* %ptr) { ret void }
...
---
name: atomic_load_i32
alignment: 2
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
liveins: $a0
; MIPS32-LABEL: name: atomic_load_i32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4 from %ir.ptr)
; MIPS32: G_FENCE 4, 1
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
G_FENCE 4, 1
$v0 = COPY %1(s32)
RetRA implicit $v0
...

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fence.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
define i32 @atomic_load_i32(i32* %ptr) {
; MIPS32-LABEL: atomic_load_i32:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: sync
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
%val = load atomic i32, i32* %ptr acquire, align 4
ret i32 %val
}

llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @atomic_load_i32(i32* %ptr) { ret void }
...
---
name: atomic_load_i32
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
liveins: $a0
; MIPS32-LABEL: name: atomic_load_i32
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4 from %ir.ptr)
; MIPS32: G_FENCE 4, 1
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load monotonic 4 from %ir.ptr)
G_FENCE 4, 1
$v0 = COPY %1(s32)
RetRA implicit $v0
...